SPRUIY2 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
      3. 3.2.3 RTINT (Real Time Interrupt)
      4. 3.2.4 INT (Low-Priority Interrupt)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Pipeline
    1. 4.1  Introduction
    2. 4.2  Decoupled Pipeline Phases
    3. 4.3  Dual Instruction Prefetch Buffers
    4. 4.4  Pipeline Advancement and Stalls
    5. 4.5  Pipeline Hazards and Protection Mechanisms
    6. 4.6  Register Updates and Corresponding Pipeline Phases
    7. 4.7  Register Reads and Writes During Normal Operation
    8. 4.8  D2 Read Protection
    9. 4.9  E1 Read Protection
    10. 4.10 WAW Protection
    11. 4.11 Protection During Interrupt
  7. 5Addressing Modes
    1. 5.1 Addressing Modes Overview
      1. 5.1.1 Documentation and Implementation
      2. 5.1.2 List of Addressing Mode Types
        1. 5.1.2.1 Additional Types of Addressing
      3. 5.1.3 Addressing Modes Summarized
    2. 5.2 Addressing Mode Fields
      1. 5.2.1 ADDR1 Field
      2. 5.2.2 ADDR2 Field
      3. 5.2.3 ADDR3 Field
      4. 5.2.4 DIRM Field
      5. 5.2.5 Additional Fields
    3. 5.3 Alignment and Pipeline Considerations
      1. 5.3.1 Alignment
      2. 5.3.2 Pipeline Considerations
    4. 5.4 Types of Addressing Modes
      1. 5.4.1 Direct Addressing
      2. 5.4.2 Pointer Addressing
        1. 5.4.2.1 Pointer Addressing with #Immediate Offset
        2. 5.4.2.2 Pointer Addressing with Pointer Offset
        3. 5.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 5.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 5.4.3 Stack Addressing
        1. 5.4.3.1 Allocating and De-allocating Stack Space
      4. 5.4.4 Circular Addressing Instruction
      5. 5.4.5 Bit Reversed Addressing Instruction
  8. 6Safety and Security Unit (SSU)
    1. 6.1 SSU Overview
    2. 6.2 Links and Task Isolation
    3. 6.3 Sharing Data Outside Task Isolation Boundary
    4. 6.4 Protected Call and Return
  9. 7Emulation
    1. 7.1 Overview of Emulation Features
    2. 7.2 Debug Terminology
    3. 7.3 Debug Interface
    4. 7.4 Execution Control Mode
    5. 7.5 Breakpoints, Watchpoints, and Counters
      1. 7.5.1 Software Breakpoint
      2. 7.5.2 Hardware Debugging Resources
        1. 7.5.2.1 Hardware Breakpoint
        2. 7.5.2.2 Hardware Watchpoint
        3. 7.5.2.3 Benchmark Counters
      3. 7.5.3 PC Trace
  10. 8Revision History

4.1 Introduction

When executing a program, the C29x CPU performs these basic operations:

  • Fetches instructions from program memory
  • Decodes instructions
  • Reads data values from memory or from CPU registers
  • Executes instructions
  • Writes results to memory or to CPU registers

The C29x CPU has 9 pipeline stages. Each of these stages can have one or more pipeline stages to achieve high frequency operation and each of these pipeline stages perform a specific function to execute a program. At any time, there can be up to nine instructions being carried out, each in a different phase of completion. Figure 4-1 shows the different stages of C29x CPU pipeline and how each stage is decoupled from other.

Table 4-1 provides description for each of the nine phases of the C29x CPU pipeline.

F29x C29x CPU Pipeline Stages Figure 4-1 C29x CPU Pipeline Stages
Table 4-1 C29x CPU Pipeline Stages
Pipeline Stage C29x CPU Operation
Fetch 1 (F1) Instruction fetch address is placed on program address bus. CPU does look ahead fetches to improve the overall throughput.
Fetch 2 (F2) Instruction returned from memory is latched into CPU. Instructions fetched from memory are stored in 4-level deep instruction buffer. Fetch unit has two 4 ˟ 128-bit instruction buffers. One is meant for normal execution and other is meant for delayed branches.
Decode 1 (D1) Following key operations are handled in this phase
  • Fetched instructions words are checked for errors and corrected if error checking is enabled.
  • Decode instruction boundaries and packets
  • Perform Instruction mapping
  • Security errors are checked
  • Perform Safe interconnect checks on Program Bus
Decode 2 (D2) This is a very critical phase of the pipeline. Any instruction packet that enters this phase of the pipeline always completes all operations unless the CPU undergoes a reset in between. The following key operations happen in this phase of the pipeline.
  • Arbitration between instruction execution, Debug commands, pending interrupts and exceptions.
  • All discontinuities and Control flow decisions.
  • Address generation for Reads and writes.
  • Compute operations involving the Ax registers.
  • Detection of Secure call/return and Interrupt entry violations.
  • Detecting the Pipeline hazards and managing the pipeline until hazards are resolved
Read 1 (R1)

Place read request on Read 1 and Read 2 buses

Stall the CPU pipeline if memory or peripheral is not ready
Read 2 (R2) Read data is returned to CPU.
Read 3 (R3)

Perform ECC check on read data

Perform Safe interconnect checks on Read Buses
Execute 1 (E1)

Load Ax, Dx, Mx registers from memory

Operations on Dx and Mx Registers

CPI load operations

Generate Write data for store operation

ESTS, Dx, and Mx register updates resulting from 1 cycle operations
Execute 2 (E2)

Write (W)

Place write request Write buses

Stall the CPU pipeline on if memory or peripheral is not ready

ESTS, Dx, and Mx register updates resulting from 2 cycle operations
Execute 3 (E3)

ESTS, Dx, and Mx register updates resulting from 3 cycle operations

Perform Safe interconnect check on Write bus
Execute 4 (E4) ESTS, Dx, and Mx register updates resulting from 4 cycle operations
Execute 5 (E5) ESTS, Dx, and Mx register updates resulting from 5 cycle operations
Execute 6 (E6) ESTS, Dx, and Mx register updates resulting from 6 cycle operations