SPRUIY2 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
      3. 3.2.3 RTINT (Real Time Interrupt)
      4. 3.2.4 INT (Low-Priority Interrupt)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Pipeline
    1. 4.1  Introduction
    2. 4.2  Decoupled Pipeline Phases
    3. 4.3  Dual Instruction Prefetch Buffers
    4. 4.4  Pipeline Advancement and Stalls
    5. 4.5  Pipeline Hazards and Protection Mechanisms
    6. 4.6  Register Updates and Corresponding Pipeline Phases
    7. 4.7  Register Reads and Writes During Normal Operation
    8. 4.8  D2 Read Protection
    9. 4.9  E1 Read Protection
    10. 4.10 WAW Protection
    11. 4.11 Protection During Interrupt
  7. 5Addressing Modes
    1. 5.1 Addressing Modes Overview
      1. 5.1.1 Documentation and Implementation
      2. 5.1.2 List of Addressing Mode Types
        1. 5.1.2.1 Additional Types of Addressing
      3. 5.1.3 Addressing Modes Summarized
    2. 5.2 Addressing Mode Fields
      1. 5.2.1 ADDR1 Field
      2. 5.2.2 ADDR2 Field
      3. 5.2.3 ADDR3 Field
      4. 5.2.4 DIRM Field
      5. 5.2.5 Additional Fields
    3. 5.3 Alignment and Pipeline Considerations
      1. 5.3.1 Alignment
      2. 5.3.2 Pipeline Considerations
    4. 5.4 Types of Addressing Modes
      1. 5.4.1 Direct Addressing
      2. 5.4.2 Pointer Addressing
        1. 5.4.2.1 Pointer Addressing with #Immediate Offset
        2. 5.4.2.2 Pointer Addressing with Pointer Offset
        3. 5.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 5.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 5.4.3 Stack Addressing
        1. 5.4.3.1 Allocating and De-allocating Stack Space
      4. 5.4.4 Circular Addressing Instruction
      5. 5.4.5 Bit Reversed Addressing Instruction
  8. 6Safety and Security Unit (SSU)
    1. 6.1 SSU Overview
    2. 6.2 Links and Task Isolation
    3. 6.3 Sharing Data Outside Task Isolation Boundary
    4. 6.4 Protected Call and Return
  9. 7Emulation
    1. 7.1 Overview of Emulation Features
    2. 7.2 Debug Terminology
    3. 7.3 Debug Interface
    4. 7.4 Execution Control Mode
    5. 7.5 Breakpoints, Watchpoints, and Counters
      1. 7.5.1 Software Breakpoint
      2. 7.5.2 Hardware Debugging Resources
        1. 7.5.2.1 Hardware Breakpoint
        2. 7.5.2.2 Hardware Watchpoint
        3. 7.5.2.3 Benchmark Counters
      3. 7.5.3 PC Trace
  10. 8Revision History

3.2.3 RTINT (Real Time Interrupt)

The RTINT (real time interrupt) is the third-highest priority interrupt line, and receives signals driven by an interrupt expansion and aggregation unit (the PIPE module for most C29x CPU systems).

Blocking and Masking

RTINT sources are able to be masked, but the actual RTINT line connected to the CPU can never be blocked/disabled by user code. There is no global enable/disable bit for the RTINT line in the CPU. Because of this, any interrupts that are received on the RTINT line are directly passed to the CPU for prioritization. Priority is then decided among any interrupts on the NMI or INT lines. The RTINT signal line can only be stopped from nesting within INTs by using the ATOMIC instruction within the INT ISR, and only for a finite number of instruction packets. However, interrupts ISRs can be prioritized/blocked before the interrupts reach the RTINT line using the external PIPE module.

Signal Propagation

The PIPE module provides external interrupt aggregation and arbitration for the RTINT and INT lines. This allows for many signals to be categorized as "real-time interrupts" ("RTINT") or "low-priority interrupts" ("INT"), and then prioritized before passing to the CPUs RTINT or INT interrupt line.

The PIPE effectively multiplexes the single RTINT CPU interrupt line to be able to receive from multiple incoming RTINT interrupts in the appropriate order.

The module allows for enabling and disabling of RTINT signals before the signals reach the RTINT line of the CPU. The module also allows nesting capability amongst other interrupts categorized as RTINT. See the F29H85x and F29P58x Real-Time Microcontrollers Technical Reference Manual for details on the PIPE module features.

Stack

This interrupt line uses the protected Real Time Interrupt Stack for context save and restore. This SSU-protected (Safety and Security Unit) stack has protection features to prevent stack overflow during nesting, when nesting is requested by the PIPE module. The WARNRTISP and MAXRTISP CPU registers serve this purpose in the C29x CPU system.

This protection limits nesting of RTINT up to the number of levels supported by the RTINT Stack minus one level (which is always reserved for NMI interrupt).

For security, the SSU protection of the RTINT Stack are designed so that the contents of the stack are not visible. Registers are also zeroed to prevent visibility into what was happening before the interrupt was serviced.

See Section 2.4 for details on stack overflow protection using the WARNRTISP and MAXRTISP registers.

Required Instructions

NMI and RTINT interrupts can potentially have the respective interrupt service routines residing in a different LINK/STACK. Therefore NMI and RTINT interrupt service routines (ISRs) require that the first instruction packet of every vector address contain the (ISR1.PROT || ISR2.PROT) instructions. The CPU pipeline control hardware checks for these required instructions and generates a FAULT, if these instructions are not the first instruction packet of the ISR. These required instructions are inserted automatically by the compiler, but must be configured to do so for the appropriate vectors within a separate security settings file. See Section 3.6 for more details.

ISR1.PROT also initializes the stack pointer (A15) to the appropriate STACK by performing the following operation: A15 = SECSPn (where n is the current STACK indicated by ISTS.CURRSP).

For more details on the security implications of the LINK/STACK/ZONE and memory space for CPU interrupts, see Section 3.6.