SPRUIY4B February 2023 – May 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1
Table 4-115 lists the memory-mapped registers for the MEM_CFG_REGS registers. All register offset addresses not listed in Table 4-115 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | DxLOCK | Dedicated RAM Config Lock Register | EALLOW | Go |
2h | DxCOMMIT | Dedicated RAM Config Lock Commit Register | EALLOW | Go |
8h | DxACCPROT0 | Dedicated RAM Config Register | EALLOW | Go |
Ah | DxACCPROT1 | Dedicated RAM Config Register | EALLOW | Go |
10h | DxTEST | Dedicated RAM TEST Register | Go | |
12h | DxINIT | Dedicated RAM Init Register | EALLOW | Go |
14h | DxINITDONE | Dedicated RAM InitDone Status Register | Go | |
16h | DxRAMTEST_LOCK | Lock register to Dx RAM TEST registers | Go | |
20h | LSxLOCK | Local Shared RAM Config Lock Register | EALLOW | Go |
22h | LSxCOMMIT | Local Shared RAM Config Lock Commit Register | EALLOW | Go |
28h | LSxACCPROT0 | Local Shared RAM Config Register 0 | EALLOW | Go |
30h | LSxTEST | Local Shared RAM TEST Register | Go | |
32h | LSxINIT | Local Shared RAM Init Register | EALLOW | Go |
34h | LSxINITDONE | Local Shared RAM InitDone Status Register | Go | |
36h | LSxRAMTEST_LOCK | Lock register to LSx RAM TEST registers | Go | |
A0h | ROM_LOCK | ROM Config Lock Register | Go | |
A2h | ROM_TEST | ROM TEST Register | Go | |
A4h | ROM_FORCE_ERROR | ROM Force Error register | Go |
Complex bit access types are encoded to fit into small table cells. Table 4-116 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
DxLOCK is shown in Figure 4-103 and described in Table 4-117.
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Dedicated RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_PIEVECT | RESERVED | RESERVED | LOCK_M1 | LOCK_M0 | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | LOCK_PIEVECT | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for PIEVECT RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | LOCK_M1 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for M1 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
0 | LOCK_M0 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for M0 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
DxCOMMIT is shown in Figure 4-104 and described in Table 4-118.
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Dedicated RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMMIT_PIEVECT | RESERVED | RESERVED | COMMIT_M1 | COMMIT_M0 | ||
R-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | COMMIT_PIEVECT | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for PIEVECT RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
3 | RESERVED | R/WSonce | 0h | Reserved |
2 | RESERVED | R/WSonce | 0h | Reserved |
1 | COMMIT_M1 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for M1 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_M0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for M0 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
DxACCPROT0 is shown in Figure 4-105 and described in Table 4-119.
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Dedicated RAM Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_M1 | FETCHPROT_M1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_M0 | FETCHPROT_M0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23-18 | RESERVED | R | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_M1 | R/W | 0h | CPU WR Protection For M1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are block. Reset type: SYSRSn |
8 | FETCHPROT_M1 | R/W | 0h | Fetch Protection For M1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_M0 | R/W | 0h | CPU WR Protection For M0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are block. Reset type: SYSRSn |
0 | FETCHPROT_M0 | R/W | 0h | Fetch Protection For M0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
DxACCPROT1 is shown in Figure 4-106 and described in Table 4-120.
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Dedicated RAM Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_PIEVECT | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_PIEVECT | R/W | 0h | CPU Write Protection For PIEVECT RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | RESERVED | R/W | 0h | Reserved |
DxTEST is shown in Figure 4-107 and described in Table 4-121.
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Dedicated RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TEST_PIEVECT | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | TEST_M1 | TEST_M0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9-8 | TEST_PIEVECT | R/W | 0h | Selects the defferent modes for PIEVECT RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | TEST_M1 | R/W | 0h | Selects the defferent modes for M1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
1-0 | TEST_M0 | R/W | 0h | Selects the defferent modes for M0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
DxINIT is shown in Figure 4-108 and described in Table 4-122.
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Dedicated RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_PIEVECT | RESERVED | RESERVED | INIT_M1 | INIT_M0 | ||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | INIT_PIEVECT | R-0/W1S | 0h | RAM Initialization control for PIEVECT RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | INIT_M1 | R-0/W1S | 0h | RAM Initialization control for M1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_M0 | R-0/W1S | 0h | RAM Initialization control for M0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
DxINITDONE is shown in Figure 4-109 and described in Table 4-123.
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Dedicated RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITDONE_PIEVECT | RESERVED | RESERVED | INITDONE_M1 | INITDONE_M0 | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | INITDONE_PIEVECT | R | 0h | RAM Initialization status for PIEVECT RAM: 0: RAM Initialization has completed. 1: RAM Initialization has completed. Reset type: SYSRSn |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | INITDONE_M1 | R | 0h | RAM Initialization status for M1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization has completed. Reset type: SYSRSn |
0 | INITDONE_M0 | R | 0h | RAM Initialization status for M0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
DxRAMTEST_LOCK is shown in Figure 4-110 and described in Table 4-124.
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Lock register to Dx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PIEVECT | RESERVED | RESERVED | M1 | M0 | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-5 | RESERVED | R | 0h | Reserved |
4 | PIEVECT | R/W | 0h | 0: Allows writes to DxTEST.TEST_PIEVECT field. 1: Blocks writes to DxTEST.TEST_PIEVECT field Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | M1 | R/W | 0h | 0: Allows writes to DxTEST.TEST_M1 field. 1: Blocks writes to DxTEST.TEST_M1 field Reset type: SYSRSn |
0 | M0 | R/W | 0h | 0: Allows writes to DxTEST.TEST_M0 field. 1: Blocks writes to DxTEST.TEST_M0 field Reset type: SYSRSn |
LSxLOCK is shown in Figure 4-111 and described in Table 4-125.
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Local Shared RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | LOCK_LS1 | LOCK_LS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | LOCK_LS1 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS1 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
0 | LOCK_LS0 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS0 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
LSxCOMMIT is shown in Figure 4-112 and described in Table 4-126.
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Local Shared RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | COMMIT_LS1 | COMMIT_LS0 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R/WSonce | 0h | Reserved |
6 | RESERVED | R/WSonce | 0h | Reserved |
5 | RESERVED | R/WSonce | 0h | Reserved |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | RESERVED | R/WSonce | 0h | Reserved |
2 | RESERVED | R/WSonce | 0h | Reserved |
1 | COMMIT_LS1 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS1 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_LS0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS0 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
LSxACCPROT0 is shown in Figure 4-113 and described in Table 4-127.
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Local Shared RAM Config Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_LS1 | FETCHPROT_LS1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_LS0 | FETCHPROT_LS0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23-18 | RESERVED | R | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_LS1 | R/W | 0h | CPU WR Protection For LS1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_LS1 | R/W | 0h | Fetch Protection For LS1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_LS0 | R/W | 0h | CPU WR Protection For LS0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_LS0 | R/W | 0h | Fetch Protection For LS0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
LSxTEST is shown in Figure 4-114 and described in Table 4-128.
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Local Shared RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | TEST_LS1 | TEST_LS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | RESERVED | R/W | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | TEST_LS1 | R/W | 0h | Selects the defferent modes for LS1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
1-0 | TEST_LS0 | R/W | 0h | Selects the defferent modes for LS0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
LSxINIT is shown in Figure 4-115 and described in Table 4-129.
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Local Shared RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | INIT_LS1 | INIT_LS0 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | RESERVED | R-0/W1S | 0h | Reserved |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | INIT_LS1 | R-0/W1S | 0h | RAM Initialization control for LS1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_LS0 | R-0/W1S | 0h | RAM Initialization control for LS0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
LSxINITDONE is shown in Figure 4-116 and described in Table 4-130.
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Local Shared RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | INITDONE_LS1 | INITDONE_LS0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | INITDONE_LS1 | R | 0h | RAM Initialization status for LS1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | INITDONE_LS0 | R | 0h | RAM Initialization status for LS0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
LSxRAMTEST_LOCK is shown in Figure 4-117 and described in Table 4-131.
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Lock register to LSx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||||||||||
R-0/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | LS1 | LS0 | |||||||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | LS1 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS1 field. 1: Blocks writes to LSxTEST.TEST_LS1 field. Reset type: SYSRSn |
0 | LS0 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS0 field. 1: Blocks writes to LSxTEST.TEST_LS0 field. Reset type: SYSRSn |
ROM_LOCK is shown in Figure 4-118 and described in Table 4-132.
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ROM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | LOCK_SECUREROM | LOCK_BOOTROM | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | LOCK_SECUREROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of SECUREROM 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
0 | LOCK_BOOTROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of BOOTROM 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
ROM_TEST is shown in Figure 4-119 and described in Table 4-133.
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ROM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | TEST_SECUREROM | TEST_BOOTROM | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | TEST_SECUREROM | R/W | 0h | Selects the different modes for SECUREROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: SYSRSn |
1-0 | TEST_BOOTROM | R/W | 0h | Selects the different modes for BOOTROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: SYSRSn |
ROM_FORCE_ERROR is shown in Figure 4-120 and described in Table 4-134.
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ROM Force Error register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | FORCE_SECUREROM_ERROR | FORCE_BOOTROM_ERROR | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | FORCE_SECUREROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: SYSRSn |
0 | FORCE_BOOTROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: SYSRSn |