SPRUIY4B February   2023  – May 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 VCRC Unit
  5. 3 Lockstep Compare Module (LCM)
    1. 3.1 Introduction
      1. 3.1.1 Features
      2. 3.1.2 Block Diagram
    2. 3.2 Enabling LCM Comparators
    3. 3.3 Disabling LCM Redundant Module
    4. 3.4 LCM Error Handling
    5. 3.5 LCM Error Flags
    6. 3.6 Debug Mode with LCM
    7. 3.7 Register Parity Error Protection
    8. 3.8 Functional Logic
      1. 3.8.1 Comparator Logic
      2. 3.8.2 Self-Test Logic
        1. 3.8.2.1 Match Test Mode
        2. 3.8.2.2 Mismatch Test Mode
      3. 3.8.3 Error Injection Tests
        1. 3.8.3.1 Comparator Error Force Test
        2. 3.8.3.2 Register Parity Error Test
    9. 3.9 LCM Registers
      1. 3.9.1 LCM Base Address Table
      2. 3.9.2 LCM_REGS Registers
      3. 3.9.3 LCM Registers to Driverlib Functions
  6. 4 System Control and Interrupts
    1. 4.1  Introduction
      1. 4.1.1 SYSCTL Related Collateral
      2. 4.1.2 LOCK Protection on System Configuration Registers
      3. 4.1.3 EALLOW Protection
    2. 4.2  Power Management
    3. 4.3  Device Identification and Configuration Registers
    4. 4.4  Resets
      1. 4.4.1  Reset Sources
      2. 4.4.2  External Reset (XRS)
      3. 4.4.3  Simulate External Reset (SIMRESET.XRS)
      4. 4.4.4  Power-On Reset (POR)
      5. 4.4.5  Brown-Out-Reset (BOR)
      6. 4.4.6  Debugger Reset (SYSRS)
      7. 4.4.7  Simulate CPU Reset
      8. 4.4.8  Watchdog Reset (WDRS)
      9. 4.4.9  NMI Watchdog Reset (NMIWDRS)
      10. 4.4.10 DCSM Safe Code Copy Reset (SCCRESET)
    5. 4.5  Peripheral Interrupts
      1. 4.5.1 Interrupt Concepts
      2. 4.5.2 Interrupt Architecture
        1. 4.5.2.1 Peripheral Stage
        2. 4.5.2.2 PIE Stage
        3. 4.5.2.3 CPU Stage
      3. 4.5.3 Interrupt Entry Sequence
      4. 4.5.4 Configuring and Using Interrupts
        1. 4.5.4.1 Enabling Interrupts
        2. 4.5.4.2 Handling Interrupts
        3. 4.5.4.3 Disabling Interrupts
        4. 4.5.4.4 Nesting Interrupts
        5. 4.5.4.5 Vector Address Validity Check
      5. 4.5.5 PIE Channel Mapping
      6. 4.5.6 PIE Interrupt Priority
        1. 4.5.6.1 Channel Priority
        2. 4.5.6.2 Group Priority
      7. 4.5.7 System Error
      8. 4.5.8 Vector Tables
    6. 4.6  Exceptions and Non-Maskable Interrupts
      1. 4.6.1 Configuring and Using NMIs
      2. 4.6.2 Emulation Considerations
      3. 4.6.3 NMI Sources
        1. 4.6.3.1 Missing Clock Detection
        2. 4.6.3.2 RAM Uncorrectable Error
        3. 4.6.3.3 Flash Uncorrectable ECC Error
        4. 4.6.3.4 Software-Forced Error
      4. 4.6.4 Illegal Instruction Trap (ITRAP)
      5. 4.6.5 ERRORSTS Pin
    7. 4.7  Clocking
      1. 4.7.1  Clock Sources
        1. 4.7.1.1 Primary Internal Oscillator (INTOSC2)
          1. 4.7.1.1.1 External Resistor (ExtR) Mode
            1. 4.7.1.1.1.1 INTOSC2 with External Precision Resistor – ExtR
        2. 4.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 4.7.1.3 Auxiliary Clock Input (AUXCLKIN)
        4. 4.7.1.4 External Oscillator (XTAL)
      2. 4.7.2  Derived Clocks
        1. 4.7.2.1 Oscillator Clock (OSCCLK)
        2. 4.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 4.7.3  Device Clock Domains
        1. 4.7.3.1 System Clock (PLLSYSCLK)
        2. 4.7.3.2 CPU Clock (CPUCLK)
        3. 4.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 4.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 4.7.3.5 CAN Bit Clock
        6. 4.7.3.6 CPU Timer2 Clock (TIMER2CLK)
      4. 4.7.4  XCLKOUT
      5. 4.7.5  Clock Connectivity
      6. 4.7.6  Clock Source and PLL Setup
      7. 4.7.7  Using an External Crystal or Resonator
      8. 4.7.8  Using an External Oscillator
      9. 4.7.9  Using an External Resistor (ExtR) With Internal Oscillator
      10. 4.7.10 Choosing PLL Settings
      11. 4.7.11 System Clock Setup
      12. 4.7.12 SYS PLL Bypass
      13. 4.7.13 Clock (OSCCLK) Failure Detection
        1. 4.7.13.1 Missing Clock Detection
    8. 4.8  32-Bit CPU Timers 0/1/2
    9. 4.9  Watchdog Timer
      1. 4.9.1 Servicing the Watchdog Timer
      2. 4.9.2 Minimum Window Check
      3. 4.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 4.9.4 Watchdog Operation in Low Power Modes
      5. 4.9.5 Emulation Considerations
    10. 4.10 Low-Power Modes
      1. 4.10.1 Clock-Gating Low-Power Modes
      2. 4.10.2 IDLE
      3. 4.10.3 STANDBY
      4. 4.10.4 HALT
    11. 4.11 Memory Controller Module
      1. 4.11.1 Functional Description
        1. 4.11.1.1 Dedicated RAM (Mx RAM)
        2. 4.11.1.2 Local Shared RAM (LSx RAM)
        3. 4.11.1.3 Access Protection
          1. 4.11.1.3.1 CPU Fetch Protection
          2. 4.11.1.3.2 CPU Write Protection
          3. 4.11.1.3.3 CPU Read Protection
        4. 4.11.1.4 Memory Error Detection, Correction, and Error Handling
          1. 4.11.1.4.1 Error Detection and Correction
          2. 4.11.1.4.2 Error Handling
        5. 4.11.1.5 Application Test Hooks for Error Detection and Correction
        6. 4.11.1.6 RAM Initialization
    12. 4.12 JTAG
      1. 4.12.1 JTAG Noise and TAP_STATUS
    13. 4.13 System Control Register Configuration Restrictions
    14. 4.14 Software
      1. 4.14.1 SYSCTL Examples
        1. 4.14.1.1 Missing clock detection (MCD)
        2. 4.14.1.2 XCLKOUT (External Clock Output) Configuration
      2. 4.14.2 TIMER Examples
        1. 4.14.2.1 CPU Timers
        2. 4.14.2.2 CPU Timers
      3. 4.14.3 MEMCFG Examples
        1. 4.14.3.1 Correctable & Uncorrectable Memory Error Handling
      4. 4.14.4 INTERRUPT Examples
        1. 4.14.4.1 External Interrupts (ExternalInterrupt)
        2. 4.14.4.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
        3. 4.14.4.3 CPU Timer Interrupt Software Prioritization
        4. 4.14.4.4 EPWM Real-Time Interrupt
      5. 4.14.5 LPM Examples
        1. 4.14.5.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO
        2. 4.14.5.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog
        3. 4.14.5.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO
        4. 4.14.5.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog
        5. 4.14.5.5 Low Power Modes: Halt Mode and Wakeup using GPIO
        6. 4.14.5.6 Low Power Modes: Halt Mode and Wakeup
      6. 4.14.6 WATCHDOG Examples
        1. 4.14.6.1 Watchdog
    15. 4.15 System Control Registers
      1. 4.15.1  SYSCTRL Base Address Table
      2. 4.15.2  ACCESS_PROTECTION_REGS Registers
      3. 4.15.3  CLK_CFG_REGS Registers
      4. 4.15.4  CPU_SYS_REGS Registers
      5. 4.15.5  CPUTIMER_REGS Registers
      6. 4.15.6  DEV_CFG_REGS Registers
      7. 4.15.7  MEM_CFG_REGS Registers
      8. 4.15.8  MEMORY_ERROR_REGS Registers
      9. 4.15.9  NMI_INTRUPT_REGS Registers
      10. 4.15.10 PIE_CTRL_REGS Registers
      11. 4.15.11 SYNC_SOC_REGS Registers
      12. 4.15.12 SYS_STATUS_REGS Registers
      13. 4.15.13 TEST_ERROR_REGS Registers
      14. 4.15.14 UID_REGS Registers
      15. 4.15.15 WD_REGS Registers
      16. 4.15.16 XINT_REGS Registers
      17. 4.15.17 Register to Driverlib Function Mapping
        1. 4.15.17.1 ASYSCTL Registers to Driverlib Functions
        2. 4.15.17.2 CPUTIMER Registers to Driverlib Functions
        3. 4.15.17.3 MEMCFG Registers to Driverlib Functions
        4. 4.15.17.4 NMI Registers to Driverlib Functions
        5. 4.15.17.5 PIE Registers to Driverlib Functions
        6. 4.15.17.6 SYSCTL Registers to Driverlib Functions
        7. 4.15.17.7 XINT Registers to Driverlib Functions
  7. 5 ROM Code and Peripheral Booting
    1. 5.1 Introduction
      1. 5.1.1 ROM Related Collateral
    2. 5.2 Device Boot Sequence
    3. 5.3 Device Boot Modes
      1. 5.3.1 Default Boot Modes
      2. 5.3.2 Custom Boot Modes
    4. 5.4 Device Boot Configurations
      1. 5.4.1 Configuring Boot Mode Pins
      2. 5.4.2 Configuring Boot Mode Table Options
      3. 5.4.3 Boot Mode Example Use Cases
        1. 5.4.3.1 Zero Boot Mode Select Pins
        2. 5.4.3.2 One Boot Mode Select Pin
        3. 5.4.3.3 Three Boot Mode Select Pins
    5. 5.5 Device Boot Flow Diagrams
      1. 5.5.1 Boot Flow
      2. 5.5.2 Emulation Boot Flow
      3. 5.5.3 Standalone Boot Flow
    6. 5.6 Device Reset and Exception Handling
      1. 5.6.1 Reset Causes and Handling
      2. 5.6.2 Exceptions and Interrupts Handling
    7. 5.7 Boot ROM Description
      1. 5.7.1  Boot ROM Configuration Registers
        1. 5.7.1.1 GPREG2 Usage and MPOST Configuration
      2. 5.7.2  Entry Points
      3. 5.7.3  Wait Points
      4. 5.7.4  Secure Flash Boot
        1. 5.7.4.1 Secure Flash CPU1 Linker File Example
      5. 5.7.5  Memory Maps
        1. 5.7.5.1 Boot ROM Memory Maps
        2. 5.7.5.2 Reserved RAM Memory Maps
      6. 5.7.6  ROM Tables
      7. 5.7.7  Boot Modes and Loaders
        1. 5.7.7.1 Boot Modes
          1. 5.7.7.1.1 Flash Boot
          2. 5.7.7.1.2 RAM Boot
          3. 5.7.7.1.3 Wait Boot
        2. 5.7.7.2 Bootloaders
          1. 5.7.7.2.1 SCI Boot Mode
          2. 5.7.7.2.2 SPI Boot Mode
          3. 5.7.7.2.3 I2C Boot Mode
          4. 5.7.7.2.4 Parallel Boot Mode
          5. 5.7.7.2.5 CAN Boot Mode
          6. 5.7.7.2.6 CAN-FD Boot Mode
      8. 5.7.8  GPIO Assignments
      9. 5.7.9  Secure ROM Function APIs
      10. 5.7.10 Clock Initializations
      11. 5.7.11 Boot Status Information
        1. 5.7.11.1 Booting Status
        2. 5.7.11.2 Boot Mode and MPOST (Memory Power On Self-Test) Status
      12. 5.7.12 ROM Version
    8. 5.8 Application Notes for Using the Bootloaders
      1. 5.8.1 Bootloader Data Stream Structure
        1. 5.8.1.1 Data Stream Structure 8-bit
      2. 5.8.2 The C2000 Hex Utility
        1. 5.8.2.1 HEX2000.exe Command Syntax
  8. 6 Dual Code Security Module (DCSM)
    1. 6.1 Introduction
      1. 6.1.1 DCSM Related Collateral
    2. 6.2 Functional Description
      1. 6.2.1 CSM Passwords
      2. 6.2.2 Emulation Code Security Logic (ECSL)
      3. 6.2.3 CPU Secure Logic
      4. 6.2.4 Execute-Only Protection
      5. 6.2.5 Password Lock
      6. 6.2.6 JTAGLOCK
      7. 6.2.7 Link Pointer and Zone Select
      8. 6.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 6.3 Flash and OTP Erase/Program
    4. 6.4 Secure Copy Code
    5. 6.5 SecureCRC
    6. 6.6 CSM Impact on Other On-Chip Resources
      1. 6.6.1 RAMOPEN
    7. 6.7 Incorporating Code Security in User Applications
      1. 6.7.1 Environments That Require Security Unlocking
      2. 6.7.2 CSM Password Match Flow
      3. 6.7.3 C Code Example to Unsecure C28x Zone1
      4. 6.7.4 C Code Example to Resecure C28x Zone1
      5. 6.7.5 Environments That Require ECSL Unlocking
      6. 6.7.6 ECSL Password Match Flow
      7. 6.7.7 ECSL Disable Considerations for any Zone
        1. 6.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 6.7.8 Device Unique ID
    8. 6.8 Software
      1. 6.8.1 DCSM Examples
        1. 6.8.1.1 Empty DCSM Tool Example
    9. 6.9 DCSM Registers
      1. 6.9.1 DCSM Base Address Table
      2. 6.9.2 DCSM_Z1_REGS Registers
      3. 6.9.3 DCSM_Z2_REGS Registers
      4. 6.9.4 DCSM_COMMON_REGS Registers
      5. 6.9.5 DCSM_Z1_OTP Registers
      6. 6.9.6 DCSM_Z2_OTP Registers
      7. 6.9.7 DCSM Registers to Driverlib Functions
  9. 7 Flash Module
    1. 7.1  Introduction to Flash and OTP Memory
      1. 7.1.1 FLASH Related Collateral
      2. 7.1.2 Features
      3. 7.1.3 Flash Tools
      4. 7.1.4 Default Flash Configuration
    2. 7.2  Flash Bank, OTP, and Pump
    3. 7.3  Flash Wrapper
    4. 7.4  Flash and OTP Memory Performance
    5. 7.5  Flash Read Interface
      1. 7.5.1 C28x-Flash Read Interface
        1. 7.5.1.1 Standard Read Mode
        2. 7.5.1.2 Prefetch Mode
        3. 7.5.1.3 Data Cache
        4. 7.5.1.4 Flash Read Operation
    6. 7.6  Flash Erase and Program
      1. 7.6.1 Erase
      2. 7.6.2 Program
      3. 7.6.3 Verify
    7. 7.7  Error Correction Code (ECC) Protection
      1. 7.7.1 Single-Bit Data Error
      2. 7.7.2 Uncorrectable Error
      3. 7.7.3 Mechanism to Check the Correctness of ECC Logic
    8. 7.8  Reserved Locations Within Flash and OTP
    9. 7.9  Migrating an Application from RAM to Flash
    10. 7.10 Procedure to Change the Flash Control Registers
    11. 7.11 Software
      1. 7.11.1 FLASH Examples
        1. 7.11.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
        2. 7.11.1.2 Boot Source Code
        3. 7.11.1.3 Erase Source Code
        4. 7.11.1.4 Live DFU Command Functionality
        5. 7.11.1.5 Verify Source Code
        6. 7.11.1.6 SCI Boot Mode Routines
        7. 7.11.1.7 Flash Programming Solution using SCI
    12. 7.12 Flash Registers
      1. 7.12.1 FLASH Base Address Table
      2. 7.12.2 FLASH_CTRL_REGS Registers
      3. 7.12.3 FLASH_ECC_REGS Registers
      4. 7.12.4 FLASH Registers to Driverlib Functions
  10. 8 Dual-Clock Comparator (DCC)
    1. 8.1 Introduction
      1. 8.1.1 Features
      2. 8.1.2 Block Diagram
    2. 8.2 Module Operation
      1. 8.2.1 Configuring DCC Counters
      2. 8.2.2 Single-Shot Measurement Mode
      3. 8.2.3 Continuous Monitoring Mode
      4. 8.2.4 Error Conditions
    3. 8.3 Interrupts
    4. 8.4 Software
      1. 8.4.1 DCC Examples
        1. 8.4.1.1 DCC Single shot Clock verification
        2. 8.4.1.2 DCC Single shot Clock measurement
        3. 8.4.1.3 DCC Continuous clock monitoring
        4. 8.4.1.4 DCC Continuous clock monitoring
        5. 8.4.1.5 DCC Detection of clock failure
    5. 8.5 DCC Registers
      1. 8.5.1 DCC Base Address Table
      2. 8.5.2 DCC_REGS Registers
      3. 8.5.3 DCC Registers to Driverlib Functions
  11. 9 General-Purpose Input/Output (GPIO)
    1. 9.1  Introduction
      1. 9.1.1 GPIO Related Collateral
    2. 9.2  Configuration Overview
    3. 9.3  Digital Inputs on ADC Pins (AIOs)
    4. 9.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 9.5  Digital General-Purpose I/O Control
    6. 9.6  Input Qualification
      1. 9.6.1 No Synchronization (Asynchronous Input)
      2. 9.6.2 Synchronization to SYSCLKOUT Only
      3. 9.6.3 Qualification Using a Sampling Window
    7. 9.7  GPIO and Peripheral Muxing
      1. 9.7.1 GPIO Muxing
      2. 9.7.2 Peripheral Muxing
    8. 9.8  Internal Pullup Configuration Requirements
    9. 9.9  Software
      1. 9.9.1 GPIO Examples
        1. 9.9.1.1 Device GPIO Setup
        2. 9.9.1.2 Device GPIO Toggle
        3. 9.9.1.3 Device GPIO Interrupt
        4. 9.9.1.4 External Interrupt (XINT)
      2. 9.9.2 LED Examples
    10. 9.10 GPIO Registers
      1. 9.10.1 GPIO Base Address Table
      2. 9.10.2 GPIO_CTRL_REGS Registers
      3. 9.10.3 GPIO_DATA_REGS Registers
      4. 9.10.4 GPIO_DATA_READ_REGS Registers
      5. 9.10.5 GPIO Registers to Driverlib Functions
  12. 10Crossbar (X-BAR)
    1. 10.1 Input X-BAR
    2. 10.2 ePWM and GPIO Output X-BAR
      1. 10.2.1 ePWM X-BAR
        1. 10.2.1.1 ePWM X-BAR Architecture
      2. 10.2.2 GPIO Output X-BAR
        1. 10.2.2.1 GPIO Output X-BAR Architecture
      3. 10.2.3 X-BAR Flags
    3. 10.3 XBAR Registers
      1. 10.3.1 XBAR Base Address Table
      2. 10.3.2 INPUT_XBAR_REGS Registers
      3. 10.3.3 XBAR_REGS Registers
      4. 10.3.4 EPWM_XBAR_REGS Registers
      5. 10.3.5 OUTPUT_XBAR_REGS Registers
      6. 10.3.6 Register to Driverlib Function Mapping
        1. 10.3.6.1 INPUTXBAR Registers to Driverlib Functions
        2. 10.3.6.2 XBAR Registers to Driverlib Functions
        3. 10.3.6.3 EPWMXBAR Registers to Driverlib Functions
        4. 10.3.6.4 OUTPUTXBAR Registers to Driverlib Functions
  13. 11Analog Subsystem
    1. 11.1 Introduction
      1. 11.1.1 Features
      2. 11.1.2 Block Diagram
    2. 11.2 Optimizing Power-Up Time
    3. 11.3 Digital Inputs on ADC Pins (AIOs)
    4. 11.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 11.5 Analog Pins and Internal Connections
    6. 11.6 Analog Subsystem Registers
      1. 11.6.1 ASBSYS Base Address Table
      2. 11.6.2 ANALOG_SUBSYS_REGS Registers
  14. 12Analog-to-Digital Converter (ADC)
    1. 12.1  Introduction
      1. 12.1.1 ADC Related Collateral
      2. 12.1.2 Features
      3. 12.1.3 Block Diagram
    2. 12.2  ADC Configurability
      1. 12.2.1 Clock Configuration
      2. 12.2.2 Resolution
      3. 12.2.3 Voltage Reference
        1. 12.2.3.1 External Reference Mode
        2. 12.2.3.2 Internal Reference Mode
        3. 12.2.3.3 Selecting Reference Mode
      4. 12.2.4 Signal Mode
      5. 12.2.5 Expected Conversion Results
      6. 12.2.6 Interpreting Conversion Results
    3. 12.3  SOC Principle of Operation
      1. 12.3.1 SOC Configuration
      2. 12.3.2 Trigger Operation
      3. 12.3.3 ADC Acquisition (Sample and Hold) Window
      4. 12.3.4 ADC Input Models
      5. 12.3.5 Channel Selection
    4. 12.4  SOC Configuration Examples
      1. 12.4.1 Single Conversion from ePWM Trigger
      2. 12.4.2 Oversampled Conversion from ePWM Trigger
      3. 12.4.3 Multiple Conversions from CPU Timer Trigger
      4. 12.4.4 Software Triggering of SOCs
    5. 12.5  ADC Conversion Priority
    6. 12.6  Burst Mode
      1. 12.6.1 Burst Mode Example
      2. 12.6.2 Burst Mode Priority Example
    7. 12.7  EOC and Interrupt Operation
      1. 12.7.1 Interrupt Overflow
      2. 12.7.2 Continue to Interrupt Mode
      3. 12.7.3 Early Interrupt Configuration Mode
    8. 12.8  Post-Processing Blocks
      1. 12.8.1 PPB Offset Correction
      2. 12.8.2 PPB Error Calculation
      3. 12.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 12.8.4 PPB Sample Delay Capture
    9. 12.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 12.9.1 Implementation
      2. 12.9.2 Detecting an Open Input Pin
      3. 12.9.3 Detecting a Shorted Input Pin
    10. 12.10 Power-Up Sequence
    11. 12.11 ADC Calibration
      1. 12.11.1 ADC Zero Offset Calibration
    12. 12.12 ADC Timings
      1. 12.12.1 ADC Timing Diagrams
    13. 12.13 Additional Information
      1. 12.13.1 Ensuring Synchronous Operation
        1. 12.13.1.1 Basic Synchronous Operation
        2. 12.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 12.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 12.13.1.4 Non-overlapping Conversions
      2. 12.13.2 Choosing an Acquisition Window Duration
      3. 12.13.3 Achieving Simultaneous Sampling
      4. 12.13.4 Result Register Mapping
      5. 12.13.5 Internal Temperature Sensor
      6. 12.13.6 Designing an External Reference Circuit
      7. 12.13.7 ADC-DAC Loopback Testing
      8. 12.13.8 Internal Test Mode
      9. 12.13.9 ADC Gain and Offset Calibration
    14. 12.14 Software
      1. 12.14.1 ADC Examples
        1. 12.14.1.1  ADC Software Triggering
        2. 12.14.1.2  ADC ePWM Triggering
        3. 12.14.1.3  ADC Temperature Sensor Conversion
        4. 12.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 12.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 12.14.1.6  ADC PPB Offset (adc_ppb_offset)
        7. 12.14.1.7  ADC PPB Limits (adc_ppb_limits)
        8. 12.14.1.8  ADC PPB Delay Capture (adc_ppb_delay)
        9. 12.14.1.9  ADC ePWM Triggering Multiple SOC
        10. 12.14.1.10 ADC Burst Mode
        11. 12.14.1.11 ADC Burst Mode Oversampling
        12. 12.14.1.12 ADC SOC Oversampling
        13. 12.14.1.13 ADC PPB PWM trip (adc_ppb_pwm_trip)
        14. 12.14.1.14 ADC Open Shorts Detection (adc_open_shorts_detection)
    15. 12.15 ADC Registers
      1. 12.15.1 ADC Base Address Table
      2. 12.15.2 ADC_RESULT_REGS Registers
      3. 12.15.3 ADC_REGS Registers
      4. 12.15.4 ADC Registers to Driverlib Functions
  15. 13Comparator Subsystem (CMPSS)
    1. 13.1 Introduction
      1. 13.1.1 CMPSS Related Collateral
      2. 13.1.2 Features
      3. 13.1.3 CMPSS Module Variants
      4. 13.1.4 Block Diagram
    2. 13.2 Comparator
    3. 13.3 Reference DAC
    4. 13.4 Ramp Generator
      1. 13.4.1 Ramp Generator Overview
      2. 13.4.2 Ramp Generator Behavior
      3. 13.4.3 Ramp Generator Behavior at Corner Cases
    5. 13.5 Digital Filter
      1. 13.5.1 Filter Initialization Sequence
    6. 13.6 Using the CMPSS
      1. 13.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 13.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 13.6.3 Calibrating the CMPSS
      4. 13.6.4 Enabling and Disabling the CMPSS Clock
    7. 13.7 CMPSS DAC Output
    8. 13.8 Software
      1. 13.8.1 CMPSS Examples
        1. 13.8.1.1 CMPSS Asynchronous Trip
        2. 13.8.1.2 CMPSS Digital Filter Configuration
      2. 13.8.2 CMPSS_LITE Examples
        1. 13.8.2.1 CMPSSLITE Asynchronous Trip
    9. 13.9 CMPSS Registers
      1. 13.9.1 CMPSS Base Address Table
      2. 13.9.2 CMPSS_REGS Registers
      3. 13.9.3 CMPSS_LITE_REGS Registers
      4. 13.9.4 CMPSS Registers to Driverlib Functions
      5. 13.9.5 CMPSS_LITE Registers to Driverlib Functions
  16. 14Enhanced Pulse Width Modulator (ePWM)
    1. 14.1  Introduction
      1. 14.1.1 EPWM Related Collateral
      2. 14.1.2 Submodule Overview
    2. 14.2  Configuring Device Pins
    3. 14.3  ePWM Modules Overview
    4. 14.4  Time-Base (TB) Submodule
      1. 14.4.1 Purpose of the Time-Base Submodule
      2. 14.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 14.4.3 Calculating PWM Period and Frequency
        1. 14.4.3.1 Time-Base Period Shadow Register
        2. 14.4.3.2 Time-Base Clock Synchronization
        3. 14.4.3.3 Time-Base Counter Synchronization
        4. 14.4.3.4 ePWM SYNC Selection
      4. 14.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 14.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 14.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 14.4.7 Global Load
        1. 14.4.7.1 Global Load Pulse Pre-Scalar
        2. 14.4.7.2 One-Shot Load Mode
        3. 14.4.7.3 One-Shot Sync Mode
    5. 14.5  Counter-Compare (CC) Submodule
      1. 14.5.1 Purpose of the Counter-Compare Submodule
      2. 14.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 14.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 14.5.4 Count Mode Timing Waveforms
    6. 14.6  Action-Qualifier (AQ) Submodule
      1. 14.6.1 Purpose of the Action-Qualifier Submodule
      2. 14.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 14.6.3 Action-Qualifier Event Priority
      4. 14.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 14.6.5 Configuration Requirements for Common Waveforms
    7. 14.7  Dead-Band Generator (DB) Submodule
      1. 14.7.1 Purpose of the Dead-Band Submodule
      2. 14.7.2 Dead-band Submodule Additional Operating Modes
      3. 14.7.3 Operational Highlights for the Dead-Band Submodule
    8. 14.8  PWM Chopper (PC) Submodule
      1. 14.8.1 Purpose of the PWM Chopper Submodule
      2. 14.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 14.8.3 Waveforms
        1. 14.8.3.1 One-Shot Pulse
        2. 14.8.3.2 Duty Cycle Control
    9. 14.9  Trip-Zone (TZ) Submodule
      1. 14.9.1 Purpose of the Trip-Zone Submodule
      2. 14.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 14.9.2.1 Trip-Zone Configurations
      3. 14.9.3 Generating Trip Event Interrupts
    10. 14.10 Event-Trigger (ET) Submodule
      1. 14.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 14.11 Digital Compare (DC) Submodule
      1. 14.11.1 Purpose of the Digital Compare Submodule
      2. 14.11.2 Enhanced Trip Action Using CMPSS
      3. 14.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 14.11.4 Operation Highlights of the Digital Compare Submodule
        1. 14.11.4.1 Digital Compare Events
        2. 14.11.4.2 Event Filtering
        3. 14.11.4.3 Valley Switching
    12. 14.12 ePWM Crossbar (X-BAR)
    13. 14.13 Applications to Power Topologies
      1. 14.13.1  Overview of Multiple Modules
      2. 14.13.2  Key Configuration Capabilities
      3. 14.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 14.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 14.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 14.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 14.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 14.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 14.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 14.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 14.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 14.14 Register Lock Protection
    15. 14.15 High-Resolution Pulse Width Modulator (HRPWM)
      1. 14.15.1 Operational Description of HRPWM
        1. 14.15.1.1 Controlling the HRPWM Capabilities
        2. 14.15.1.2 HRPWM Source Clock
        3. 14.15.1.3 Configuring the HRPWM
        4. 14.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 14.15.1.5 Principle of Operation
          1. 14.15.1.5.1 Edge Positioning
          2. 14.15.1.5.2 Scaling Considerations
          3. 14.15.1.5.3 Duty Cycle Range Limitation
          4. 14.15.1.5.4 High-Resolution Period
            1. 14.15.1.5.4.1 High-Resolution Period Configuration
        6. 14.15.1.6 Deadband High-Resolution Operation
        7. 14.15.1.7 Scale Factor Optimizing Software (SFO)
        8. 14.15.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 14.15.1.8.1 #Defines for HRPWM Header Files
          2. 14.15.1.8.2 Implementing a Simple Buck Converter
            1. 14.15.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 14.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 14.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 14.15.1.8.3.1 PWM DAC Function Initialization Code
            2. 14.15.1.8.3.2 PWM DAC Function Run-Time Code
      2. 14.15.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 14.15.2.1 Scale Factor Optimizer Function - int SFO()
        2. 14.15.2.2 Software Usage
          1. 14.15.2.2.1 A Sample of How to Add "Include" Files
          2.        623
          3. 14.15.2.2.2 Declaring an Element
          4.        625
          5. 14.15.2.2.3 Initializing With a Scale Factor Value
          6.        627
          7. 14.15.2.2.4 SFO Function Calls
    16. 14.16 Software
      1. 14.16.1 EPWM Examples
        1. 14.16.1.1  ePWM Trip Zone
        2. 14.16.1.2  ePWM Up Down Count Action Qualifier
        3. 14.16.1.3  ePWM Synchronization
        4. 14.16.1.4  ePWM Digital Compare
        5. 14.16.1.5  ePWM Digital Compare Event Filter Blanking Window
        6. 14.16.1.6  ePWM Valley Switching
        7. 14.16.1.7  ePWM Digital Compare Edge Filter
        8. 14.16.1.8  ePWM Deadband
        9. 14.16.1.9  ePWM Chopper
        10. 14.16.1.10 EPWM Configure Signal
        11. 14.16.1.11 Realization of Monoshot mode
        12. 14.16.1.12 EPWM Action Qualifier (epwm_up_aq)
      2. 14.16.2 HRPWM Examples
        1. 14.16.2.1 HRPWM Duty Control with SFO
        2. 14.16.2.2 HRPWM Slider
        3. 14.16.2.3 HRPWM Period Control
        4. 14.16.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 14.16.2.5 HRPWM Slider Test
        6. 14.16.2.6 HRPWM Duty Up Count
        7. 14.16.2.7 HRPWM Period Up-Down Count
    17. 14.17 ePWM Registers
      1. 14.17.1 EPWM Base Address Table
      2. 14.17.2 EPWM_REGS Registers
      3. 14.17.3 Register to Driverlib Function Mapping
        1. 14.17.3.1 EPWM Registers to Driverlib Functions
        2. 14.17.3.2 HRPWM Registers to Driverlib Functions
  17. 15Enhanced Capture (eCAP)
    1. 15.1 Introduction
      1. 15.1.1 Features
      2. 15.1.2 ECAP Related Collateral
    2. 15.2 Description
    3. 15.3 Configuring Device Pins for the eCAP
    4. 15.4 Capture and APWM Operating Mode
    5. 15.5 Capture Mode Description
      1. 15.5.1 Event Prescaler
      2. 15.5.2 Edge Polarity Select and Qualifier
      3. 15.5.3 Continuous/One-Shot Control
      4. 15.5.4 32-Bit Counter and Phase Control
      5. 15.5.5 CAP1-CAP4 Registers
      6. 15.5.6 eCAP Synchronization
        1. 15.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 15.5.7 Interrupt Control
      8. 15.5.8 Shadow Load and Lockout Control
      9. 15.5.9 APWM Mode Operation
    6. 15.6 Application of the eCAP Module
      1. 15.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 15.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 15.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 15.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 15.7 Application of the APWM Mode
      1. 15.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 15.8 Software
      1. 15.8.1 ECAP Examples
        1. 15.8.1.1 eCAP APWM Example
        2. 15.8.1.2 eCAP Capture PWM Example
        3. 15.8.1.3 eCAP APWM Phase-shift Example
        4. 15.8.1.4 eCAP Software Sync Example
    9. 15.9 eCAP Registers
      1. 15.9.1 ECAP Base Address Table
      2. 15.9.2 ECAP_REGS Registers
      3. 15.9.3 ECAP Registers to Driverlib Functions
  18. 16Enhanced Quadrature Encoder Pulse (eQEP)
    1. 16.1  Introduction
      1. 16.1.1 EQEP Related Collateral
    2. 16.2  Configuring Device Pins
    3. 16.3  Description
      1. 16.3.1 EQEP Inputs
      2. 16.3.2 Functional Description
      3. 16.3.3 eQEP Memory Map
    4. 16.4  Quadrature Decoder Unit (QDU)
      1. 16.4.1 Position Counter Input Modes
        1. 16.4.1.1 Quadrature Count Mode
        2. 16.4.1.2 Direction-Count Mode
        3. 16.4.1.3 Up-Count Mode
        4. 16.4.1.4 Down-Count Mode
      2. 16.4.2 eQEP Input Polarity Selection
      3. 16.4.3 Position-Compare Sync Output
    5. 16.5  Position Counter and Control Unit (PCCU)
      1. 16.5.1 Position Counter Operating Modes
        1. 16.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 16.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 16.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 16.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 16.5.2 Position Counter Latch
        1. 16.5.2.1 Index Event Latch
        2. 16.5.2.2 Strobe Event Latch
      3. 16.5.3 Position Counter Initialization
      4. 16.5.4 eQEP Position-compare Unit
    6. 16.6  eQEP Edge Capture Unit
    7. 16.7  eQEP Watchdog
    8. 16.8  eQEP Unit Timer Base
    9. 16.9  QMA Module
      1. 16.9.1 Modes of Operation
        1. 16.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
        2. 16.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
      2. 16.9.2 Interrupt and Error Generation
    10. 16.10 eQEP Interrupt Structure
    11. 16.11 Software
      1. 16.11.1 EQEP Examples
        1. 16.11.1.1 Frequency Measurement Using eQEP
        2. 16.11.1.2 Position and Speed Measurement Using eQEP
        3. 16.11.1.3 ePWM frequency Measurement Using eQEP via xbar connection
        4. 16.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 16.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 16.12 eQEP Registers
      1. 16.12.1 EQEP Base Address Table
      2. 16.12.2 EQEP_REGS Registers
      3. 16.12.3 EQEP Registers to Driverlib Functions
  19. 17Controller Area Network (CAN)
    1. 17.1  Introduction
      1. 17.1.1 DCAN Related Collateral
      2. 17.1.2 Features
      3. 17.1.3 Block Diagram
        1. 17.1.3.1 CAN Core
        2. 17.1.3.2 Message Handler
        3. 17.1.3.3 Message RAM
        4. 17.1.3.4 Registers and Message Object Access (IFx)
    2. 17.2  Functional Description
      1. 17.2.1 Configuring Device Pins
      2. 17.2.2 Address/Data Bus Bridge
    3. 17.3  Operating Modes
      1. 17.3.1 Initialization
      2. 17.3.2 CAN Message Transfer (Normal Operation)
        1. 17.3.2.1 Disabled Automatic Retransmission
        2. 17.3.2.2 Auto-Bus-On
      3. 17.3.3 Test Modes
        1. 17.3.3.1 Silent Mode
        2. 17.3.3.2 Loopback Mode
        3. 17.3.3.3 External Loopback Mode
        4. 17.3.3.4 Loopback Combined with Silent Mode
    4. 17.4  Multiple Clock Source
    5. 17.5  Interrupt Functionality
      1. 17.5.1 Message Object Interrupts
      2. 17.5.2 Status Change Interrupts
      3. 17.5.3 Error Interrupts
      4. 17.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 17.5.5 Interrupt Topologies
    6. 17.6  Parity Check Mechanism
      1. 17.6.1 Behavior on Parity Error
    7. 17.7  Debug Mode
    8. 17.8  Module Initialization
    9. 17.9  Configuration of Message Objects
      1. 17.9.1 Configuration of a Transmit Object for Data Frames
      2. 17.9.2 Configuration of a Transmit Object for Remote Frames
      3. 17.9.3 Configuration of a Single Receive Object for Data Frames
      4. 17.9.4 Configuration of a Single Receive Object for Remote Frames
      5. 17.9.5 Configuration of a FIFO Buffer
    10. 17.10 Message Handling
      1. 17.10.1  Message Handler Overview
      2. 17.10.2  Receive/Transmit Priority
      3. 17.10.3  Transmission of Messages in Event Driven CAN Communication
      4. 17.10.4  Updating a Transmit Object
      5. 17.10.5  Changing a Transmit Object
      6. 17.10.6  Acceptance Filtering of Received Messages
      7. 17.10.7  Reception of Data Frames
      8. 17.10.8  Reception of Remote Frames
      9. 17.10.9  Reading Received Messages
      10. 17.10.10 Requesting New Data for a Receive Object
      11. 17.10.11 Storing Received Messages in FIFO Buffers
      12. 17.10.12 Reading from a FIFO Buffer
    11. 17.11 CAN Bit Timing
      1. 17.11.1 Bit Time and Bit Rate
        1. 17.11.1.1 Synchronization Segment
        2. 17.11.1.2 Propagation Time Segment
        3. 17.11.1.3 Phase Buffer Segments and Synchronization
        4. 17.11.1.4 Oscillator Tolerance Range
      2. 17.11.2 Configuration of the CAN Bit Timing
        1. 17.11.2.1 Calculation of the Bit Timing Parameters
        2. 17.11.2.2 Example for Bit Timing at High Baudrate
        3. 17.11.2.3 Example for Bit Timing at Low Baudrate
    12. 17.12 Message Interface Register Sets
      1. 17.12.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 17.12.2 Message Interface Register Set 3 (IF3)
    13. 17.13 Message RAM
      1. 17.13.1 Structure of Message Objects
      2. 17.13.2 Addressing Message Objects in RAM
      3. 17.13.3 Message RAM Representation in Debug Mode
    14. 17.14 Software
      1. 17.14.1 CAN Examples
        1. 17.14.1.1 CAN External Loopback
        2. 17.14.1.2 CAN External Loopback with Interrupts
        3. 17.14.1.3 CAN Transmit and Receive Configurations
        4. 17.14.1.4 CAN Error Generation Example
        5. 17.14.1.5 CAN Remote Request Loopback
        6. 17.14.1.6 CAN example that illustrates the usage of Mask registers
    15. 17.15 CAN Registers
      1. 17.15.1 CAN Base Address Table
      2. 17.15.2 CAN_REGS Registers
      3. 17.15.3 CAN Registers to Driverlib Functions
  20. 18Modular Controller Area Network (MCAN)
    1. 18.1 MCAN Introduction
      1. 18.1.1 MCAN Related Collateral
      2. 18.1.2 MCAN Features
    2. 18.2 MCAN Environment
    3. 18.3 CAN Network Basics
    4. 18.4 MCAN Integration
    5. 18.5 MCAN Functional Description
      1. 18.5.1  Module Clocking Requirements
      2. 18.5.2  Interrupt Requests
      3. 18.5.3  Operating Modes
        1. 18.5.3.1 Software Initialization
        2. 18.5.3.2 Normal Operation
        3. 18.5.3.3 CAN FD Operation
      4. 18.5.4  Transmitter Delay Compensation
        1. 18.5.4.1 Description
        2. 18.5.4.2 Transmitter Delay Compensation Measurement
      5. 18.5.5  Restricted Operation Mode
      6. 18.5.6  Bus Monitoring Mode
      7. 18.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 18.5.7.1 Frame Transmission in DAR Mode
      8. 18.5.8  Clock Stop Mode
        1. 18.5.8.1 Suspend Mode
        2. 18.5.8.2 Wakeup Request
      9. 18.5.9  Test Modes
        1. 18.5.9.1 External Loop Back Mode
        2. 18.5.9.2 Internal Loop Back Mode
      10. 18.5.10 Timestamp Generation
        1. 18.5.10.1 External Timestamp Counter
      11. 18.5.11 Timeout Counter
      12. 18.5.12 Safety
        1. 18.5.12.1 ECC Wrapper
        2. 18.5.12.2 ECC Aggregator
          1. 18.5.12.2.1 ECC Aggregator Overview
          2. 18.5.12.2.2 ECC Aggregator Registers
        3. 18.5.12.3 Reads to ECC Control and Status Registers
        4. 18.5.12.4 ECC Interrupts
      13. 18.5.13 Rx Handling
        1. 18.5.13.1 Acceptance Filtering
          1. 18.5.13.1.1 Range Filter
          2. 18.5.13.1.2 Filter for Specific IDs
          3. 18.5.13.1.3 Classic Bit Mask Filter
          4. 18.5.13.1.4 Standard Message ID Filtering
          5. 18.5.13.1.5 Extended Message ID Filtering
        2. 18.5.13.2 Rx FIFOs
          1. 18.5.13.2.1 Rx FIFO Blocking Mode
          2. 18.5.13.2.2 Rx FIFO Overwrite Mode
        3. 18.5.13.3 Dedicated Rx Buffers
          1. 18.5.13.3.1 Rx Buffer Handling
      14. 18.5.14 Tx Handling
        1. 18.5.14.1 Transmit Pause
        2. 18.5.14.2 Dedicated Tx Buffers
        3. 18.5.14.3 Tx FIFO
        4. 18.5.14.4 Tx Queue
        5. 18.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 18.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 18.5.14.7 Transmit Cancellation
        8. 18.5.14.8 Tx Event Handling
      15. 18.5.15 FIFO Acknowledge Handling
      16. 18.5.16 Message RAM
        1. 18.5.16.1 Message RAM Configuration
        2. 18.5.16.2 Rx Buffer and FIFO Element
        3. 18.5.16.3 Tx Buffer Element
        4. 18.5.16.4 Tx Event FIFO Element
        5. 18.5.16.5 Standard Message ID Filter Element
        6. 18.5.16.6 Extended Message ID Filter Element
    6. 18.6 Software
      1. 18.6.1 MCAN Examples
        1. 18.6.1.1  MCAN Internal Loopback with Interrupt
        2. 18.6.1.2  MCAN Loopback with Interrupts Example Using SYSCONFIG Tool
        3. 18.6.1.3  MCAN receive using Rx Buffer
        4. 18.6.1.4  MCAN External Reception (with mask filter) into RX-FIFO1
        5. 18.6.1.5  MCAN Classic frames transmission using Tx Buffer
        6. 18.6.1.6  MCAN External Reception (with RANGE filter) into RX-FIFO1
        7. 18.6.1.7  MCAN External Transmit using Tx Buffer
        8. 18.6.1.8  MCAN receive using Rx Buffer
        9. 18.6.1.9  MCAN Internal Loopback with Interrupt
        10. 18.6.1.10 MCAN External Transmit using Tx Buffer
    7. 18.7 MCAN Registers
      1. 18.7.1 MCAN Base Address Table
      2. 18.7.2 MCANSS_REGS Registers
      3. 18.7.3 MCAN_REGS Registers
      4. 18.7.4 MCAN_ERROR_REGS Registers
      5. 18.7.5 MCAN Registers to Driverlib Functions
  21. 19Inter-Integrated Circuit Module (I2C)
    1. 19.1 Introduction
      1. 19.1.1 I2C Related Collateral
      2. 19.1.2 Features
      3. 19.1.3 Features Not Supported
      4. 19.1.4 Functional Overview
      5. 19.1.5 Clock Generation
      6. 19.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 19.1.6.1 Formula for the Master Clock Period
    2. 19.2 Configuring Device Pins
    3. 19.3 I2C Module Operational Details
      1. 19.3.1  Input and Output Voltage Levels
      2. 19.3.2  Selecting Pullup Resistors
      3. 19.3.3  Data Validity
      4. 19.3.4  Operating Modes
      5. 19.3.5  I2C Module START and STOP Conditions
      6. 19.3.6  Non-repeat Mode versus Repeat Mode
      7. 19.3.7  Serial Data Formats
        1. 19.3.7.1 7-Bit Addressing Format
        2. 19.3.7.2 10-Bit Addressing Format
        3. 19.3.7.3 Free Data Format
        4. 19.3.7.4 Using a Repeated START Condition
      8. 19.3.8  Clock Synchronization
      9. 19.3.9  Arbitration
      10. 19.3.10 Digital Loopback Mode
      11. 19.3.11 NACK Bit Generation
    4. 19.4 Interrupt Requests Generated by the I2C Module
      1. 19.4.1 Basic I2C Interrupt Requests
      2. 19.4.2 I2C FIFO Interrupts
    5. 19.5 Resetting or Disabling the I2C Module
    6. 19.6 Software
      1. 19.6.1 I2C Examples
        1. 19.6.1.1 C28x-I2C Library source file for FIFO interrupts
        2. 19.6.1.2 C28x-I2C Library source file for FIFO using polling
        3. 19.6.1.3 C28x-I2C Library source file for FIFO interrupts
        4. 19.6.1.4 I2C Digital Loopback with FIFO Interrupts
        5. 19.6.1.5 I2C EEPROM
        6. 19.6.1.6 I2C Digital External Loopback with FIFO Interrupts
        7. 19.6.1.7 I2C EEPROM
        8. 19.6.1.8 I2C controller target communication using FIFO interrupts
        9. 19.6.1.9 I2C EEPROM
    7. 19.7 I2C Registers
      1. 19.7.1 I2C Base Address Table
      2. 19.7.2 I2C_REGS Registers
      3. 19.7.3 I2C Registers to Driverlib Functions
  22. 20Power Management Bus Module (PMBus)
    1. 20.1 Introduction
      1. 20.1.1 PMBUS Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Block Diagram
    2. 20.2 Configuring Device Pins
    3. 20.3 Slave Mode Operation
      1. 20.3.1 Configuration
      2. 20.3.2 Message Handling
        1. 20.3.2.1  Quick Command
        2. 20.3.2.2  Send Byte
        3. 20.3.2.3  Receive Byte
        4. 20.3.2.4  Write Byte and Write Word
        5. 20.3.2.5  Read Byte and Read Word
        6. 20.3.2.6  Process Call
        7. 20.3.2.7  Block Write
        8. 20.3.2.8  Block Read
        9. 20.3.2.9  Block Write-Block Read Process Call
        10. 20.3.2.10 Alert Response
        11. 20.3.2.11 Extended Command
        12. 20.3.2.12 Group Command
    4. 20.4 Master Mode Operation
      1. 20.4.1 Configuration
      2. 20.4.2 Message Handling
        1. 20.4.2.1  Quick Command
        2. 20.4.2.2  Send Byte
        3. 20.4.2.3  Receive Byte
        4. 20.4.2.4  Write Byte and Write Word
        5. 20.4.2.5  Read Byte and Read Word
        6. 20.4.2.6  Process Call
        7. 20.4.2.7  Block Write
        8. 20.4.2.8  Block Read
        9. 20.4.2.9  Block Write-Block Read Process Call
        10. 20.4.2.10 Alert Response
        11. 20.4.2.11 Extended Command
        12. 20.4.2.12 Group Command
    5. 20.5 PMBus Registers
      1. 20.5.1 PMBUS Base Address Table
      2. 20.5.2 PMBUS_REGS Registers
      3. 20.5.3 PMBUS Registers to Driverlib Functions
  23. 21Serial Communications Interface (SCI)
    1. 21.1  Introduction
      1. 21.1.1 Features
      2. 21.1.2 SCI Related Collateral
      3. 21.1.3 Block Diagram
    2. 21.2  Architecture
    3. 21.3  SCI Module Signal Summary
    4. 21.4  Configuring Device Pins
    5. 21.5  Multiprocessor and Asynchronous Communication Modes
    6. 21.6  SCI Programmable Data Format
    7. 21.7  SCI Multiprocessor Communication
      1. 21.7.1 Recognizing the Address Byte
      2. 21.7.2 Controlling the SCI TX and RX Features
      3. 21.7.3 Receipt Sequence
    8. 21.8  Idle-Line Multiprocessor Mode
      1. 21.8.1 Idle-Line Mode Steps
      2. 21.8.2 Block Start Signal
      3. 21.8.3 Wake-Up Temporary (WUT) Flag
        1. 21.8.3.1 Sending a Block Start Signal
      4. 21.8.4 Receiver Operation
    9. 21.9  Address-Bit Multiprocessor Mode
      1. 21.9.1 Sending an Address
    10. 21.10 SCI Communication Format
      1. 21.10.1 Receiver Signals in Communication Modes
      2. 21.10.2 Transmitter Signals in Communication Modes
    11. 21.11 SCI Port Interrupts
      1. 21.11.1 Break Detect
    12. 21.12 SCI Baud Rate Calculations
    13. 21.13 SCI Enhanced Features
      1. 21.13.1 SCI FIFO Description
      2. 21.13.2 SCI Auto-Baud
      3. 21.13.3 Autobaud-Detect Sequence
    14. 21.14 Software
      1. 21.14.1 SCI Examples
        1. 21.14.1.1 Tune Baud Rate via UART Example
        2. 21.14.1.2 SCI FIFO Digital Loop Back
        3. 21.14.1.3 SCI Digital Loop Back with Interrupts
        4. 21.14.1.4 SCI Echoback
        5. 21.14.1.5 stdout redirect example
    15. 21.15 SCI Registers
      1. 21.15.1 SCI Base Address Table
      2. 21.15.2 SCI_REGS Registers
      3. 21.15.3 SCI Registers to Driverlib Functions
  24. 22Serial Peripheral Interface (SPI)
    1. 22.1 Introduction
      1. 22.1.1 Features
      2. 22.1.2 SPI Related Collateral
      3. 22.1.3 Block Diagram
    2. 22.2 System-Level Integration
      1. 22.2.1 SPI Module Signals
      2. 22.2.2 Configuring Device Pins
        1. 22.2.2.1 GPIOs Required for High-Speed Mode
      3. 22.2.3 SPI Interrupts
    3. 22.3 SPI Operation
      1. 22.3.1 Introduction to Operation
      2. 22.3.2 Master Mode
      3. 22.3.3 Slave Mode
      4. 22.3.4 Data Format
        1. 22.3.4.1 Transmission of Bit from SPIRXBUF
      5. 22.3.5 Baud Rate Selection
        1. 22.3.5.1 Baud Rate Determination
        2. 22.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 22.3.6 SPI Clocking Schemes
      7. 22.3.7 SPI FIFO Description
      8. 22.3.8 SPI High-Speed Mode
      9. 22.3.9 SPI 3-Wire Mode Description
    4. 22.4 Programming Procedure
      1. 22.4.1 Initialization Upon Reset
      2. 22.4.2 Configuring the SPI
      3. 22.4.3 Configuring the SPI for High-Speed Mode
      4. 22.4.4 Data Transfer Example
      5. 22.4.5 SPI 3-Wire Mode Code Examples
        1. 22.4.5.1 3-Wire Master Mode Transmit
        2.       1062
          1. 22.4.5.2.1 3-Wire Master Mode Receive
        3.       1064
          1. 22.4.5.2.1 3-Wire Slave Mode Transmit
        4.       1066
          1. 22.4.5.2.1 3-Wire Slave Mode Receive
      6. 22.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 22.5 Software
      1. 22.5.1 SPI Examples
        1. 22.5.1.1 SPI Digital Loopback
        2. 22.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 22.5.1.3 SPI EEPROM
    6. 22.6 SPI Registers
      1. 22.6.1 SPI Base Address Table
      2. 22.6.2 SPI_REGS Registers
      3. 22.6.3 SPI Registers to Driverlib Functions
  25. 23Local Interconnect Network (LIN)
    1. 23.1 Introduction
      1. 23.1.1 SCI Features
      2. 23.1.2 LIN Features
      3. 23.1.3 LIN Related Collateral
      4. 23.1.4 Block Diagram
    2. 23.2 Serial Communications Interface Module
      1. 23.2.1 SCI Communication Formats
        1. 23.2.1.1 SCI Frame Formats
        2. 23.2.1.2 SCI Asynchronous Timing Mode
        3. 23.2.1.3 SCI Baud Rate
          1. 23.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 23.2.1.4 SCI Multiprocessor Communication Modes
          1. 23.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 23.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 23.2.1.5 SCI Multibuffered Mode
      2. 23.2.2 SCI Interrupts
        1. 23.2.2.1 Transmit Interrupt
        2. 23.2.2.2 Receive Interrupt
        3. 23.2.2.3 WakeUp Interrupt
        4. 23.2.2.4 Error Interrupts
      3. 23.2.3 SCI Configurations
        1. 23.2.3.1 Receiving Data
          1. 23.2.3.1.1 Receiving Data in Single-Buffer Mode
          2. 23.2.3.1.2 Receiving Data in Multibuffer Mode
        2. 23.2.3.2 Transmitting Data
          1. 23.2.3.2.1 Transmitting Data in Single-Buffer Mode
          2. 23.2.3.2.2 Transmitting Data in Multibuffer Mode
      4. 23.2.4 SCI Low-Power Mode
        1. 23.2.4.1 Sleep Mode for Multiprocessor Communication
    3. 23.3 Local Interconnect Network Module
      1. 23.3.1 LIN Communication Formats
        1. 23.3.1.1  LIN Standards
        2. 23.3.1.2  Message Frame
          1. 23.3.1.2.1 Message Header
          2. 23.3.1.2.2 Response
        3. 23.3.1.3  Synchronizer
        4. 23.3.1.4  Baud Rate
          1. 23.3.1.4.1 Fractional Divider
          2. 23.3.1.4.2 Superfractional Divider
            1. 23.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 23.3.1.5  Header Generation
          1. 23.3.1.5.1 Event Triggered Frame Handling
          2. 23.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 23.3.1.6  Extended Frames Handling
        7. 23.3.1.7  Timeout Control
          1. 23.3.1.7.1 No-Response Error (NRE)
          2. 23.3.1.7.2 Bus Idle Detection
          3. 23.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 23.3.1.8  TXRX Error Detector (TED)
          1. 23.3.1.8.1 Bit Errors
          2. 23.3.1.8.2 Physical Bus Errors
          3. 23.3.1.8.3 ID Parity Errors
          4. 23.3.1.8.4 Checksum Errors
        9. 23.3.1.9  Message Filtering and Validation
        10. 23.3.1.10 Receive Buffers
        11. 23.3.1.11 Transmit Buffers
      2. 23.3.2 LIN Interrupts
      3. 23.3.3 Servicing LIN Interrupts
      4. 23.3.4 LIN Configurations
        1. 23.3.4.1 Receiving Data
          1. 23.3.4.1.1 Receiving Data in Single-Buffer Mode
          2. 23.3.4.1.2 Receiving Data in Multibuffer Mode
        2. 23.3.4.2 Transmitting Data
          1. 23.3.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 23.3.4.2.2 Transmitting Data in Multibuffer Mode
    4. 23.4 Low-Power Mode
      1. 23.4.1 Entering Sleep Mode
      2. 23.4.2 Wakeup
      3. 23.4.3 Wakeup Timeouts
    5. 23.5 Emulation Mode
    6. 23.6 Software
      1. 23.6.1 LIN Examples
        1. 23.6.1.1 LIN Internal Loopback with Interrupts
        2. 23.6.1.2 LIN SCI Mode Internal Loopback with Interrupts
        3. 23.6.1.3 LIN Internal Loopback without interrupts(polled mode)
    7. 23.7 SCI/LIN Registers
      1. 23.7.1 LIN Base Address Table
      2. 23.7.2 LIN_REGS Registers
      3. 23.7.3 LIN Registers to Driverlib Functions
  26. 24Embedded Pattern Generator (EPG)
    1. 24.1 Introduction
      1. 24.1.1 Features
      2. 24.1.2 EPG Block Diagram
      3. 24.1.3 EPG Related Collateral
    2. 24.2 Clock Generator Modules
      1. 24.2.1 DCLK (50% duty cycle clock)
      2. 24.2.2 Clock Stop
    3. 24.3 Signal Generator Module
    4. 24.4 EPG Peripheral Signal Mux Selection
    5. 24.5 EPG Example Use Cases
      1. 24.5.1 EPG Example: Synchronous Clocks with Offset
        1. 24.5.1.1 Synchronous Clocks with Offset Register Configuration
      2. 24.5.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 24.5.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 24.5.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 24.5.3.1 Serial Data Bit Stream (MSB first) Register Configuration
    6. 24.6 EPG Interrupt
    7. 24.7 Software
      1. 24.7.1 EPG Examples
        1. 24.7.1.1 EPG Generating Synchronous Clocks
        2. 24.7.1.2 EPG Generating Two Offset Clocks
        3. 24.7.1.3 EPG Generating Two Offset Clocks With SIGGEN
        4. 24.7.1.4 EPG Generate Serial Data
        5. 24.7.1.5 EPG Generate Serial Data Shift Mode
    8. 24.8 EPG Registers
      1. 24.8.1 EPG Base Address Table
      2. 24.8.2 EPG_REGS Registers
      3. 24.8.3 EPG_MUX_REGS Registers
      4. 24.8.4 EPG Registers to Driverlib Functions
  27. 25Revision History

20.5.2 PMBUS_REGS Registers

Table 20-2 lists the memory-mapped registers for the PMBUS_REGS registers. All register offset addresses not listed in Table 20-2 should be considered as reserved locations and the register contents should not be modified.

Table 20-2 PMBUS_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hPMBMCPMBUS Master Mode Control RegisterEALLOWGo
2hPMBTXBUFPMBUS Transmit BufferGo
4hPMBRXBUFPMBUS Receive bufferGo
6hPMBACKPMBUS Acknowledge RegisterGo
8hPMBSTSPMBUS Status RegisterGo
AhPMBINTMPMBUS Interrupt Mask RegisterEALLOWGo
ChPMBSCPMBUS Slave Mode Configuration RegisterEALLOWGo
EhPMBHSAPMBUS Hold Slave Address RegisterGo
10hPMBCTRLPMBUS Control RegisterEALLOWGo
12hPMBTIMCTLPMBUS Timing Control RegisterEALLOWGo
14hPMBTIMCLKPMBUS Clock Timing RegisterEALLOWGo
16hPMBTIMSTSETUPPMBUS Start Setup Time RegisterEALLOWGo
18hPMBTIMBIDLEPMBUS Bus Idle Time RegisterEALLOWGo
1AhPMBTIMLOWTIMOUTPMBUS Clock Low Timeout Value RegisterEALLOWGo
1ChPMBTIMHIGHTIMOUTPMBUS Clock High Timeout Value RegisterEALLOWGo

Complex bit access types are encoded to fit into small table cells. Table 20-3 shows the codes that are used for access types in this section.

Table 20-3 PMBUS_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCR
C		Read
to Clear
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

20.5.2.1 PMBMC Register (Offset = 0h) [Reset = 00000000h]

PMBMC is shown in Figure 20-28 and described in Table 20-4.

Return to the Summary Table.

PMBUS Master Mode Control Register

Figure 20-28 PMBMC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDPRC_CALLGRP_CMDPEC_ENAEXT_CMDCMD_ENA
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BYTE_COUNT
R/W-0h
76543210
SLAVE_ADDRRW
R/W-0hR/W-0h
Table 20-4 PMBMC Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved
20PRC_CALLR/W0h0 = Default state for all messages besides Process Call message
1 = Enables transmission of Process Call message

Reset type: SYSRSn

19GRP_CMDR/W0h0 = Default state for all messages besides Group Command message
1 = Enables transmission of Group Command message

Reset type: SYSRSn

18PEC_ENAR/W0h0 = Disables PEC processing
1 = Enables PEC byte transmission/reception

Reset type: SYSRSn

17EXT_CMDR/W0h0 = Use 1 byte for Command Code
1 = Use 2 bytes for Command Code

Reset type: SYSRSn

16CMD_ENAR/W0h0 = Disables use of command code on Master initiated messages (
1 = Enables use of command code on Master initiated messages

Reset type: SYSRSn

15-8BYTE_COUNTR/W0hIndicates number of data bytes transmitted in current message. Byte count does not include any device addresses, command words or block lengths in block messages. In block messages, the PMBus Interface automatically inserts the block length into the message based on the byte count setting. The firmware only needs to load the address, command words and data to be transmitted. PMBus Interface supports byte writes up to 255
bytes.

Reset type: SYSRSn

7-1SLAVE_ADDRR/W0hSpecifies the address of the slave to which the current message is
directed towards.

Reset type: SYSRSn

0RWR/W0h0 = Message is a write transaction (data from Master to Slave)
1 = Message is a read transaction (data from Slave to Master)

Reset type: SYSRSn

20.5.2.2 PMBTXBUF Register (Offset = 2h) [Reset = 00000000h]

PMBTXBUF is shown in Figure 20-29 and described in Table 20-5.

Return to the Summary Table.

PMBUS Transmit Buffer

Figure 20-29 PMBTXBUF Register
313029282726252423222120191817161514131211109876543210
TXDATA
R/W-0h
Table 20-5 PMBTXBUF Register Field Descriptions
BitFieldTypeResetDescription
31-0TXDATAR/W0hBits 31-24: BYTE3 - Last data byte transmitted from Transmit Data Buffer
Bits 23-16: BYTE2 - Third data byte transmitted from Transmit Data Buffer
Bits 15-8: BYTE1 - Second data byte transmitted from Transmit Data Buffer
Bits 7-0: BYTE0 - First data byte transmitted from Transmit Data Buffer

Reset type: SYSRSn

20.5.2.3 PMBRXBUF Register (Offset = 4h) [Reset = 00000000h]

PMBRXBUF is shown in Figure 20-30 and described in Table 20-6.

Return to the Summary Table.

PMBUS Receive buffer

Figure 20-30 PMBRXBUF Register
313029282726252423222120191817161514131211109876543210
RXDATA
R-0h
Table 20-6 PMBRXBUF Register Field Descriptions
BitFieldTypeResetDescription
31-0RXDATAR0hBits 31-24: BYTE3 - Last data byte received in Receive Data Buffer
Bits 23-16: BYTE2 - Third data byte received in Receive Data Buffer
Bits 15-8: BYTE1 - Second data byte received in Receive Data Buffer
Bits 7-0: BYTE0 - First data byte received in Receive Data Buffer

Reset type: SYSRSn

20.5.2.4 PMBACK Register (Offset = 6h) [Reset = 00000000h]

PMBACK is shown in Figure 20-31 and described in Table 20-7.

Return to the Summary Table.

PMBUS Acknowledge Register

Figure 20-31 PMBACK Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDACK
R-0hR/W-0h
Table 20-7 PMBACK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ACKR/W0h0 = NACK received data
1 = Acknowledge received data, bit clears upon issue of ACK on PMBus

Reset type: SYSRSn

20.5.2.5 PMBSTS Register (Offset = 8h) [Reset = 00340000h]

PMBSTS is shown in Figure 20-32 and described in Table 20-8.

Return to the Summary Table.

PMBUS Status Register

Figure 20-32 PMBSTS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDSCL_RAWSDA_RAWCONTROL_RAWALERT_RAWCONTROL_EDGEALERT_EDGE
R-0hR-1hR-1hR-0hR-1hRC-0hRC-0h
15141312111098
MASTERLOST_ARBBUS_FREEUNIT_BUSYRPT_STARTSLAVE_ADDR_READYCLK_HIGH_DETECTEDCLK_LOW_TIMEOUT
RC-0hRC-0hRC-0hRC-0hRC-0hRC-0hRC-0hRC-0h
76543210
PEC_VALIDNACKEOMDATA_REQUESTDATA_READYRD_BYTE_COUNT
RC-0hRC-0hRC-0hRC-0hRC-0hRC-0h
Table 20-8 PMBSTS Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved
21SCL_RAWR1h0 = PMBus clock pin observed at logic level low
1 = PMBus clock pin observed at logic level high

Reset type: SYSRSn

20SDA_RAWR1h0 = PMBus data pin observed at logic level low
1 = PMBus data pin observed at logic level high

Reset type: SYSRSn

19CONTROL_RAWR0h0 = Control pin observed at logic level low
1 = Control pin observed at logic level high

Reset type: SYSRSn

18ALERT_RAWR1h0 = Alert pin observed at logic level low
1 = Alert pin observed at logic level high

Reset type: SYSRSn

17CONTROL_EDGERC0h0 = Control pin has not transitioned
1 = Control pin has been asserted by another device on PMBus

Reset type: SYSRSn

16ALERT_EDGERC0h0 = Alert pin has not transitioned
1 = Alert pin has been asserted by another device on PMBus

Reset type: SYSRSn

15MASTERRC0h0 = PMBus Interface in Slave Mode or Idle Mode
1 = PMBus Interface in Master Mode

Reset type: SYSRSn

14LOST_ARBRC0h0 = Master has attained control of PMBus
1 = Master has lost arbitration and control of PMBus

Reset type: SYSRSn

13BUS_FREERC0h0 = PMBus processing current message
1 = PMBus available for new message

Reset type: SYSRSn

12UNIT_BUSYRC0h0 = PMBus Interface is idle, ready to transmit/receive message
1 = PMBus Interface is busy, processing current message

Reset type: SYSRSn

11RPT_STARTRC0h0 = No Repeated Start received by interface
1 = Repeated Start condition received by interface

Reset type: SYSRSn

10SLAVE_ADDR_READYRC0h0 = Indicates no slave address is available for reading
1 = Slave address ready to be read from Receive Data Register (Bits 6:0)

Reset type: SYSRSn

9CLK_HIGH_DETECTEDRC0h0 = No Clock High condition detected
1 = Clock High exceeded 50us during message

Reset type: SYSRSn

8CLK_LOW_TIMEOUTRC0h0 = No clock low timeout detected
1 = Clock low timeout detected, clock held low for greater than 35ms

Reset type: SYSRSn

7PEC_VALIDRC0h0 = Received PEC not valid (if EOM is asserted)
1 = Received PEC is valid
Note: PEC_VALID status is don't care during the message. This will have a valid value only after EOM.

Reset type: SYSRSn

6NACKRC0h0 = Data transmitted has been accepted by receiver
1 = Receiver has not accepted transmitted data

Reset type: SYSRSn

5EOMRC0h0 = Message still in progress or PMBus in idle state.
1 = End of current message detected

Reset type: SYSRSn

4DATA_REQUESTRC0h0 = No data needed by PMBus Interface
1 = PMBus Interface request additional data. PMBus clock stretching enabled to stall bus

Reset type: SYSRSn

3DATA_READYRC0h0 = No data available for reading by processor
1 = PMBus Interface read buffer full, firmware required to read data prior to further bus
activity. PMBus clock stretching enabled to stall bus until data is read by firmware.

Reset type: SYSRSn

2-0RD_BYTE_COUNTRC0h0 = No received data
1 = 1 byte received. Data located in Receive Data Register, Bits 7-0
2 = 2 bytes received. Data located in Receive Data Register, Bits 15-0
3 = 3 bytes received. Data located in Receive Data Register, Bits 23-0
4 = 4 bytes received. Data located in Receive Data Register, Bits 31-0

Reset type: SYSRSn

20.5.2.6 PMBINTM Register (Offset = Ah) [Reset = 000003FFh]

PMBINTM is shown in Figure 20-33 and described in Table 20-9.

Return to the Summary Table.

PMBUS Interrupt Mask Register

Figure 20-33 PMBINTM Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCLK_HIGH_DETECTLOST_ARB
R-0hR/W-1hR/W-1h
76543210
CONTROLALERTEOMSLAVE_ADDR_READYDATA_REQUESTDATA_READYBUS_LOW_TIMEOUTBUS_FREE
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 20-9 PMBINTM Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9CLK_HIGH_DETECTR/W1h0 = Generates interrupt if clock high exceeds 50us during message
1 = Disables interrupt generation for Clock High detection

Reset type: SYSRSn

8LOST_ARBR/W1h0 = Generates interrupt upon assertion of Lost Arbitration flag
1 = Disables interrupt generation upon assertion of Lost Arbitration flag

Reset type: SYSRSn

7CONTROLR/W1h0 = Generates interrupt upon assertion of Control flag
1 = Disables interrupt generation upon assertion of Control flag

Reset type: SYSRSn

6ALERTR/W1h0 = Generates interrupt upon assertion of Alert flag
1 = Disables interrupt generation upon assertion of Alert flag

Reset type: SYSRSn

5EOMR/W1h0 = Generates interrupt upon assertion of End of Message flag
1 = Disables interrupt generation upon assertion of End of Message flag

Reset type: SYSRSn

4SLAVE_ADDR_READYR/W1h0 = Generates interrupt upon assertion of Slave Address Ready flag
1 = Disables interrupt generation upon assertion of Slave Address Ready flag

Reset type: SYSRSn

3DATA_REQUESTR/W1h0 = Generates interrupt upon assertion of Data Request flag
1 = Disables interrupt generation upon assertion of Data Request flag

Reset type: SYSRSn

2DATA_READYR/W1h0 = Generates interrupt upon assertion of Data Ready flag
1 = Disables interrupt generation upon assertion of Data Ready flag

Reset type: SYSRSn

1BUS_LOW_TIMEOUTR/W1h0 = Generates interrupt upon assertion of Clock Low Timeout flag
1 = Disables interrupt generation upon assertion of Clock Low Timeout flag

Reset type: SYSRSn

0BUS_FREER/W1h0 = Generates interrupt upon assertion of Bus Free flag
1 = Disables interrupt generation upon assertion of Bus Free flag

Reset type: SYSRSn

20.5.2.7 PMBSC Register (Offset = Ch) [Reset = 00607F7Ch]

PMBSC is shown in Figure 20-34 and described in Table 20-10.

Return to the Summary Table.

PMBUS Slave Mode Configuration Register

Figure 20-34 PMBSC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRX_BYTE_ACK_CNTMAN_CMDTX_PECTX_COUNT
R-0hR/W-3hR/W-0hR/W-0hR/W-0h
15141312111098
PEC_ENASLAVE_MASK
R/W-0hR/W-7Fh
76543210
MAN_SLAVE_ACKSLAVE_ADDR
R/W-0hR/W-7Ch
Table 20-10 PMBSC Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved
22-21RX_BYTE_ACK_CNTR/W3hConfigures number of data bytes to automatically
acknowledge when receiving data in slave mode.
00 = 1 byte received by slave. Firmware is required to manually acknowledge every received byte.
01 = 2 bytes received by slave. Hardware automatically acknowledges the first received
byte. Firmware is required to manually acknowledge after the second received byte.
10 = 3 bytes received by slave. Hardware automatically acknowledges the first 2 received
bytes. Firmware is required to manually acknowledge after the third received byte.
11 = 4 bytes received by slave. Hardware automatically acknowledges the first 3 received
bytes. Firmware is required to manually acknowledge after the fourth received byte

Reset type: SYSRSn

20MAN_CMDR/W0h0 = Slave automatically acknowledges received command code
1 = Data Request flag generated after receipt of command code, firmware required to
issue ACK to continue message

Reset type: SYSRSn

19TX_PECR/W0hAsserted when the slave needs to send a PEC byte at end of message.
PMBus Interface will transmit the calculated PEC byte after transmitting the number of data bytes
indicated by TX Byte Cnt(Bits 18:16).

Reset type: SYSRSn

18-16TX_COUNTR/W0h0 = No bytes valid
1 = One byte valid, Byte #0 (Bits 7:0 of Transmit Data Register)
2 = Two bytes valid, Bytes #0 and #1 (Bits 15:0 of Transmit Data Register)
3 = Three bytes valid, Bytes #0-2 (Bits 23:0 of Transmit Data Register)
4 = Four bytes valid, Bytes #0-3 (Bits 31:0 of Transmit Data Register)

Reset type: SYSRSn

15PEC_ENAR/W0h0 = PEC processing disabled
1 = PEC processing enabled

Reset type: SYSRSn

14-8SLAVE_MASKR/W7FhUsed in address detection, the slave mask enables acknowledgement
of multiple device addresses by the slave. Writing a '0' to a bit within the slave mask enables the
corresponding bit in the slave address to be either '1' or '0' and still allow for a match. Writing a '0'
to all bits in the mask enables the PMBus Interface to acknowledge any device address. Upon
power-up, the slave mask defaults to 7Fh, indicating the slave will only acknowledge the address
programmed into the Slave Address (Bits 6-0).

Reset type: SYSRSn

7MAN_SLAVE_ACKR/W0h0 = Slave automatically acknowledges device address specified in SLAVE_ADDR, Bits 6:0
1 = Enables the Manual Slave Address Acknowledgement Mode. Firmware is required to
read received address and acknowledge on every message
Note:
When bit 31 (I2C_mode) of PMBCTRL register is set it is recommended to use manual acknowledging of slave address only (MAN_SLAVE_ACK =1).

Reset type: SYSRSn

6-0SLAVE_ADDRR/W7ChConfigures the current device address of the slave. Used in automatic slave address acknowledge mode (default mode).
The PMBus Interface will compare the received device address with the value stored in the Slave Address bits and the mask
configured in the Slave Mask bits. If matching, the slave will acknowledge the device address.

Reset type: SYSRSn

20.5.2.8 PMBHSA Register (Offset = Eh) [Reset = 00000000h]

PMBHSA is shown in Figure 20-35 and described in Table 20-11.

Return to the Summary Table.

PMBUS Hold Slave Address Register

Figure 20-35 PMBHSA Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
SLAVE_ADDRSLAVE_RW
R-0hR-0h
Table 20-11 PMBHSA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-1SLAVE_ADDRR0hStored device address acknowledged by the slave

Reset type: SYSRSn

0SLAVE_RWR0hStored R/W bit from address acknowledged by the slave
0 = Write Access
1 = Read Access

Reset type: SYSRSn

20.5.2.9 PMBCTRL Register (Offset = 10h) [Reset = 00200000h]

PMBCTRL is shown in Figure 20-36 and described in Table 20-12.

Return to the Summary Table.

PMBUS Control Register

Figure 20-36 PMBCTRL Register
3130292827262524
I2CMODERESERVEDCLKDIV
R/W-0hR-0hR/W-0h
2322212019181716
CLKDIVMASTER_ENSLAVE_ENCLK_LO_DISRESERVEDRESERVEDSCL_DIRSCL_VALUE
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
SCL_MODESDA_DIRSDA_VALUESDA_MODECNTL_DIRCNTL_VALUECNTL_MODEALERT_DIR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ALERT_VALUEALERT_MODECNTL_INT_EDGERESERVEDFAST_MODEBUS_LO_INT_EDGEALERT_ENRESET
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-12 PMBCTRL Register Field Descriptions
BitFieldTypeResetDescription
31I2CMODER/W0h0 = PMBUS mode
1 = I2C mode

Reset type: SYSRSn

30-28RESERVEDR0hReserved
27-23CLKDIVR/W0hThe clock to the PMBUS transmit/receive FSMs (FSM_CLK) is
divided version of the SYSCLK clock.

Frequency(FSM_CLK) = Frequency(SYSCLK)/(CLKDIV+1)

Note: FSM_CLK should be less than (or) equal to 10MHz.

Reset type: SYSRSn

22MASTER_ENR/W0h0 = Disables PMBus Master capability
1 = Enables PMBus Master capability

Reset type: SYSRSn

21SLAVE_ENR/W1h0 = Disables PMBus Slave capability
1 = Enables PMBus Slave capability

Reset type: SYSRSn

20CLK_LO_DISR/W0h0 = Clock Low Timeout Enabled
1 = Clock Low Timeout Disabled

Reset type: SYSRSn

19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17SCL_DIRR/W0h0 = PMBus clock pin configured as output
1 = PMBus clock pin configured as input

Reset type: SYSRSn

16SCL_VALUER/W0h0 = PMBus clock pin driven low in GPIO Mode
1 = PMBus clock pin driven high in GPIO Mode

Reset type: SYSRSn

15SCL_MODER/W0h0 = PMBus clock pin configured in functional mode
1 = PMBus clock pin configured as GPIO

Reset type: SYSRSn

14SDA_DIRR/W0h0 = PMBus data pin configured as output
1 = PMBus data pin configured as input

Reset type: SYSRSn

13SDA_VALUER/W0h0 = PMBus data pin driven low in GPIO Mode
1 = PMBus data pin driven high in GPIO Mode

Reset type: SYSRSn

12SDA_MODER/W0h0 = PMBus data pin driven low in GPIO Mode
1 = PMBus data pin driven high in GPIO Mode

Reset type: SYSRSn

11CNTL_DIRR/W0h0 = Control pin configured as output
1 = Control pin configured as input

Reset type: SYSRSn

10CNTL_VALUER/W0h0 = Control pin driven low in GPIO Mode
1 = Control pin driven high in GPIO Mode

Reset type: SYSRSn

9CNTL_MODER/W0h0 = Control pin configured in functional mode (Default)
1 = Control pin configured as GPIO

Reset type: SYSRSn

8ALERT_DIRR/W0h0 = Alert pin configured as output
1 = Alert pin configured as input

Reset type: SYSRSn

7ALERT_VALUER/W0h0 = Alert pin driven low in GPIO Mode
1 = Alert pin driven high in GPIO Mode

Reset type: SYSRSn

6ALERT_MODER/W0h0 = Alert pin configured in functional mode
1 = Aler3 pin configured as GPIO

Reset type: SYSRSn

5CNTL_INT_EDGER/W0h0 = Interrupt generated on falling edge of Control
1 = Interrupt generated on rising edge of Control

Reset type: SYSRSn

4RESERVEDR/W0hReserved
3FAST_MODER/W0h0 = Standard 100 KHz mode enabled
1 = Fast Mode enabled (400KHz operation on PMBus)

Reset type: SYSRSn

2BUS_LO_INT_EDGER/W0h0 = Interrupt generated on rising edge of clock low timeout
1 = Interrupt generated on falling edge of clock low timeout

Reset type: SYSRSn

1ALERT_ENR/W0h0 = PMBus Alert is not driven by slave, pulled up high on PMBus
1 = PMBus Alert driven low by slave

Reset type: SYSRSn

0RESETR/W0h0 = No reset of internal state machines (Default)
1 = Control state machines are reset to initial states
Note: Status register PMBSTS should be explicitly cleared by reading the register after softrest as this will not be cleared by Software Reset.

Reset type: SYSRSn

20.5.2.10 PMBTIMCTL Register (Offset = 12h) [Reset = 00000000h]

PMBTIMCTL is shown in Figure 20-37 and described in Table 20-13.

Return to the Summary Table.

PMBUS Timing Control Register

Figure 20-37 PMBTIMCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTIM_OVERRIDE
R-0hR/W-0h
Table 20-13 PMBTIMCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0TIM_OVERRIDER/W0h0 PMBUS FSMs uses the default settings of the timing parameters.
1 PMBUS FSMs would use the settings in following registers:
* PMBTIMCLK
* PMBTIMSTSETUP
* PMBTIMBIDLE
* PMBTIMLOWTIMOUT
* PMBTIMHIGHTIMOUT

Reset type: SYSRSn

20.5.2.11 PMBTIMCLK Register (Offset = 14h) [Reset = 0060002Fh]

PMBTIMCLK is shown in Figure 20-38 and described in Table 20-14.

Return to the Summary Table.

PMBUS Clock Timing Register

Figure 20-38 PMBTIMCLK Register
31302928272625242322212019181716
RESERVEDCLK_FREQ
R-0hR/W-60h
1514131211109876543210
RESERVEDCLK_HIGH_LIMIT
R-0hR/W-2Fh
Table 20-14 PMBTIMCLK Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16CLK_FREQR/W60hDefines the number of PMBUS FSM input clock in the PMBUS master clock period.
Number of FSM clocks in the one clock period = (CLK_FREQ+4)

Reset type: SYSRSn

15-8RESERVEDR0hReserved
7-0CLK_HIGH_LIMITR/W2FhDefines the number of PMBUS FSM input clock in the PMBUS master clock high pulse.
Number of FSM clocks in the one clock high pulse = (CLK_HIGH_LIMIT+3)

Reset type: SYSRSn

20.5.2.12 PMBTIMSTSETUP Register (Offset = 16h) [Reset = 0000002Fh]

PMBTIMSTSETUP is shown in Figure 20-39 and described in Table 20-15.

Return to the Summary Table.

PMBUS Start Setup Time Register

Figure 20-39 PMBTIMSTSETUP Register
313029282726252423222120191817161514131211109876543210
RESERVEDTSU_STA
R-0hR/W-2Fh
Table 20-15 PMBTIMSTSETUP Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0TSU_STAR/W2FhDetermines the Setup time between last rise edge of the PMBUS master clock and the next start edge, TSU_STA value defines the setup time in terms of PMBUS FSM clock cycles.

Reset type: SYSRSn

20.5.2.13 PMBTIMBIDLE Register (Offset = 18h) [Reset = 000001F3h]

PMBTIMBIDLE is shown in Figure 20-40 and described in Table 20-16.

Return to the Summary Table.

PMBUS Bus Idle Time Register

Figure 20-40 PMBTIMBIDLE Register
313029282726252423222120191817161514131211109876543210
RESERVEDBUSIDLE
R-0hR/W-1F3h
Table 20-16 PMBTIMBIDLE Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0BUSIDLER/W1F3hDetermines the duration for which PMBUS clock and Data are 1 , to conclude that the bus is IDLE. BUSIDLE value is in terms of number of PMBUS FSM clock cycles.

Reset type: SYSRSn

20.5.2.14 PMBTIMLOWTIMOUT Register (Offset = 1Ah) [Reset = 0005572Fh]

PMBTIMLOWTIMOUT is shown in Figure 20-41 and described in Table 20-17.

Return to the Summary Table.

PMBUS Clock Low Timeout Value Register

Figure 20-41 PMBTIMLOWTIMOUT Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLKLOWTIMOUT
R-0hR/W-0005572Fh
Table 20-17 PMBTIMLOWTIMOUT Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-0CLKLOWTIMOUTR/W0005572FhDetermines the duration for which PMBUS clock if low , will result in a clock low timeout condition. CLKLOWTIMOUT value is in terms of number of PMBUS FSM clock cycles.

Reset type: SYSRSn

20.5.2.15 PMBTIMHIGHTIMOUT Register (Offset = 1Ch) [Reset = 000001F3h]

PMBTIMHIGHTIMOUT is shown in Figure 20-42 and described in Table 20-18.

Return to the Summary Table.

PMBUS Clock High Timeout Value Register

Figure 20-42 PMBTIMHIGHTIMOUT Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCLKHIGHTIMOUT
R-0hR/W-1F3h
Table 20-18 PMBTIMHIGHTIMOUT Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0CLKHIGHTIMOUTR/W1F3hDetermines the duration for which PMBUS clock if high , will result in a clock high timeout condition. CLKHIGHTIMOUT value is in terms of number of PMBUS FSM clock cycles.

Reset type: SYSRSn