SPRUIY4B February 2023 – May 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1
The test can be executed by running setting the LCM_REGS[PARITY_TEST.TESTEN] bits to the appropriate value.
Once the TESTEN register bits are set, the actual registers are no longer accessible in the memory map. Instead, the one bit parity error status values are accessible for every byte in the registers. Parity is computed for every byte, and the corresponding parity pass/fail value is available at the bit 0 location of every byte, in-place. A 0 in the bit 0 location corresponds to a pass; a 1 in the bit 0 location corresponds to a fail.
To actually inject an error, the value 1 can then be written to the bit 0 location of any byte. This inverts the stored parity value, and therefore inject an error into the parity test mechanism. Note that this propagates as an NMI like an actual parity error, and must therefore be handled within the parity error NMI.