SPRUIY5A February   2021  – July 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   Trademarks
  2. 1 Stackup
  3. 2 Floorplan Component Placement
  4. 3 Critical Interfaces Impact Placement
  5. 4 Route Critical Interfaces First
  6. 5 Route SERDES Interfaces First
  7. 6 Route DDR Signals
    1. 6.1 Address, Command, Control, and Clock Group Routes
    2. 6.2 Data Group Routes
  8. 7 Complete Power Decoupling
  9. 8 Route Lowest Priority Interfaces
  10. 9 References
  11. 10Revision History

4 Route Critical Interfaces First

As indicated above, critical interfaces affect component placement options. When routing begins, these critical interfaces must be routed first. The design team must establish a priority for the different interfaces. Those with higher priority must be completed before implementing those of lower priority. PCB layout teams often waste considerable effort ripping up and re-routing traces for lower priority interfaces when deficiencies are found in the routing of more critical interfaces. Always complete routing for the critical interfaces first.

Table 4-1 lists a recommended priority order for interfaces contained on the AM64x and AM243x families of devices. Individual design requirements may cause this list to change, but this provides a good baseline.

Table 4-1 Routing Priority
Interface Routing Priority
PCIe/USB3 10 (Highest Priority)
DDR4/LPDDR4 9
USB2, OSPI 8
Power distribution 7
RGMII 6
QSPI 6
eMMC 5
Clocks 5
MII / RMII 4
SPI 4
Motor control 4
Analog audio 3
GPMC 2
GPIO 1
UART 1
I2C 1 (Lowest Priority)

The placement of most of these should appear obvious. The multi-gigabit SERDES interfaces are the most critical due to their data rate and loss concerns. PCIe is at the top because it is very sensitive to PCB losses. The limited length for these routes might affect the PCB placement of the PCIe connector and the AM64x device. PCIe signals are found on the outer rings of the BGA footprint, allowing the traces to escape from the BGA without vias.

The asynchronous and low-speed interfaces are at the bottom. This leaves the synchronous and source-synchronous interfaces on the top, ordered by data rate. The one surprise may be power distribution. Power distribution is often left to last, but this can then result in poor decoupling performance or current starvation and excessive power supply noise due to insufficient copper to carry the power and ground currents. Space for copper and decoupling must be allocated before routing the middle and low priority interfaces.