SPRUIY5A February   2021  – July 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   Trademarks
  2. 1 Stackup
  3. 2 Floorplan Component Placement
  4. 3 Critical Interfaces Impact Placement
  5. 4 Route Critical Interfaces First
  6. 5 Route SERDES Interfaces First
  7. 6 Route DDR Signals
    1. 6.1 Address, Command, Control, and Clock Group Routes
    2. 6.2 Data Group Routes
  8. 7 Complete Power Decoupling
  9. 8 Route Lowest Priority Interfaces
  10. 9 References
  11. 10Revision History

6 Route DDR Signals

The AM64x supports connection to DDR4 and LPDDR4 devices. The DDR signals must be routed next. For detailed recommendations for DDR routing, see the AM64x DDR Board Design and Layout Guidelines. Figure 6-1 through Figure 6-3 show the BGA breakout for the DDR4 on the AM64x GP EVM. Routing for LPDDR4 uses a similar escape.

The DDR4 SDRAM memory devices are normally arranged so that the data group balls are closest to the AM64x device. The pin placement of the DDR4 signals on the AM64x places the address and command signals between data byte lane1 and data byte lane0. To achieve an escape on four layers it was necessary to rotate the DDR4 memory and place the address pins closer to the AM64x. Since the EVM uses a single x16-bit DDR4 memory device, the added trace length for the data lines is not significant.

Figure 6-1 DDR4 Address and Data Top Layer
Figure 6-2 DDR4 Address on Sig1 Layer
Figure 6-3 DDR4 Address on Bottom Layer