SPRUIY8 October   2024 F29H850TU , F29H859TU-Q1 , TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28343-Q1 , TMS320C28344 , TMS320C28345 , TMS320C28346 , TMS320C28346-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2C28 to C29 CPU Migration
    1. 2.1 Use Cases
    2. 2.2 Key Differences
    3. 2.3 Source Code Migration
      1. 2.3.1 C/C++ Source Code
        1. 2.3.1.1 Pragmas and Attributes
        2. 2.3.1.2 Macros
        3. 2.3.1.3 Intrinsics
        4. 2.3.1.4 Inline assembly
        5. 2.3.1.5 Keywords
        6. 2.3.1.6 Data Type Differences
        7. 2.3.1.7 Tooling support for Migration
      2. 2.3.2 Assembly Language Source Code
    4. 2.4 Toolchain Migration
      1. 2.4.1 Compiler
      2. 2.4.2 Linker
      3. 2.4.3 CCS Project Migration
  6. 3CLA to C29 CPU Migration
    1. 3.1 Use Cases
    2. 3.2 Key Differences
    3. 3.3 Source Code Migration
      1. 3.3.1 C/C++ Source Code
        1. 3.3.1.1 Data Type Differences
        2. 3.3.1.2 Migrating CLAmath.h Functions and Intrinsics
        3. 3.3.1.3 Migrating C28 and CLA to the Same C29 CPU
        4. 3.3.1.4 Migrating C28 and CLA to Different C29 CPUs
      2. 3.3.2 Assembly Language Source Code
    4. 3.4 Toolchain Migration
  7. 4References

3.2 Key Differences

The key differences between the CLA and C29 Programming models are summarized in Table 3-3.

Table 3-1 CLA vs C29 Programming Model Differences
ItemCLAC29
Instruction issue per clock cycleSingleVLIW - Multiple (up to 8)
Pipeline stages89
Memory accessLSRAM onlyRAM and Flash
8b byte addressabilityNoYes
Registers4 x 32-bit floating point
2x 16-bit Auxiliary		16 x 64-bit floating point

(pairs of 32-bit floating point registers)


8 x 64-bit fixed point

(pairs of 32-bit fixed point registers)


16 x 32-bit addressing
Stack reach16-bit Stack Pointer (SP)32-bit Stack Pointer (A15)
Instruction width(s)32-bit16-bit, 32-bit, 48-b

it

Bus widths1 x 32-bit Data Read (32-bit address)
1 x 32-bit Data Write (32-bit address)
1 x 32-bit Program Read (16-bit address)		2 x 64-bit Data Read (32-bit address)
1 x 64-bit Data Write (32-bit address)
1 x 128-bit Program Read (32-bit address)