SPRUIY9B May 2021 – October 2023
The SK EVM has 2GB, 16bit wide LPDDR4 memory with operating data rate of 4226Mbps per pin. Micron's MT53E1G16D1FW-046 WT: A is used. The LPDDR memory is mounted on-board (single chip) and requires 1.1V and thus reduces power demand. The LPDDR4 device requires I/O power and core 2 power of 1.1V, DRAM activating power supply (core 1) of 1.8V.
LPDDR4 reset is active low signal, which is controlled by SOC and the signal is pulled up to set the default active state and a footprint for pull-down is also provided. A 240 Ω resistor is connected from ZQ pin to 1.1V supply for LPDDR4 device and SoC DDR0_CAL pin is grounded.
The ODT (On Die Termination) is applied to DQ, DQS and DM_n signals. The device is capable of providing three different ODT modes: Nominal, Dynamic and Park with termination values: RTT (Park), RTT (NOM), and RTT (WR). Figure 4-14 shows the DDR interface between LPDDR4 and AM64x.