SPRUIY9B May   2021  – October 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Key Features
  5. 2EVM Revisions and Assembly Variants
  6. 3Important Usage Notes
  7. 4System Description
    1. 4.1 Key Features
    2. 4.2 Functional Block Diagram
    3. 4.3 Power-On/Off Procedures
      1. 4.3.1 Power-On Procedure
      2. 4.3.2 Power-Off Procedure
    4. 4.4 Peripheral and Major Component Description
      1. 4.4.1  Clocking
        1. 4.4.1.1 Ethernet PHY Clock
        2. 4.4.1.2 AM64x SoC Clock
      2. 4.4.2  Reset
      3. 4.4.3  Power
        1. 4.4.3.1 Power Input
        2. 4.4.3.2 USB Type-C Interface for Power Input
        3. 4.4.3.3 Power Fault Indication
        4. 4.4.3.4 Power Supply
        5. 4.4.3.5 Power Sequencing
        6. 4.4.3.6 Power Supply
      4. 4.4.4  Configuration
        1. 4.4.4.1 Boot Modes
      5. 4.4.5  JTAG
      6. 4.4.6  Test Automation
      7. 4.4.7  UART Interface
      8. 4.4.8  Memory Interfaces
        1. 4.4.8.1 LPDDR4 Interface
        2. 4.4.8.2 MMC Interface
          1. 4.4.8.2.1 Micro SD Interface
          2. 4.4.8.2.2 WiLink Interface
          3. 4.4.8.2.3 OSPI Interface
          4. 4.4.8.2.4 Board ID EEPROM Interface
      9. 4.4.9  Ethernet Interface
        1. 4.4.9.1 DP83867 PHY Default Configuration
        2. 4.4.9.2 DP83867 – Power, Clock, Reset, Interrupt and LEDs
        3. 4.4.9.3 Industrial Application LEDs
      10. 4.4.10 USB 3.0 Interface
      11. 4.4.11 PRU Connector
      12. 4.4.12 User Expansion Connector
      13. 4.4.13 MCU Connector
      14. 4.4.14 Interrupt
      15. 4.4.15 I2C Interface
      16. 4.4.16 IO Expander (GPIOs)
  8. 5Known Issues
    1. 5.1 Issue 1: LP8733x Max output Capacitance Spec Exceeded on LDO0 and LDO1
    2. 5.2 Issue 2: LP8733x Output Voltage of 0.9V Exceeds AM64x VDDR_CORE max Voltage Spec of 0.895 V
    3. 5.3 Issue 3 - SDIO Devices on MMC0 Require Careful Trace Lengths to Meet Interface Timing Requirements
    4. 5.4 Issue 4 - LPDDR4 Data Rate Limitation in Stressful Conditions
    5. 5.5 Issue 5 - Junk Character
    6. 5.6 Issue 6 - Test Power Down Signal Floating
    7. 5.7 Issue 7 - uSD Boot Not Working
  9. 6Regulatory Compliance
  10. 7Revision History

4.4.12 User Expansion Connector

This connector is compatible with the standard expansion connector found on a Raspberry Pi®™ 4B allowing seamless interface with HAT boards. Four mounting holes must be oriented with the connector to allow for connection of these boards. Signals connected from SoC to the Expansion Header include: SPI (0), SPI (1), UART (5), I2C (0), I2C (2), EHRPWM4_A / B, EHRPWM5_A / B along with GPIOs [32, 35, 38, 39, 40, 41, 42] along with 5 V and 3.3V PWR and GND. Each of the power supplies 5 V and 3.3V are current limited to 155 mA and 500 mA respectively. This is achieved by using load switch TPS22902YFPR. Enable for the load switch is controlled by IO expander. Signals routed from User Expansion connector are listed in Table 4-21.

Table 4-21 40 Pin User Expansion Connector
Pin Net Name Pin Net Name
1 VCC3V3_RPI 2 VCC5V0_RPI
3 RPI_I2C2_SDA 4 VCC5V0_RPI
5 RPI_I2C2_SCL 6 DGND
7 RPI_GPIO0_35 8 SOC_MAIN_UART5_TXD
9 DGND 10 SOC_MAIN_UART5_RXD
11 RPI_SPI1_CS1 12 RPI_SPI1_CS0
13 RPI_GPIO0_42 14 DGND
15 RPI_GPIO0_32 16 RPI_GPIO0_38
17 VCC3V3_RPI 18 RPI_GPIO0_39
19 RPI_SPI0_D0 20 DGND
21 RPI_SPI0_D1 22 RPI_GPIO0_40
23 RPI_SPI0_CLK 24 RPI_SPI0_CS0
25 DGND 26 RPI_SPI0_CS1
27 SoC_I2C0_SDA 28 SoC_I2C0_SCL
29 RPI_ETHRPWM5_A 30 DGND
31 RPI_ETHRPWM5_B 32 RPI_ETHRPWM4_A
33 RPI_ETHRPWM4_B 34 DGND
35 RPI_SPI1_D1 36 RPI_SPI1_CS2
37 RPI_GPIO0_41 38 RPI_SPI1_D0
39 RPI_HAT_DETECT 40 RPI_SPI1_CLK
GUID-F15B54BF-0710-4B23-AC87-F322B7903EA3-low.png Figure 4-25 40-Pin User Expansion Connector