SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
A software initialization begins when the MCAN_CCCR.INIT bit is set to 1. This is done either by software or by a hardware reset, when an uncorrected bit error is detected in the Message RAM, or by going to a Bus_Off state. While the MCAN_CCCR.INIT bit is set, the message transfer is stopped and the status of the output TX pin is recessive (high). The counters of the Error Management Logic (EML) are unchanged. Setting the MCAN_CCCR.INIT bit does not change any configuration register. Resetting the MCAN_CCCR.INIT bit finishes the software initialization. After waiting for the occurrence of a sequence of 11 consecutive recessive bits (indication for Bus_Idle state) the message transfer starts.
Access to the MCAN configuration registers is only enabled when both MCAN_CCCR.INIT and MCAN_CCCR.CCE bits are set (write protection).
The MCAN_CCCR.CCE bit can only be set/reset while the MCAN_CCCR.INIT = 1. The MCAN_CCCR.CCE bit is automatically reset when the MCAN_CCCR.INIT bit is reset.
The following registers are reset when the MCAN_CCCR.CCE bit is set:
The Timeout Counter value MCAN_TOCV.TOC field is preset to the value configured by the MCAN_TOCC.TOP field when the MCAN_CCCR.CCE bit is set.
In addition, the Tx Handler and Rx Handler are held in idle state while MCAN_CCCR.CCE = 1.
The following registers are only writable while MCAN_CCCR.CCE = 0
MCAN_CCCR.TEST and MCAN_CCCR.MON bits can only be set by the Host CPU while MCAN_CCCR.INIT = 1 and MCAN_CCCR.CCE = 1. Both bits are reset at any time. The MCAN_CCCR.DAR bit can only be set/reset while MCAN_CCCR.INIT = 1 and MCAN_CCCR.CCE = 1.
Table 35-4 shows the steps to configure the MCAN module.
Step | Operation | Description | Pseudo Code |
---|---|---|---|
1 | Initialize MCAN_CCCR | Set
MCAN_CCCR.INIT bit and check that the bit has been set |
INIT = 1; If INIT ≠ 1, wait until set |
2 | Unlock protected registers | Set MCAN_CCCR.CCE bit | CCE = 1; |
3 | Configure CAN mode | Set MCAN_CCCR.FDOE bit to CAN FD | FDOE = 1 for CAN
FD FDOE = 0 for Classic CAN |
4 | Configure Bit Rate Switching | Set MCAN_CCCR.BRSE bit | BRSE = 1 for bit
rate switching BRSE = 0 for no bit rate switching |
5 | Set nominal bit timing(1) | Set MCAN_NBTP register | |
6 | Lock protected registers | Clear MCAN_CCCR.CCE bit | CCE = 0; |
7 | Return MCAN module to normal operation | Clear
MCAN_CCCR.INIT bit and check that the bit has been cleared |
INIT = 0; If INIT ≠ 0, wait until cleared |