SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
Table 34-6 lists the memory-mapped registers for the EPG_REGS registers. All register offset addresses not listed in Table 34-6 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | GCTL0 | EPG Global control register 0 | Go | |
2h | GCTL1 | EPG Global control register 1 | Go | |
4h | GCTL2 | EPG Global control register 2 | Go | |
6h | GCTL3 | EPG Global control register 3 | Go | |
8h | EPGLOCK | EPG LOCK Register | Go | |
Ah | EPGCOMMIT | EPG COMMIT register | Go | |
Ch | GINTSTS | EPG Global interrupt status register. | Go | |
Eh | GINTEN | EPG Global interrupt enable register. | Go | |
10h | GINTCLR | EPG Global interrupt clear register. | Go | |
12h | GINTFRC | EPG Global interrupt force register. | Go | |
18h | CLKDIV0_CTL0 | Clock divider 0's control register 0 | Go | |
1Eh | CLKDIV0_CLKOFFSET | Clock divider 0's clock offset value | Go | |
24h | CLKDIV1_CTL0 | Clock divider 1's control register 0 | Go | |
2Ah | CLKDIV1_CLKOFFSET | Clock divider 1's clock offset value | Go | |
30h | SIGGEN0_CTL0 | Signal generator 0's control register 0 | Go | |
32h | SIGGEN0_CTL1 | Signal generator 0's control register 1 | Go | |
38h | SIGGEN0_DATA0 | Signal generator 0's data register 0 | Go | |
3Ah | SIGGEN0_DATA1 | Signal generator 0's data register 1 | Go | |
3Ch | SIGGEN0_DATA0_ACTIVE | Signal generator 0's data active register 0 | Go | |
3Eh | SIGGEN0_DATA1_ACTIVE | Signal generator 0's data active register 1 | Go | |
50h | REVISION | IP Revision tie-off value | Go |
Complex bit access types are encoded to fit into small table cells. Table 34-7 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
GCTL0 is shown in Figure 34-8 and described in Table 34-8.
Return to the Summary Table.
EPG Global control register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EPGOUT23SEL | EPGOUT22SEL | EPGOUT21SEL | EPGOUT20SEL | EPGOUT17SEL | EPGOUT16SEL | EPGOUT15SEL | EPGOUT13SEL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SIGGEN1_EN | SIGGEN0_EN | EN | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | EPGOUT23SEL | R/W | 0h | 0 : Selects signal mux output 1 : Selects clock mux output Reset type: SYSRSn |
14 | EPGOUT22SEL | R/W | 0h | 0 : Selects signal mux output 1 : Selects clock mux output Reset type: SYSRSn |
13 | EPGOUT21SEL | R/W | 0h | 0 : Selects signal mux output 1 : Selects clock mux output Reset type: SYSRSn |
12 | EPGOUT20SEL | R/W | 0h | 0 : Selects signal mux output 1 : Selects clock mux output Reset type: SYSRSn |
11 | EPGOUT17SEL | R/W | 0h | 0 : Selects signal mux output 1 : Selects clock mux output Reset type: SYSRSn |
10 | EPGOUT16SEL | R/W | 0h | 0 : Selects signal mux output 1 : Selects clock mux output Reset type: SYSRSn |
9 | EPGOUT15SEL | R/W | 0h | 0 : Selects signal mux output 1 : Selects clock mux output Reset type: SYSRSn |
8 | EPGOUT13SEL | R/W | 0h | 0 : Selects signal mux output 1 : Selects clock mux output Reset type: SYSRSn |
7-3 | RESERVED | R | 0h | Reserved |
2 | SIGGEN1_EN | R/W | 0h | 0 : Signal generator 1 is disabled. 1 : Signal generator 1 is enabled, signal generator functions as per the mode definition. Reset type: SYSRSn |
1 | SIGGEN0_EN | R/W | 0h | 0 : Signal generator 0 is disabled. 1 : Signal generator 0 is enabled, signal generator functions as per the mode definition. Reset type: SYSRSn |
0 | EN | R/W | 0h | 0 : EPG module is disabled 1 : EPG module is enabled, clock generators and signal generators are functional. Reset type: SYSRSn |
GCTL1 is shown in Figure 34-9 and described in Table 34-9.
Return to the Summary Table.
EPG Global control register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | SIGGEN0_CLKSEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6-4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2-0 | SIGGEN0_CLKSEL | R/W | 0h | Clock source select of SIGGEN0: 0x0 : CLKGEN0.CLKOUT0_GCLK 0x1 : CLKGEN0.CLKOUT1_GCLK 0x2 : CLKGEN0.CLKOUT2_GCLK 0x3 : CLKGEN0.CLKOUT3_GCLK 0x4 : CLKGEN1.CLKOUT0_GCLK 0x5 : CLKGEN1.CLKOUT1_GCLK 0x6 : CLKGEN1.CLKOUT2_GCLK 0x7 : CLKGEN1.CLKOUT3_GCLK Reset type: SYSRSn |
GCTL2 is shown in Figure 34-10 and described in Table 34-10.
Return to the Summary Table.
EPG Global control register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EPGOUT7_CLKOUTSEL | RESERVED | EPGOUT6_CLKOUTSEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EPGOUT5_CLKOUTSEL | RESERVED | EPGOUT4_CLKOUTSEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | EPGOUT3_CLKOUTSEL | RESERVED | EPGOUT2_CLKOUTSEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EPGOUT1_CLKOUTSEL | RESERVED | EPGOUT0_CLKOUTSEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30-28 | EPGOUT7_CLKOUTSEL | R/W | 0h | Output 7 signal source select: 0x0 : CLKGEN0.CLKOUT0_DCLK 0x1 : CLKGEN0.CLKOUT1_DCLK 0x2 : CLKGEN0.CLKOUT2_DCLK 0x3 : CLKGEN0.CLKOUT3_DCLK 0x4 : CLKGEN1.CLKOUT0_DCLK 0x5 : CLKGEN1.CLKOUT1_DCLK 0x6 : CLKGEN1.CLKOUT2_DCLK 0x7 : CLKGEN1.CLKOUT3_DCLK Reset type: SYSRSn |
27 | RESERVED | R/W | 0h | Reserved |
26-24 | EPGOUT6_CLKOUTSEL | R/W | 0h | Output 6 signal source select: 0x0 : CLKGEN0.CLKOUT0_DCLK 0x1 : CLKGEN0.CLKOUT1_DCLK 0x2 : CLKGEN0.CLKOUT2_DCLK 0x3 : CLKGEN0.CLKOUT3_DCLK 0x4 : CLKGEN1.CLKOUT0_DCLK 0x5 : CLKGEN1.CLKOUT1_DCLK 0x6 : CLKGEN1.CLKOUT2_DCLK 0x7 : CLKGEN1.CLKOUT3_DCLK Reset type: SYSRSn |
23 | RESERVED | R/W | 0h | Reserved |
22-20 | EPGOUT5_CLKOUTSEL | R/W | 0h | Output 5 signal source select: 0x0 : CLKGEN0.CLKOUT0_DCLK 0x1 : CLKGEN0.CLKOUT1_DCLK 0x2 : CLKGEN0.CLKOUT2_DCLK 0x3 : CLKGEN0.CLKOUT3_DCLK 0x4 : CLKGEN1.CLKOUT0_DCLK 0x5 : CLKGEN1.CLKOUT1_DCLK 0x6 : CLKGEN1.CLKOUT2_DCLK 0x7 : CLKGEN1.CLKOUT3_DCLK Reset type: SYSRSn |
19 | RESERVED | R/W | 0h | Reserved |
18-16 | EPGOUT4_CLKOUTSEL | R/W | 0h | Output 4 signal source select: 0x0 : CLKGEN0.CLKOUT0_DCLK 0x1 : CLKGEN0.CLKOUT1_DCLK 0x2 : CLKGEN0.CLKOUT2_DCLK 0x3 : CLKGEN0.CLKOUT3_DCLK 0x4 : CLKGEN1.CLKOUT0_DCLK 0x5 : CLKGEN1.CLKOUT1_DCLK 0x6 : CLKGEN1.CLKOUT2_DCLK 0x7 : CLKGEN1.CLKOUT3_DCLK Reset type: SYSRSn |
15 | RESERVED | R/W | 0h | Reserved |
14-12 | EPGOUT3_CLKOUTSEL | R/W | 0h | Output 3 signal source select: 0x0 : CLKGEN0.CLKOUT0_DCLK 0x1 : CLKGEN0.CLKOUT1_DCLK 0x2 : CLKGEN0.CLKOUT2_DCLK 0x3 : CLKGEN0.CLKOUT3_DCLK 0x4 : CLKGEN1.CLKOUT0_DCLK 0x5 : CLKGEN1.CLKOUT1_DCLK 0x6 : CLKGEN1.CLKOUT2_DCLK 0x7 : CLKGEN1.CLKOUT3_DCLK Reset type: SYSRSn |
11 | RESERVED | R/W | 0h | Reserved |
10-8 | EPGOUT2_CLKOUTSEL | R/W | 0h | Output 2 signal source select: 0x0 : CLKGEN0.CLKOUT0_DCLK 0x1 : CLKGEN0.CLKOUT1_DCLK 0x2 : CLKGEN0.CLKOUT2_DCLK 0x3 : CLKGEN0.CLKOUT3_DCLK 0x4 : CLKGEN1.CLKOUT0_DCLK 0x5 : CLKGEN1.CLKOUT1_DCLK 0x6 : CLKGEN1.CLKOUT2_DCLK 0x7 : CLKGEN1.CLKOUT3_DCLK Reset type: SYSRSn |
7 | RESERVED | R/W | 0h | Reserved |
6-4 | EPGOUT1_CLKOUTSEL | R/W | 0h | Output 1 signal source select: 0x0 : CLKGEN0.CLKOUT0_DCLK 0x1 : CLKGEN0.CLKOUT1_DCLK 0x2 : CLKGEN0.CLKOUT2_DCLK 0x3 : CLKGEN0.CLKOUT3_DCLK 0x4 : CLKGEN1.CLKOUT0_DCLK 0x5 : CLKGEN1.CLKOUT1_DCLK 0x6 : CLKGEN1.CLKOUT2_DCLK 0x7 : CLKGEN1.CLKOUT3_DCLK Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2-0 | EPGOUT0_CLKOUTSEL | R/W | 0h | Output 0 signal source select: 0x0 : CLKGEN0.CLKOUT0_DCLK 0x1 : CLKGEN0.CLKOUT1_DCLK 0x2 : CLKGEN0.CLKOUT2_DCLK 0x3 : CLKGEN0.CLKOUT3_DCLK 0x4 : CLKGEN1.CLKOUT0_DCLK 0x5 : CLKGEN1.CLKOUT1_DCLK 0x6 : CLKGEN1.CLKOUT2_DCLK 0x7 : CLKGEN1.CLKOUT3_DCLK Reset type: SYSRSn |
GCTL3 is shown in Figure 34-11 and described in Table 34-11.
Return to the Summary Table.
EPG Global control register 3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EPGOUT7_SIGOUTSEL | EPGOUT6_SIGOUTSEL | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EPGOUT5_SIGOUTSEL | EPGOUT4_SIGOUTSEL | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EPGOUT3_SIGOUTSEL | EPGOUT2_SIGOUTSEL | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPGOUT1_SIGOUTSEL | EPGOUT0_SIGOUTSEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | EPGOUT7_SIGOUTSEL | R/W | 0h | Output 7 source select: 0x0 : SIGGEN0.DATATRANOUT0 0x1 : SIGGEN0.DATATRANOUT1 0x2 : SIGGEN0.DATATRANOUT2 0x3 : SIGGEN0.DATATRANOUT3 0x4 : SIGGEN0.DATATRANOUT4 0x5 : SIGGEN0.DATATRANOUT5 0x6 : SIGGEN0.DATATRANOUT6 0x7 : SIGGEN0.DATATRANOUT7 0x8 : SIGGEN1.DATATRANOUT0 0x9 : SIGGEN1.DATATRANOUT1 0xA : SIGGEN1.DATATRANOUT2 0xB : SIGGEN1.DATATRANOUT3 0xC : SIGGEN1.DATATRANOUT4 0xD : SIGGEN1.DATATRANOUT5 0xE : SIGGEN1.DATATRANOUT6 0xF : SIGGEN1.DATATRANOUT7 Reset type: SYSRSn |
27-24 | EPGOUT6_SIGOUTSEL | R/W | 0h | Output 6 source select: 0x0 : SIGGEN0.DATATRANOUT0 0x1 : SIGGEN0.DATATRANOUT1 0x2 : SIGGEN0.DATATRANOUT2 0x3 : SIGGEN0.DATATRANOUT3 0x4 : SIGGEN0.DATATRANOUT4 0x5 : SIGGEN0.DATATRANOUT5 0x6 : SIGGEN0.DATATRANOUT6 0x7 : SIGGEN0.DATATRANOUT7 0x8 : SIGGEN1.DATATRANOUT0 0x9 : SIGGEN1.DATATRANOUT1 0xA : SIGGEN1.DATATRANOUT2 0xB : SIGGEN1.DATATRANOUT3 0xC : SIGGEN1.DATATRANOUT4 0xD : SIGGEN1.DATATRANOUT5 0xE : SIGGEN1.DATATRANOUT6 0xF : SIGGEN1.DATATRANOUT7 Reset type: SYSRSn |
23-20 | EPGOUT5_SIGOUTSEL | R/W | 0h | Output 5 source select: 0x0 : SIGGEN0.DATATRANOUT0 0x1 : SIGGEN0.DATATRANOUT1 0x2 : SIGGEN0.DATATRANOUT2 0x3 : SIGGEN0.DATATRANOUT3 0x4 : SIGGEN0.DATATRANOUT4 0x5 : SIGGEN0.DATATRANOUT5 0x6 : SIGGEN0.DATATRANOUT6 0x7 : SIGGEN0.DATATRANOUT7 0x8 : SIGGEN1.DATATRANOUT0 0x9 : SIGGEN1.DATATRANOUT1 0xA : SIGGEN1.DATATRANOUT2 0xB : SIGGEN1.DATATRANOUT3 0xC : SIGGEN1.DATATRANOUT4 0xD : SIGGEN1.DATATRANOUT5 0xE : SIGGEN1.DATATRANOUT6 0xF : SIGGEN1.DATATRANOUT7 Reset type: SYSRSn |
19-16 | EPGOUT4_SIGOUTSEL | R/W | 0h | Output 4 source select: 0x0 : SIGGEN0.DATATRANOUT0 0x1 : SIGGEN0.DATATRANOUT1 0x2 : SIGGEN0.DATATRANOUT2 0x3 : SIGGEN0.DATATRANOUT3 0x4 : SIGGEN0.DATATRANOUT4 0x5 : SIGGEN0.DATATRANOUT5 0x6 : SIGGEN0.DATATRANOUT6 0x7 : SIGGEN0.DATATRANOUT7 0x8 : SIGGEN1.DATATRANOUT0 0x9 : SIGGEN1.DATATRANOUT1 0xA : SIGGEN1.DATATRANOUT2 0xB : SIGGEN1.DATATRANOUT3 0xC : SIGGEN1.DATATRANOUT4 0xD : SIGGEN1.DATATRANOUT5 0xE : SIGGEN1.DATATRANOUT6 0xF : SIGGEN1.DATATRANOUT7 Reset type: SYSRSn |
15-12 | EPGOUT3_SIGOUTSEL | R/W | 0h | Output 3 source select: 0x0 : SIGGEN0.DATATRANOUT0 0x1 : SIGGEN0.DATATRANOUT1 0x2 : SIGGEN0.DATATRANOUT2 0x3 : SIGGEN0.DATATRANOUT3 0x4 : SIGGEN0.DATATRANOUT4 0x5 : SIGGEN0.DATATRANOUT5 0x6 : SIGGEN0.DATATRANOUT6 0x7 : SIGGEN0.DATATRANOUT7 0x8 : SIGGEN1.DATATRANOUT0 0x9 : SIGGEN1.DATATRANOUT1 0xA : SIGGEN1.DATATRANOUT2 0xB : SIGGEN1.DATATRANOUT3 0xC : SIGGEN1.DATATRANOUT4 0xD : SIGGEN1.DATATRANOUT5 0xE : SIGGEN1.DATATRANOUT6 0xF : SIGGEN1.DATATRANOUT7 Reset type: SYSRSn |
11-8 | EPGOUT2_SIGOUTSEL | R/W | 0h | Output 2 source select: 0x0 : SIGGEN0.DATATRANOUT0 0x1 : SIGGEN0.DATATRANOUT1 0x2 : SIGGEN0.DATATRANOUT2 0x3 : SIGGEN0.DATATRANOUT3 0x4 : SIGGEN0.DATATRANOUT4 0x5 : SIGGEN0.DATATRANOUT5 0x6 : SIGGEN0.DATATRANOUT6 0x7 : SIGGEN0.DATATRANOUT7 0x8 : SIGGEN1.DATATRANOUT0 0x9 : SIGGEN1.DATATRANOUT1 0xA : SIGGEN1.DATATRANOUT2 0xB : SIGGEN1.DATATRANOUT3 0xC : SIGGEN1.DATATRANOUT4 0xD : SIGGEN1.DATATRANOUT5 0xE : SIGGEN1.DATATRANOUT6 0xF : SIGGEN1.DATATRANOUT7 Reset type: SYSRSn |
7-4 | EPGOUT1_SIGOUTSEL | R/W | 0h | Output 1 source select: 0x0 : SIGGEN0.DATATRANOUT0 0x1 : SIGGEN0.DATATRANOUT1 0x2 : SIGGEN0.DATATRANOUT2 0x3 : SIGGEN0.DATATRANOUT3 0x4 : SIGGEN0.DATATRANOUT4 0x5 : SIGGEN0.DATATRANOUT5 0x6 : SIGGEN0.DATATRANOUT6 0x7 : SIGGEN0.DATATRANOUT7 0x8 : SIGGEN1.DATATRANOUT0 0x9 : SIGGEN1.DATATRANOUT1 0xA : SIGGEN1.DATATRANOUT2 0xB : SIGGEN1.DATATRANOUT3 0xC : SIGGEN1.DATATRANOUT4 0xD : SIGGEN1.DATATRANOUT5 0xE : SIGGEN1.DATATRANOUT6 0xF : SIGGEN1.DATATRANOUT7 Reset type: SYSRSn |
3-0 | EPGOUT0_SIGOUTSEL | R/W | 0h | Output 0 source select: 0x0 : SIGGEN0.DATATRANOUT0 0x1 : SIGGEN0.DATATRANOUT1 0x2 : SIGGEN0.DATATRANOUT2 0x3 : SIGGEN0.DATATRANOUT3 0x4 : SIGGEN0.DATATRANOUT4 0x5 : SIGGEN0.DATATRANOUT5 0x6 : SIGGEN0.DATATRANOUT6 0x7 : SIGGEN0.DATATRANOUT7 0x8 : SIGGEN1.DATATRANOUT0 0x9 : SIGGEN1.DATATRANOUT1 0xA : SIGGEN1.DATATRANOUT2 0xB : SIGGEN1.DATATRANOUT3 0xC : SIGGEN1.DATATRANOUT4 0xD : SIGGEN1.DATATRANOUT5 0xE : SIGGEN1.DATATRANOUT6 0xF : SIGGEN1.DATATRANOUT7 Reset type: SYSRSn |
EPGLOCK is shown in Figure 34-12 and described in Table 34-12.
Return to the Summary Table.
EPG LOCK Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGGEN0_CTL1 | SIGGEN0_CTL0 | CLKDIV1_CTL0 | CLKDIV0_CTL0 | GCTL3 | GCTL2 | GCTL1 | GCTL0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | SIGGEN0_CTL1 | R/W | 0h | 0: Writes to SIGGEN0_CTL1 register is allowed. 1: Writes to SIGGEN0_CTL1 register is not allowed. Reset type: SYSRSn |
6 | SIGGEN0_CTL0 | R/W | 0h | 0: Writes to SIGGEN0_CTL0 register is allowed. 1: Writes to SIGGEN0_CTL0 register is not allowed. Reset type: SYSRSn |
5 | CLKDIV1_CTL0 | R/W | 0h | 0: Writes to CLKDIV1_CTL0 register is allowed. 1: Writes to CLKDIV1_CTL0 register is not allowed. Reset type: SYSRSn |
4 | CLKDIV0_CTL0 | R/W | 0h | 0: Writes to CLKDIV0_CTL0 register is allowed. 1: Writes to CLKDIV0_CTL0 register is not allowed. Reset type: SYSRSn |
3 | GCTL3 | R/W | 0h | 0: Writes to GCTL3 register is allowed. 1: Writes to GCTL3 register is not allowed. Reset type: SYSRSn |
2 | GCTL2 | R/W | 0h | 0: Writes to GCTL2 register is allowed. 1: Writes to GCTL2 register is not allowed. Reset type: SYSRSn |
1 | GCTL1 | R/W | 0h | 0: Writes to GCTL1 register is allowed. 1: Writes to GCTL1 register is not allowed. Reset type: SYSRSn |
0 | GCTL0 | R/W | 0h | 0: Writes to GCTL0 register is allowed. 1: Writes to GCTL0 register is not allowed. Reset type: SYSRSn |
EPGCOMMIT is shown in Figure 34-13 and described in Table 34-13.
Return to the Summary Table.
EPG COMMIT register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/WSonce-0h | R/WSonce-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGGEN0_CTL1 | SIGGEN0_CTL0 | CLKDIV1_CTL0 | CLKDIV0_CTL0 | GCTL3 | GCTL2 | GCTL1 | GCTL0 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R/WSonce | 0h | Reserved |
8 | RESERVED | R/WSonce | 0h | Reserved |
7 | SIGGEN0_CTL1 | R/WSonce | 0h | 0: Writes to EPGLOCK.SIGGEN0_CTL1 field is allowed. 1: Writes to EPGLOCK.SIGGEN0_CTL1 field is not allowed. Reset type: SYSRSn |
6 | SIGGEN0_CTL0 | R/WSonce | 0h | 0: Writes to EPGLOCK.SIGGEN0_CTL0 field is allowed. 1: Writes to EPGLOCK.SIGGEN0_CTL0 field is not allowed. Reset type: SYSRSn |
5 | CLKDIV1_CTL0 | R/WSonce | 0h | 0: Writes to EPGLOCK.CLKDIV1_CTL0 field is allowed. 1: Writes to EPGLOCK.CLKDIV1_CTL0 field is not allowed. Reset type: SYSRSn |
4 | CLKDIV0_CTL0 | R/WSonce | 0h | 0: Writes to EPGLOCK.CLKDIV0_CTL0 field is allowed. 1: Writes to EPGLOCK.CLKDIV0_CTL0 field is not allowed. Reset type: SYSRSn |
3 | GCTL3 | R/WSonce | 0h | 0: Writes to EPGLOCK.GCTL3 field is allowed. 1: Writes to EPGLOCK.GCTL3 field is not allowed. Reset type: SYSRSn |
2 | GCTL2 | R/WSonce | 0h | 0: Writes to EPGLOCK.GCTL2 field is allowed. 1: Writes to EPGLOCK.GCTL2 field is not allowed. Reset type: SYSRSn |
1 | GCTL1 | R/WSonce | 0h | 0: Writes to EPGLOCK.GCTL1 field is allowed. 1: Writes to EPGLOCK.GCTL1 field is not allowed. Reset type: SYSRSn |
0 | GCTL0 | R/WSonce | 0h | 0: Writes to EPGLOCK.GCTL0 field is allowed. 1: Writes to EPGLOCK.GCTL0 field is not allowed. Reset type: SYSRSn |
GINTSTS is shown in Figure 34-14 and described in Table 34-14.
Return to the Summary Table.
EPG Global interrupt status register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | SIGGEN0_FILL | SIGGEN0_DONE | INT | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | SIGGEN0_FILL | R | 0h | 0: Do not fill data in SIGGEN0 1: Fill data in SIGGEN0 This status bit does not get set in BIT_BANG mode. In all other modes, the SIGGEN0_FILL bit is set high after the signal generator has completed BITLENGTH/2 shifts. Note: For odd values of BITLENGTH, BITLENGTH/2 is rounded down to the nearest integer. Reset type: SYSRSn |
1 | SIGGEN0_DONE | R | 0h | 0: Operation of SIGGEN0 is in progress 1: Operation of SIGGEN0 has completed This status bit does not get set in BIT_BANG mode. In all other modes, the SIGGEN0_DONE bit is set high after the signal generator has completed BITLENGTH shifts. Reset type: SYSRSn |
0 | INT | R | 0h | Global interrupt flag. This bit is set when an interrupt is fired, and cleared by writing 1 to GINTCLR.INT. While the INT status bit is set, new EPG interrupts cannot be generated until the bit has been cleared. Reset type: SYSRSn |
GINTEN is shown in Figure 34-15 and described in Table 34-15.
Return to the Summary Table.
EPG Global interrupt enable register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | SIGGEN0_FILL | SIGGEN0_DONE | RESERVED | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | SIGGEN0_FILL | R/W | 0h | 0: Disable interrupt generation when SIGGEN0_FILL bits is set. 1: Enable interrupt generation when SIGGEN0_FILL bits is set. Reset type: SYSRSn |
1 | SIGGEN0_DONE | R/W | 0h | 0: Disable interrupt generation when SIGGEN0_DONE bits is set. 1: Enable interrupt generation when SIGGEN0_DONE bits is set. Reset type: SYSRSn |
0 | RESERVED | R | 0h | Reserved |
GINTCLR is shown in Figure 34-16 and described in Table 34-16.
Return to the Summary Table.
EPG Global interrupt clear register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | SIGGEN0_FILL | SIGGEN0_DONE | INT | ||
R-0h | R-0/W1C-0h | R-0/W1C-0h | R-0/W1C-0h | R-0/W1C-0h | R-0/W1C-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R-0/W1C | 0h | Reserved |
3 | RESERVED | R-0/W1C | 0h | Reserved |
2 | SIGGEN0_FILL | R-0/W1C | 0h | 0: No effect 1: Clear SIGGEN0_FILL flag bit. Reset type: SYSRSn |
1 | SIGGEN0_DONE | R-0/W1C | 0h | 0: No effect 1: Clear SIGGEN0_DONE flag bit. Reset type: SYSRSn |
0 | INT | R-0/W1C | 0h | 0: No effect 1: Clear INT flag bit. Reset type: SYSRSn |
GINTFRC is shown in Figure 34-17 and described in Table 34-17.
Return to the Summary Table.
EPG Global interrupt force register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | SIGGEN0_FILL | SIGGEN0_DONE | RESERVED | ||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | SIGGEN0_FILL | R-0/W1S | 0h | 0: No effect 1: set SIGGEN0_FILL flag bit. Reset type: SYSRSn |
1 | SIGGEN0_DONE | R-0/W1S | 0h | 0: No effect 1: set SIGGEN0_DONE flag bit. Reset type: SYSRSn |
0 | RESERVED | R | 0h | Reserved |
CLKDIV0_CTL0 is shown in Figure 34-18 and described in Table 34-18.
Return to the Summary Table.
Clock divider 0's control register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CLKSTOP | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRD | |||||||||||||||
R/W-0h | |||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | CLKSTOP | R/W | 0h | Determines on which of the CLKOUTs edge clock generation is stopped following a clear of SIGGEN0_CTL0.EN. 000 : Stop on CLKOUT0 010 : Stop on CLKOUT1 100 : Stop on CLKOUT2 110 : Stop on CLKOUT3 Reset type: SYSRSn |
15-0 | PRD | R/W | 0h | Clock divider period: Clock divider counter counts up to period (PRD) and snaps back to 0. Reset type: SYSRSn |
CLKDIV0_CLKOFFSET is shown in Figure 34-19 and described in Table 34-19.
Return to the Summary Table.
Clock divider 0's clock offset value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLK3OFFSET | CLK2OFFSET | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK1OFFSET | CLK0OFFSET | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | CLK3OFFSET | R/W | 0h | Number of source clock cycles by which the divided clock output 3 (CLKOUT3) is delayed. Reset type: SYSRSn |
23-16 | CLK2OFFSET | R/W | 0h | Number of source clock cycles by which the divided clock output 2 (CLKOUT2) is delayed. Reset type: SYSRSn |
15-8 | CLK1OFFSET | R/W | 0h | Number of source clock cycles by which the divided clock output 1 (CLKOUT1) is delayed. Reset type: SYSRSn |
7-0 | CLK0OFFSET | R/W | 0h | Number of source clock cycles by which the divided clock output 0 (CLKOUT0) is delayed. Reset type: SYSRSn |
CLKDIV1_CTL0 is shown in Figure 34-20 and described in Table 34-20.
Return to the Summary Table.
Clock divider 1's control register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CLKSTOP | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRD | |||||||||||||||
R/W-0h | |||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | CLKSTOP | R/W | 0h | Determines on which of the CLKOUTs edge clock generation is stopped following a clear of SIGGEN1_CTL0.EN. 000 : Stop on CLKOUT0 010 : Stop on CLKOUT1 100 : Stop on CLKOUT2 110 : Stop on CLKOUT3 Reset type: SYSRSn |
15-0 | PRD | R/W | 0h | Clock divider period: Clock divider counter counts up to period (PRD) and snaps back to 0. Reset type: SYSRSn |
CLKDIV1_CLKOFFSET is shown in Figure 34-21 and described in Table 34-21.
Return to the Summary Table.
Clock divider 1's clock offset value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLK3OFFSET | CLK2OFFSET | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK1OFFSET | CLK0OFFSET | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | CLK3OFFSET | R/W | 0h | Number of source clock cycles by which the divided clock output 3 (CLKOUT3) is delayed. Reset type: SYSRSn |
23-16 | CLK2OFFSET | R/W | 0h | Number of source clock cycles by which the divided clock output 2 (CLKOUT2) is delayed. Reset type: SYSRSn |
15-8 | CLK1OFFSET | R/W | 0h | Number of source clock cycles by which the divided clock output 1 (CLKOUT1) is delayed. Reset type: SYSRSn |
7-0 | CLK0OFFSET | R/W | 0h | Number of source clock cycles by which the divided clock output 0 (CLKOUT0) is delayed. Reset type: SYSRSn |
SIGGEN0_CTL0 is shown in Figure 34-22 and described in Table 34-22.
Return to the Summary Table.
Signal generator 0's control register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BITLENGTH | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BROUT | BRIN | RESERVED | MODE | |||
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-16 | BITLENGTH | R/W | 0h | Defines the number bits which participates in the shift rotate operations. Reset type: SYSRSn |
15-7 | RESERVED | R | 0h | Reserved |
6 | BROUT | R/W | 0h | 0 : No bit reversal on data output from data transform block 1 : Perform bit reversal on data output from data transform block Reset type: SYSRSn |
5 | BRIN | R/W | 0h | 0 : No bit reversal on data input of data transform block 1 : Perform bit reversal on data input of data transform block Reset type: SYSRSn |
4 | RESERVED | R | 0h | Reserved |
3-0 | MODE | R/W | 0h | 0 : BIT_BANG mode, The value written into DATA0 and DATA1 registers appear on the signal generator outputs as is. 1 : SHIFT_RIGHT_ONCE mode, The data value written into (DATA1,DATA0) registers are shifted right by 1 on every clock. Shifting operations stops when BITLENGTH shifts are done and SIGGEN0_CTL0.EN bit is cleared. 2 : ROTATE_RIGHT_ONCE, The data value written into (DATA1,DATA0) registers are rotated right by 1 on every clock. Rotation happens within (DATA1,DATA0)[BITLENGTH-1:0] Rotate operations stops when BITLENGTH shifts are done and SIGGEN0_CTL0.EN bit is cleared. 3 : ROTATE_RIGHT_REPEAT, The data value written into (DATA1,DATA0) registers are rotated right by 1 on every clock. Rotation happens within (DATA1,DATA0)[BITLENGTH-1:0] Rotate operations continue until SIGGEN0_CTL0.EN bit is cleared. 4 : SHIFT_LEFT_ONCE mode, The data value written into (DATA1,DATA0) registers are shifted left by 1 on every clock. Shifting operations stops when BITLENGTH shifts are done and SIGGEN0_CTL0.EN bit is cleared. 5 : ROTATE_LEFT_ONCE, The data value written into (DATA1,DATA0) registers are rotated left by 1 on every clock. Rotation happens within (DATA1,DATA0)[BITLENGTH-1:0] Rotate operations stops when BITLENGTH shifts are done and SIGGEN0_CTL0.EN bit is cleared. 6 : ROTATE_LEFT_REPEAT, The data value written into (DATA1,DATA0) registers are rotated left by 1 on every clock. Rotation happens within (DATA1,DATA0)[BITLENGTH-1:0] Rotate operations continue until SIGGEN0_CTL0.EN bit is cleared. 7 : SHIFT_RIGHT_REPEAT mode, The data value written into (DATA1,DATA0) registers are shifted right by 1 on every clock. Shifting operations stops when SIGGEN0_CTL0.EN bit is cleared. 8 : SHIFT_LEFT_REPEAT mode, The data value written into (DATA1,DATA0) registers are shifted left by 1 on every clock. Shifting operations stops when SIGGEN0_CTL0.EN bit is cleared. Reset type: SYSRSn |
SIGGEN0_CTL1 is shown in Figure 34-23 and described in Table 34-23.
Return to the Summary Table.
Signal generator 0's control register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA63_INSEL | RESERVED | ||||||||||||||
R/W-0h | R-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA0_INSEL | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | DATA63_INSEL | R/W | 0h | Source input of bit 63 of Data register. If 0 delects DATA_NEXT[63] else, selects one of the EPGIN inputs. This provides the ability to capture the data. 0x0 : DATA_NEXT[63] 0x1 : EPGIN0 0x2 : EPGIN1 0x3 : EPGIN2 0x4 : EPGIN3 0x5 : EPGIN4 0x6 : EPGIN5 0x7 : EPGIN6 0x8 : EPGIN7 0x9-0xF : 0 Reset type: SYSRSn |
27-4 | RESERVED | R | 0h | Reserved |
3-0 | DATA0_INSEL | R/W | 0h | Source input of bit 0 of Data register. If 0 delects DATA_NEXT[0] else, selects one of the EPGIN inputs. This provides the ability to capture the data. 0x0 : DATA_NEXT[0] 0x1 : EPGIN0 0x2 : EPGIN1 0x3 : EPGIN2 0x4 : EPGIN3 0x5 : EPGIN4 0x6 : EPGIN5 0x7 : EPGIN6 0x8 : EPGIN7 0x9-0xF : 0 Reset type: SYSRSn |
SIGGEN0_DATA0 is shown in Figure 34-24 and described in Table 34-24.
Return to the Summary Table.
Signal generator 0's data register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGGEN_DATA0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SIGGEN_DATA0 | R/W | 0h | Data used in signal bit stream. {SIGGEN_DATA1,SIGGEN_DATA0} together constitures a 64 bit data stream, which are modified as per the SIGGENx_CTL0.MODE configuration. Reset type: SYSRSn |
SIGGEN0_DATA1 is shown in Figure 34-25 and described in Table 34-25.
Return to the Summary Table.
Signal generator 0's data register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGGEN_DATA1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SIGGEN_DATA1 | R/W | 0h | Data used in signal bit stream. {SIGGEN_DATA1,SIGGEN_DATA0} together constitures a 64 bit data stream, which are modified as per the SIGGENx_CTL0.MODE configuration. Reset type: SYSRSn |
SIGGEN0_DATA0_ACTIVE is shown in Figure 34-26 and described in Table 34-26.
Return to the Summary Table.
Signal generator 0's data active register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGEN_DATA0 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SIGEN_DATA0 | R | 0h | This is the lower 32 bits of the 64 bit active register (used in data transformation) Reset type: SYSRSn |
SIGGEN0_DATA1_ACTIVE is shown in Figure 34-27 and described in Table 34-27.
Return to the Summary Table.
Signal generator 0's data active register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGGEN_DATA1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SIGGEN_DATA1 | R | 0h | This is the upper 32 bits of the 64 bit active register (used in data transformation) Reset type: SYSRSn |
REVISION is shown in Figure 34-28 and described in Table 34-28.
Return to the Summary Table.
IP Revision tie-off value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SCHEME | RESERVED | FUNC | |||||
R-1h | R-0-0h | R-1h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FUNC | |||||||
R-1h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAJOR | ||||||
R-1h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM | MINOR | ||||||
R-0h | R-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | This identifies the scheme revision ID register type implemented for this module Reset type: SYSRSn |
29-28 | RESERVED | R-0 | 0h | Reserved |
27-16 | FUNC | R | 1h | Functional Release Number Reflects software-compatability. If there is no software compatability, a unique func number is assigned for compatible modules, the same number is maintained. Reset type: SYSRSn |
15-11 | RESERVED | R | 1h | Reserved |
10-8 | MAJOR | R | 0h | Major Revision Number Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. Reset type: SYSRSn |
7-6 | CUSTOM | R | 0h | Custom Module Number Indicates a special version of the module. May not be supported by standard software. Reset type: SYSRSn |
5-0 | MINOR | R | 1h | Minor Revision Number Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. Reset type: SYSRSn |