SPRUIZ1B July   2023  – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit (FPU)
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 VCRC Unit
  5. 3 C28x System Control and Interrupts
    1. 3.1  C28x System Control Introduction
      1. 3.1.1 SYSCTL Related Collateral
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
    3. 3.3  Resets
      1. 3.3.1  Reset Sources
      2. 3.3.2  External Reset (XRS)
      3. 3.3.3  Simulate External Reset (SIMRESET.XRS)
      4. 3.3.4  Power-On Reset (POR)
      5. 3.3.5  Debugger Reset (SYSRS)
      6. 3.3.6  Simulate CPU1 Reset (SIMRESET)
      7. 3.3.7  Watchdog Reset (WDRS)
      8. 3.3.8  NMI Watchdog Reset (NMIWDRS)
      9. 3.3.9  Secure Code Copy Reset (SCCRESET)
      10. 3.3.10 EtherCAT SubDevice Controller (ESC) Module Reset Output
    4. 3.4  Peripheral Interrupts
      1. 3.4.1 Interrupt Concepts
      2. 3.4.2 Interrupt Architecture
        1. 3.4.2.1 Peripheral Stage
        2. 3.4.2.2 PIE Stage
        3. 3.4.2.3 CPU Stage
        4. 3.4.2.4 Dual-CPU Interrupt Handling
      3. 3.4.3 Interrupt Entry Sequence
      4. 3.4.4 Configuring and Using Interrupts
        1. 3.4.4.1 Enabling Interrupts
        2. 3.4.4.2 Handling Interrupts
        3. 3.4.4.3 Disabling Interrupts
        4. 3.4.4.4 Nesting Interrupts
      5. 3.4.5 PIE Channel Mapping
        1. 3.4.5.1 PIE Interrupt Priority
          1. 3.4.5.1.1 Channel Priority
          2. 3.4.5.1.2 Group Priority
      6. 3.4.6 System Error Interrupts
      7. 3.4.7 Vector Tables
    5. 3.5  Exceptions and Non-Maskable Interrupts
      1. 3.5.1 Configuring and Using NMIs
      2. 3.5.2 Emulation Considerations
      3. 3.5.3 NMI Sources
        1. 3.5.3.1 Missing Clock Detection
        2. 3.5.3.2 RAM Uncorrectable Error
        3. 3.5.3.3 Flash Uncorrectable ECC Error
        4. 3.5.3.4 ROM Uncorrectable Error
        5. 3.5.3.5 NMI Vector Fetch Mismatch
        6. 3.5.3.6 CPU2 Watchdog or NMI Watchdog Reset
        7. 3.5.3.7 EtherCAT Reset Out
        8. 3.5.3.8 CRC Fail
        9. 3.5.3.9 ERAD NMI
      4. 3.5.4 Illegal Instruction Trap (ITRAP)
    6. 3.6  Safety Features
      1. 3.6.1 Write Protection on Registers
        1. 3.6.1.1 LOCK Protection on System Configuration Registers
        2. 3.6.1.2 EALLOW Protection
      2. 3.6.2 CPU1 and CPU2 ePIE Vector Address Validity Check
      3. 3.6.3 NMIWDs
      4. 3.6.4 ECC and Parity Enabled RAMs, Shared RAMs Protection
      5. 3.6.5 ECC Enabled Flash Memory
      6. 3.6.6 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1 Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
        4. 3.7.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.7.2 Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
        3. 3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
        4. 3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
      3. 3.7.3 Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)
        6. 3.7.3.6 CAN Bit Clock
        7. 3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4 External Clock Output (XCLKOUT)
      5. 3.7.5 Clock Connectivity
      6. 3.7.6 Using an External Crystal or Resonator
        1. 3.7.6.1 X1/X2 Precondition Circuit
      7. 3.7.7 PLL/AUXPLL
        1. 3.7.7.1 System Clock Setup
        2. 3.7.7.2 USB Auxiliary Clock Setup
        3. 3.7.7.3 SYS PLL/AUX PLL Bypass
      8. 3.7.8 Clock (OSCCLK) Failure Detection
        1. 3.7.8.1 Missing Clock Detection Logic
    8. 3.8  Clock Configuration Semaphore
    9. 3.9  32-Bit CPU Timers 0/1/2
    10. 3.10 Watchdog Timers
      1. 3.10.1 Servicing the Watchdog Timer
      2. 3.10.2 Minimum Window Check
      3. 3.10.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.10.4 Watchdog Operation in Low-Power Modes
      5. 3.10.5 Emulation Considerations
    11. 3.11 Low-Power Modes
      1. 3.11.1 IDLE
      2. 3.11.2 STANDBY
      3. 3.11.3 HALT
    12. 3.12 Memory Controller Module
      1. 3.12.1  Dedicated RAM (Dx RAM)
      2. 3.12.2  Local Shared RAM (LSx RAM)
      3. 3.12.3  Global Shared RAM (GSx RAM)
      4. 3.12.4  CPU Message RAM (CPU MSG RAM)
      5. 3.12.5  CLA Message RAM (CLA MSGRAM)
      6. 3.12.6  CLA-DMA MSG RAM
      7. 3.12.7  Access Arbitration
      8. 3.12.8  Access Protection
        1. 3.12.8.1 CPU Fetch Protection
        2. 3.12.8.2 CPU Write Protection
        3. 3.12.8.3 CPU Read Protection
        4. 3.12.8.4 CLA Fetch Protection
        5. 3.12.8.5 CLA Write Protection
        6. 3.12.8.6 CLA Read Protection
        7. 3.12.8.7 DMA Write Protection
      9. 3.12.9  Memory Error Detection, Correction, and Error Handling
        1. 3.12.9.1 Error Detection and Correction
        2. 3.12.9.2 Error Handling
      10. 3.12.10 Application Test Hooks for Error Detection and Correction
      11. 3.12.11 ROM Test
      12. 3.12.12 RAM Initialization
    13. 3.13 JTAG
      1. 3.13.1 JTAG Noise and TAP_STATUS
    14. 3.14 Live Firmware Update (LFU)
      1. 3.14.1 LFU Background
      2. 3.14.2 LFU Switchover Steps
      3. 3.14.3 Device Features Supporting LFU
        1. 3.14.3.1 Multi-Bank Flash
        2. 3.14.3.2 PIE Vector Table Swap
        3. 3.14.3.3 LS0/LS1 RAM Memory Swap for CPU1
          1. 3.14.3.3.1 Applicability to CLA LFU
        4. 3.14.3.4 D2/D3 RAM Memory Swap for CPU2
        5. 3.14.3.5 Additional Points Pertaining to LS0/LS1 and D2/D3 RAM Memory Swap
      4. 3.14.4 LFU Switchover
      5. 3.14.5 LFU Resources
    15. 3.15 System Control Register Configuration Restrictions
    16. 3.16 MCU Configuration (MCUCNFx)
    17. 3.17 Software
      1. 3.17.1 SYSCTL Examples
        1. 3.17.1.1 Missing clock detection (MCD) - SINGLE_CORE
        2. 3.17.1.2 XCLKOUT (External Clock Output) Configuration - SINGLE_CORE
      2. 3.17.2 MEMCFG Examples
        1. 3.17.2.1 Correctable & Uncorrectable Memory Error Handling
        2. 3.17.2.2 Shared RAM Management (CPU1) - C28X_DUAL
        3. 3.17.2.3 Shared RAM Management (CPU2) - C28X_DUAL
      3. 3.17.3 NMI Examples
        1. 3.17.3.1 NMI handling - C28X_DUAL
        2. 3.17.3.2 Watchdog Reset - C28X_DUAL
      4. 3.17.4 TIMER Examples
        1. 3.17.4.1 CPU Timers - SINGLE_CORE
        2. 3.17.4.2 CPU Timers - SINGLE_CORE
      5. 3.17.5 WATCHDOG Examples
        1. 3.17.5.1 Watchdog - SINGLE_CORE
    18. 3.18 System Control Registers
      1. 3.18.1  SYSCTRL Base Address Table
      2. 3.18.2  LFU Base Address Table
      3. 3.18.3  CPUTIMER_REGS Registers
      4. 3.18.4  PIE_CTRL_REGS Registers
      5. 3.18.5  WD_REGS Registers
      6. 3.18.6  NMI_INTRUPT_REGS Registers
      7. 3.18.7  XINT_REGS Registers
      8. 3.18.8  SYNC_SOC_REGS Registers
      9. 3.18.9  CPU1_DMA_CLA_SRC_SEL_REGS Registers
      10. 3.18.10 CPU2_DMA_CLA_SRC_SEL_REGS Registers
      11. 3.18.11 DEV_CFG_REGS Registers
      12. 3.18.12 CLK_CFG_REGS Registers
      13. 3.18.13 CPU1_SYS_REGS Registers
      14. 3.18.14 CPU2_SYS_REGS Registers
      15. 3.18.15 CPU1_SYS_STATUS_REGS Registers
      16. 3.18.16 CPU2_SYS_STATUS_REGS Registers
      17. 3.18.17 CPU1_PERIPH_AC_REGS Registers
      18. 3.18.18 CPU2_PERIPH_AC_REGS Registers
      19. 3.18.19 MEM_CFG_REGS Registers
      20. 3.18.20 ACCESS_PROTECTION_REGS Registers
      21. 3.18.21 MEMORY_ERROR_REGS Registers
      22. 3.18.22 ROM_WAIT_STATE_REGS Registers
      23. 3.18.23 TEST_ERROR_REGS Registers
      24. 3.18.24 UID_REGS Registers
      25. 3.18.25 CPU1_LFU_REGS Registers
      26. 3.18.26 CPU2_LFU_REGS Registers
      27. 3.18.27 CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers
      28. 3.18.28 CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers
      29. 3.18.29 CPU2_DMA_CLA_SRC_SEL_REGS Registers
      30. 3.18.30 Register to Driverlib Function Mapping
        1. 3.18.30.1 ASYSCTL Registers to Driverlib Functions
        2. 3.18.30.2 CPUTIMER Registers to Driverlib Functions
        3. 3.18.30.3 MEMCFG Registers to Driverlib Functions
        4. 3.18.30.4 NMI Registers to Driverlib Functions
        5. 3.18.30.5 PIE Registers to Driverlib Functions
        6. 3.18.30.6 SYSCTL Registers to Driverlib Functions
        7. 3.18.30.7 WWD Registers to Driverlib Functions
        8. 3.18.30.8 XINT Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and MPOST Configuration
      2. 4.7.2  Booting CPU2
        1. 4.7.2.1 Boot Up Procedure
        2. 4.7.2.2 IPCBOOTMODE Details
        3. 4.7.2.3 Error IPC Command Table
      3. 4.7.3  Entry Points
      4. 4.7.4  Wait Points
      5. 4.7.5  Secure Flash Boot Mode
        1. 4.7.5.1 Secure Flash CPU1 Linker File Example
      6. 4.7.6  Memory Maps
        1. 4.7.6.1 Boot ROM Memory-Maps
        2. 4.7.6.2 Reserved RAM Memory-Maps
      7. 4.7.7  ROM Tables
      8. 4.7.8  Boot Modes and Loaders
        1. 4.7.8.1 Boot Modes
          1. 4.7.8.1.1 Flash Boot
          2. 4.7.8.1.2 RAM Boot
          3. 4.7.8.1.3 Wait Boot
          4. 4.7.8.1.4 Secure LFU Flash Boot
        2. 4.7.8.2 Bootloaders
          1. 4.7.8.2.1 SCI Boot Mode
          2. 4.7.8.2.2 SPI Boot Mode
          3. 4.7.8.2.3 I2C Boot Mode
          4. 4.7.8.2.4 Parallel Boot Mode
          5. 4.7.8.2.5 CAN Boot Mode
          6. 4.7.8.2.6 CAN-FD Boot Mode
          7. 4.7.8.2.7 USB Boot Mode
          8. 4.7.8.2.8 IPC Message Copy to RAM Boot
          9. 4.7.8.2.9 Firmware Update (FWU) Flash Boot
      9. 4.7.9  GPIO Assignments
      10. 4.7.10 Secure ROM Function APIs
      11. 4.7.11 Clock Initializations
      12. 4.7.12 Boot Status Information
        1. 4.7.12.1 Booting Status
        2. 4.7.12.2 Boot Mode and MPOST (Memory Power On Self-Test) Status
      13. 4.7.13 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
    9. 4.9 Software
      1. 4.9.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
      1. 5.6.1 RAMOPEN
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
        2. 5.8.1.2 DCSM Memory partitioning Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
      7. 5.9.7 DCSM Registers to Driverlib Functions
  8. 6 Background CRC-32 (BGCRC)
    1. 6.1 Introduction
      1. 6.1.1 BGCRC Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Block Diagram
      4. 6.1.4 Memory Wait States and Memory Map
    2. 6.2 Functional Description
      1. 6.2.1 Data Read Unit
      2. 6.2.2 CRC-32 Compute Unit
      3. 6.2.3 CRC Notification Unit
        1. 6.2.3.1 CPU Interrupt and NMI
      4. 6.2.4 Operating Modes
        1. 6.2.4.1 CRC Mode
        2. 6.2.4.2 Scrub Mode
      5. 6.2.5 BGCRC Watchdog
      6. 6.2.6 Hardware and Software Faults Protection
    3. 6.3 Application of the BGCRC
      1. 6.3.1 Software Configuration
      2. 6.3.2 Decision on Error Response Severity
      3. 6.3.3 Decision of Controller for CLA_CRC
      4. 6.3.4 Execution of Time Critical Code from Wait-Stated Memories
      5. 6.3.5 BGCRC Execution
      6. 6.3.6 Debug/Error Response for BGCRC Errors
      7. 6.3.7 BGCRC Golden CRC-32 Value Computation
    4. 6.4 Software
      1. 6.4.1 BGCRC Examples
        1. 6.4.1.1 BGCRC CPU Interrupt Example
        2. 6.4.1.2 BGCRC Example with Watchdog and Lock
        3. 6.4.1.3 CLA-BGCRC Example in CRC mode
        4. 6.4.1.4 CLA-BGCRC Example in Scrub Mode
    5. 6.5 BGCRC Registers
      1. 6.5.1 BGCRC Base Address Table
      2. 6.5.2 BGCRC_REGS Registers
      3. 6.5.3 BGCRC Registers to Driverlib Functions
  9. 7 Control Law Accelerator (CLA)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 CLA Related Collateral
      3. 7.1.3 Block Diagram
    2. 7.2 CLA Interface
      1. 7.2.1 CLA Memory
      2. 7.2.2 CLA Memory Bus
      3. 7.2.3 Shared Peripherals and EALLOW Protection
      4. 7.2.4 CLA Tasks and Interrupt Vectors
      5. 7.2.5 CLA Software Interrupt to CPU
    3. 7.3 CLA, DMA, and CPU Arbitration
      1. 7.3.1 CLA Message RAM
      2. 7.3.2 CLA Program Memory
      3. 7.3.3 CLA Data Memory
      4. 7.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 7.4 CLA Configuration and Debug
      1. 7.4.1 Building a CLA Application
      2. 7.4.2 Typical CLA Initialization Sequence
      3. 7.4.3 Debugging CLA Code
        1. 7.4.3.1 Software Breakpoint Support (MDEBUGSTOP1)
        2. 7.4.3.2 Legacy Breakpoint Support (MDEBUGSTOP)
      4. 7.4.4 CLA Illegal Opcode Behavior
      5. 7.4.5 Resetting the CLA
    5. 7.5 Pipeline
      1. 7.5.1 Pipeline Overview
      2. 7.5.2 CLA Pipeline Alignment
        1. 7.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       383
        3. 7.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       385
        5. 7.5.2.3 ADC Early Interrupt to CLA Response
      3. 7.5.3 Parallel Instructions
        1. 7.5.3.1 Math Operation with Parallel Load
        2. 7.5.3.2 Multiply with Parallel Add
      4. 7.5.4 CLA Task Execution Latency
    6. 7.6 Software
      1. 7.6.1 CLA Examples
        1. 7.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 7.6.1.2 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        3. 7.6.1.3 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
        4. 7.6.1.4 CLA background nesting task
        5. 7.6.1.5 Controlling PWM output using CLA
        6. 7.6.1.6 Just-in-time ADC sampling with CLA
        7. 7.6.1.7 Optimal offloading of control algorithms to CLA
        8. 7.6.1.8 Handling shared resources across C28x and CLA
    7. 7.7 Instruction Set
      1. 7.7.1 Instruction Descriptions
      2. 7.7.2 Addressing Modes and Encoding
      3. 7.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest [, CNDF]
        11.       MCCNDD 16BitDest [, CNDF]
        12.       MCLRC BGINTM
        13.       MCMP32 MRa, MRb
        14.       MCMPF32 MRa, MRb
        15.       MCMPF32 MRa, #16FHi
        16.       MDEBUGSTOP
        17.       MDEBUGSTOP1
        18.       MEALLOW
        19.       MEDIS
        20.       MEINVF32 MRa, MRb
        21.       MEISQRTF32 MRa, MRb
        22.       MF32TOI16 MRa, MRb
        23.       MF32TOI16R MRa, MRb
        24.       MF32TOI32 MRa, MRb
        25.       MF32TOUI16 MRa, MRb
        26.       MF32TOUI16R MRa, MRb
        27.       MF32TOUI32 MRa, MRb
        28.       MFRACF32 MRa, MRb
        29.       MI16TOF32 MRa, MRb
        30.       MI16TOF32 MRa, mem16
        31.       MI32TOF32 MRa, mem32
        32.       MI32TOF32 MRa, MRb
        33.       MLSL32 MRa, #SHIFT
        34.       MLSR32 MRa, #SHIFT
        35.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        36.       MMAXF32 MRa, MRb
        37.       MMAXF32 MRa, #16FHi
        38.       MMINF32 MRa, MRb
        39.       MMINF32 MRa, #16FHi
        40.       MMOV16 MARx, MRa, #16I
        41.       MMOV16 MARx, mem16
        42.       MMOV16 mem16, MARx
        43.       MMOV16 mem16, MRa
        44.       MMOV32 mem32, MRa
        45.       MMOV32 mem32, MSTF
        46.       MMOV32 MRa, mem32 [, CNDF]
        47.       MMOV32 MRa, MRb [, CNDF]
        48.       MMOV32 MSTF, mem32
        49.       MMOVD32 MRa, mem32
        50.       MMOVF32 MRa, #32F
        51.       MMOVI16 MARx, #16I
        52.       MMOVI32 MRa, #32FHex
        53.       MMOVIZ MRa, #16FHi
        54.       MMOVZ16 MRa, mem16
        55.       MMOVXI MRa, #16FLoHex
        56.       MMPYF32 MRa, MRb, MRc
        57.       MMPYF32 MRa, #16FHi, MRb
        58.       MMPYF32 MRa, MRb, #16FHi
        59.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        60.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        61.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        62.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        63.       MNEGF32 MRa, MRb[, CNDF]
        64.       MNOP
        65.       MOR32 MRa, MRb, MRc
        66.       MRCNDD [CNDF]
        67.       MSETC BGINTM
        68.       MSETFLG FLAG, VALUE
        69.       MSTOP
        70.       MSUB32 MRa, MRb, MRc
        71.       MSUBF32 MRa, MRb, MRc
        72.       MSUBF32 MRa, #16FHi, MRb
        73.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        74.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        75.       MSWAPF MRa, MRb [, CNDF]
        76.       MTESTTF CNDF
        77.       MUI16TOF32 MRa, mem16
        78.       MUI16TOF32 MRa, MRb
        79.       MUI32TOF32 MRa, mem32
        80.       MUI32TOF32 MRa, MRb
        81.       MXOR32 MRa, MRb, MRc
    8. 7.8 CLA Registers
      1. 7.8.1 CLA Base Address Table
      2. 7.8.2 CLA_ONLY_REGS Registers
      3. 7.8.3 CLA_SOFTINT_REGS Registers
      4. 7.8.4 CLA_REGS Registers
      5. 7.8.5 CLA Registers to Driverlib Functions
  10. 8 Configurable Logic Block (CLB)
    1. 8.1  Introduction
      1. 8.1.1 CLB Related Collateral
    2. 8.2  Description
      1. 8.2.1 CLB Clock
    3. 8.3  CLB Input/Output Connection
      1. 8.3.1 Overview
      2. 8.3.2 CLB Input Selection
      3. 8.3.3 CLB Output Selection
      4. 8.3.4 CLB Output Signal Multiplexer
    4. 8.4  CLB Tile
      1. 8.4.1 Static Switch Block
      2. 8.4.2 Counter Block
        1. 8.4.2.1 Counter Description
        2. 8.4.2.2 Counter Operation
        3. 8.4.2.3 Serializer Mode
        4. 8.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 8.4.3 FSM Block
      4. 8.4.4 LUT4 Block
      5. 8.4.5 Output LUT Block
      6. 8.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 8.4.7 High Level Controller (HLC)
        1. 8.4.7.1 High Level Controller Events
        2. 8.4.7.2 High Level Controller Instructions
        3. 8.4.7.3 <Src> and <Dest>
        4. 8.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 8.5  CPU Interface
      1. 8.5.1 Register Description
      2. 8.5.2 Non-Memory Mapped Registers
    6. 8.6  DMA Access
    7. 8.7  CLB Data Export Through SPI RX Buffer
    8. 8.8  CLB Pipeline Mode
    9. 8.9  Software
      1. 8.9.1 CLB Examples
        1. 8.9.1.1  CLB Empty Project
        2. 8.9.1.2  CLB Combinational Logic
        3. 8.9.1.3  CLB GPIO Input Filter
        4. 8.9.1.4  CLB Auxilary PWM
        5. 8.9.1.5  CLB PWM Protection
        6. 8.9.1.6  CLB Event Window
        7. 8.9.1.7  CLB Signal Generator
        8. 8.9.1.8  CLB State Machine
        9. 8.9.1.9  CLB External Signal AND Gate
        10. 8.9.1.10 CLB Timer
        11. 8.9.1.11 CLB Timer Two States
        12. 8.9.1.12 CLB Interrupt Tag
        13. 8.9.1.13 CLB Output Intersect
        14. 8.9.1.14 CLB PUSH PULL
        15. 8.9.1.15 CLB Multi Tile
        16. 8.9.1.16 CLB Tile to Tile Delay
        17. 8.9.1.17 CLB Glue Logic
        18. 8.9.1.18 CLB based One-shot PWM
        19. 8.9.1.19 CLB AOC Control
        20. 8.9.1.20 CLB AOC Release Control
        21. 8.9.1.21 CLB XBARs
        22. 8.9.1.22 CLB AOC Control
        23. 8.9.1.23 CLB Serializer
        24. 8.9.1.24 CLB LFSR
        25. 8.9.1.25 CLB Lock Output Mask
        26. 8.9.1.26 CLB INPUT Pipeline Mode
        27. 8.9.1.27 CLB Clocking and PIPELINE Mode
        28. 8.9.1.28 CLB SPI Data Export
        29. 8.9.1.29 CLB SPI Data Export DMA
        30. 8.9.1.30 CLB Trip Zone Timestamp
        31. 8.9.1.31 CLB CRC
        32. 8.9.1.32 CLB TDM Serial Port
        33. 8.9.1.33 CLB LED Driver
    10. 8.10 CLB Registers
      1. 8.10.1 CLB Base Address Table
      2. 8.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 8.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 8.10.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 8.10.5 CLB Registers to Driverlib Functions
  11. 9 Dual-Clock Comparator (DCC)
    1. 9.1 Introduction
      1. 9.1.1 Features
      2. 9.1.2 Block Diagram
    2. 9.2 Module Operation
      1. 9.2.1 Configuring DCC Counters
      2. 9.2.2 Single-Shot Measurement Mode
      3. 9.2.3 Continuous Monitoring Mode
      4. 9.2.4 Error Conditions
    3. 9.3 Interrupts
    4. 9.4 Software
      1. 9.4.1 DCC Examples
        1. 9.4.1.1 DCC Single shot Clock verification - SINGLE_CORE
        2. 9.4.1.2 DCC Single shot Clock measurement - SINGLE_CORE
        3. 9.4.1.3 DCC Continuous clock monitoring - SINGLE_CORE
    5. 9.5 DCC Registers
      1. 9.5.1 DCC Base Address Table
      2. 9.5.2 DCC_REGS Registers
      3. 9.5.3 DCC Registers to Driverlib Functions
  12. 10Direct Memory Access (DMA)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Architecture
      1. 10.2.1 Peripheral Interrupt Event Trigger Sources
      2. 10.2.2 DMA Bus
    3. 10.3 Address Pointer and Transfer Control
    4. 10.4 Pipeline Timing and Throughput
    5. 10.5 CPU and CLA Arbitration
    6. 10.6 Channel Priority
      1. 10.6.1 Round-Robin Mode
      2. 10.6.2 Channel 1 High-Priority Mode
    7. 10.7 Overrun Detection Feature
    8. 10.8 Software
      1. 10.8.1 DMA Examples
        1. 10.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 10.8.1.2 DMA Transfer Shared Peripheral - C28X_DUAL
        3. 10.8.1.3 DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
        4. 10.8.1.4 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 10.9 DMA Registers
      1. 10.9.1 DMA Base Address Table
      2. 10.9.2 DMA_REGS Registers
      3. 10.9.3 DMA_CH_REGS Registers
      4. 10.9.4 DMA_CLA_SRC_SEL_REGS Registers
      5. 10.9.5 DMA Registers to Driverlib Functions
  13. 11External Memory Interface (EMIF)
    1. 11.1 Introduction
      1. 11.1.1 Purpose of the Peripheral
      2. 11.1.2 EMIF Related Collateral
      3. 11.1.3 Features
        1. 11.1.3.1 Asynchronous Memory Support
        2. 11.1.3.2 Synchronous DRAM Memory Support
      4. 11.1.4 Functional Block Diagram
      5. 11.1.5 Configuring Device Pins
    2. 11.2 EMIF Module Architecture
      1. 11.2.1  EMIF Clock Control
      2. 11.2.2  EMIF Requests
      3. 11.2.3  EMIF Signal Descriptions
      4. 11.2.4  EMIF Signal Multiplexing Control
      5. 11.2.5  SDRAM Controller and Interface
        1. 11.2.5.1  SDRAM Commands
        2. 11.2.5.2  Interfacing to SDRAM
        3. 11.2.5.3  SDRAM Configuration Registers
        4. 11.2.5.4  SDRAM Auto-Initialization Sequence
        5. 11.2.5.5  SDRAM Configuration Procedure
        6. 11.2.5.6  EMIF Refresh Controller
          1. 11.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 11.2.5.7  Self-Refresh Mode
        8. 11.2.5.8  Power-Down Mode
        9. 11.2.5.9  SDRAM Read Operation
        10. 11.2.5.10 SDRAM Write Operations
        11. 11.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 11.2.6  Asynchronous Controller and Interface
        1. 11.2.6.1 Interfacing to Asynchronous Memory
        2. 11.2.6.2 Accessing Larger Asynchronous Memories
        3. 11.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 11.2.6.4 Read and Write Operations in Normal Mode
          1. 11.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 11.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 11.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 11.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 11.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 11.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 11.2.7  Data Bus Parking
      8. 11.2.8  Reset and Initialization Considerations
      9. 11.2.9  Interrupt Support
        1. 11.2.9.1 Interrupt Events
      10. 11.2.10 DMA Event Support
      11. 11.2.11 EMIF Signal Multiplexing
      12. 11.2.12 Memory Map
      13. 11.2.13 Priority and Arbitration
      14. 11.2.14 System Considerations
        1. 11.2.14.1 Asynchronous Request Times
      15. 11.2.15 Power Management
        1. 11.2.15.1 Power Management Using Self-Refresh Mode
        2. 11.2.15.2 Power Management Using Power Down Mode
      16. 11.2.16 Emulation Considerations
    3. 11.3 Example Configuration
      1. 11.3.1 Hardware Interface
      2. 11.3.2 Software Configuration
        1. 11.3.2.1 Configuring the SDRAM Interface
          1. 11.3.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 11.3.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 11.3.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 11.3.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 11.3.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 11.3.2.2 Configuring the Flash Interface
          1. 11.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    4. 11.4 Software
      1. 11.4.1 EMIF Examples
        1. 11.4.1.1 Pin setup for EMIF module accessing ASRAM.
        2. 11.4.1.2 EMIF1 ASYNC module accessing 16bit ASRAM.
        3. 11.4.1.3 EMIF1 module accessing 16bit ASRAM as code memory.
        4. 11.4.1.4 EMIF1 module accessing 16bit SDRAM using memcpy_fast_far().
        5. 11.4.1.5 EMIF1 module accessing 16bit SDRAM then puts into Self Refresh mode before entering Low Power Mode.
        6. 11.4.1.6 EMIF1 module accessing 32bit SDRAM using DMA.
        7. 11.4.1.7 EMIF1 module accessing 16bit SDRAM using alternate address mapping.
    5. 11.5 EMIF Registers
      1. 11.5.1 EMIF Base Address Table
      2. 11.5.2 EMIF_REGS Registers
      3. 11.5.3 EMIF1_CONFIG_REGS Registers
      4. 11.5.4 EMIF Registers to Driverlib Functions
  14. 12Flash Module
    1. 12.1  Introduction to Flash and OTP Memory
      1. 12.1.1 FLASH Related Collateral
      2. 12.1.2 Features
      3. 12.1.3 Flash Tools
      4. 12.1.4 Default Flash Configuration
    2. 12.2  Flash Bank, OTP, and Pump
    3. 12.3  Flash Wrapper
    4. 12.4  Flash and OTP Memory Performance
    5. 12.5  Flash Read Interface
      1. 12.5.1 C28x-Flash Read Interface
        1. 12.5.1.1 Standard Read Mode
        2. 12.5.1.2 Prefetch Mode
        3. 12.5.1.3 Data Cache
        4. 12.5.1.4 Flash Read Operation
    6. 12.6  Flash Erase and Program
      1. 12.6.1 Flash Controller Access Semaphore
      2. 12.6.2 Erase
      3. 12.6.3 Program
      4. 12.6.4 Verify
    7. 12.7  Error Correction Code (ECC) Protection
      1. 12.7.1 Single-Bit Data Error
      2. 12.7.2 Uncorrectable Error
      3. 12.7.3 Mechanism to Check the Correctness of ECC Logic
    8. 12.8  Reserved Locations Within Flash and OTP
    9. 12.9  Migrating an Application from RAM to Flash
    10. 12.10 Procedure to Change the Flash Control Registers
    11. 12.11 Software
      1. 12.11.1 FLASH Examples
        1. 12.11.1.1 Flash Programming with 512-bit AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
        2. 12.11.1.2 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
        3. 12.11.1.3 Flash Programming with 512-bit AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
        4. 12.11.1.4 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
    12. 12.12 Flash Registers
      1. 12.12.1 FLASH Base Address Table
      2. 12.12.2 FLASH_CTRL_REGS Registers
      3. 12.12.3 FLASH_ECC_REGS Registers
      4. 12.12.4 FLASH Registers to Driverlib Functions
  15. 13Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 13.1 Introduction
      1. 13.1.1 ERAD Related Collateral
    2. 13.2 Enhanced Bus Comparator Unit
      1. 13.2.1 Enhanced Bus Comparator Unit Operations
      2. 13.2.2 Event Masking and Exporting
    3. 13.3 System Event Counter Unit
      1. 13.3.1 System Event Counter Modes
        1. 13.3.1.1 Counting Active Levels Versus Edges
        2. 13.3.1.2 Max Mode
        3. 13.3.1.3 Cumulative Mode
        4. 13.3.1.4 Input Signal Selection
      2. 13.3.2 Reset on Event
      3. 13.3.3 Operation Conditions
    4. 13.4 ERAD Ownership, Initialization and Reset
    5. 13.5 ERAD Programming Sequence
      1. 13.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 13.5.2 Timer and Counter Programming Sequence
    6. 13.6 Cyclic Redundancy Check Unit
      1. 13.6.1 CRC Unit Qualifier
      2. 13.6.2 CRC Unit Programming Sequence
    7. 13.7 Program Counter Trace
      1. 13.7.1 Functional Block Diagram
      2. 13.7.2 Trace Qualification Modes
      3. 13.7.3 Trace Memory
      4. 13.7.4 Trace Input Signal Conditioning
      5. 13.7.5 PC Trace Software Operation
      6. 13.7.6 Trace Operation in Debug Mode
    8. 13.8 Software
      1. 13.8.1 ERAD Examples
        1. 13.8.1.1  ERAD Profiling Interrupts
        2. 13.8.1.2  ERAD Profile Function
        3. 13.8.1.3  ERAD Profile Function
        4. 13.8.1.4  ERAD HWBP Monitor Program Counter
        5. 13.8.1.5  ERAD HWBP Monitor Program Counter
        6. 13.8.1.6  ERAD Profile Function
        7. 13.8.1.7  ERAD HWBP Stack Overflow Detection
        8. 13.8.1.8  ERAD HWBP Stack Overflow Detection
        9. 13.8.1.9  ERAD Stack Overflow
        10. 13.8.1.10 ERAD Profile Interrupts CLA
        11. 13.8.1.11 ERAD Profiling Interrupts
        12. 13.8.1.12 ERAD Profiling Interrupts
        13. 13.8.1.13 ERAD MEMORY ACCESS RESTRICT
        14. 13.8.1.14 ERAD INTERRUPT ORDER
        15. 13.8.1.15 ERAD AND CLB
        16. 13.8.1.16 ERAD PWM PROTECTION
    9. 13.9 ERAD Registers
      1. 13.9.1 ERAD Base Address Table
      2. 13.9.2 ERAD_GLOBAL_REGS Registers
      3. 13.9.3 ERAD_HWBP_REGS Registers
      4. 13.9.4 ERAD_COUNTER_REGS Registers
      5. 13.9.5 ERAD_CRC_GLOBAL_REGS Registers
      6. 13.9.6 ERAD_CRC_REGS Registers
      7. 13.9.7 PCTRACE_REGS Registers
      8. 13.9.8 PCTRACE_BUFFER_REGS Registers
      9. 13.9.9 ERAD Registers to Driverlib Functions
  16. 14General-Purpose Input/Output (GPIO)
    1. 14.1  Introduction
      1. 14.1.1 GPIO Related Collateral
    2. 14.2  Configuration Overview
    3. 14.3  Digital Inputs on ADC Pins (AIOs)
    4. 14.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 14.5  Digital General-Purpose I/O Control
    6. 14.6  Input Qualification
      1. 14.6.1 No Synchronization (Asynchronous Input)
      2. 14.6.2 Synchronization to SYSCLKOUT Only
      3. 14.6.3 Qualification Using a Sampling Window
    7. 14.7  USB Signals
    8. 14.8  GPIO and Peripheral Muxing
      1. 14.8.1 GPIO Muxing
      2. 14.8.2 Peripheral Muxing
    9. 14.9  Internal Pullup Configuration Requirements
    10. 14.10 Software
      1. 14.10.1 GPIO Examples
        1. 14.10.1.1 Device GPIO Toggle - SINGLE_CORE
        2. 14.10.1.2 XINT/XBAR example - SINGLE_CORE
      2. 14.10.2 LED Examples
        1. 14.10.2.1 LED Blinky Example - MULTI_CORE
        2. 14.10.2.2 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
        3. 14.10.2.3 LED Blinky example - SINGLE_CORE
        4. 14.10.2.4 LED Blinky Example (CPU1|CPU2|CPU3) - MULTI_CORE
        5. 14.10.2.5 LED Blinky Example (CPU2) - MULTI_CORE
        6. 14.10.2.6 LED Blinky Example (CPU3) - MULTI_CORE
    11. 14.11 GPIO Registers
      1. 14.11.1 GPIO Base Address Table
      2. 14.11.2 GPIO_CTRL_REGS Registers
      3. 14.11.3 GPIO_DATA_REGS Registers
      4. 14.11.4 GPIO_DATA_READ_REGS Registers
      5. 14.11.5 GPIO Registers to Driverlib Functions
  17. 15Interprocessor Communication (IPC)
    1. 15.1 Introduction
    2. 15.2 Message RAMs
    3. 15.3 IPC Flags and Interrupts
    4. 15.4 IPC Command Registers
    5. 15.5 Free-Running Counter
    6. 15.6 IPC Communication Protocol
    7. 15.7 Software
      1. 15.7.1 IPC Examples
        1. 15.7.1.1 IPC basic message passing example with interrupt - MULTI_CORE
        2. 15.7.1.2 IPC basic message passing example with interrupt - MULTI_CORE
        3. 15.7.1.3 IPC basic message passing example with interrupt - MULTI_CORE
        4. 15.7.1.4 IPC basic message passing example with interrupt - MULTI_CORE
    8. 15.8 IPC Registers
      1. 15.8.1 IPC Base Address Table
      2. 15.8.2 CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers
      3. 15.8.3 CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers
      4. 15.8.4 IPC Registers to Driverlib Functions
  18. 16Crossbar (X-BAR)
    1. 16.1 Input X-BAR, ICL XBAR, MINDB XBAR, and CLB Input X-BAR
      1. 16.1.1 CLB Input X-BAR
      2. 16.1.2 ICL and MINDB X-BAR
    2. 16.2 ePWM , CLB, and GPIO Output X-BAR
      1. 16.2.1 ePWM X-BAR
        1. 16.2.1.1 ePWM X-BAR Architecture
      2. 16.2.2 CLB X-BAR
        1. 16.2.2.1 CLB X-BAR Architecture
      3. 16.2.3 GPIO Output X-BAR
        1. 16.2.3.1 GPIO Output X-BAR Architecture
      4. 16.2.4 CLB Output X-BAR
        1. 16.2.4.1 CLB Output X-BAR Architecture
      5. 16.2.5 X-BAR Flags
    3. 16.3 XBAR Registers
      1. 16.3.1  XBAR Base Address Table
      2. 16.3.2  EPWM_XBAR_REGS Registers
      3. 16.3.3  INPUT_XBAR_REGS Registers
      4. 16.3.4  XBAR_REGS Registers
      5. 16.3.5  MINDB_XBAR_REGS Registers
      6. 16.3.6  ICL_XBAR_REGS Registers
      7. 16.3.7  CLB_XBAR_REGS Registers
      8. 16.3.8  OUTPUT_XBAR_EXT64_REGS Registers
      9. 16.3.9  OUTPUT_XBAR_REGS Registers
      10. 16.3.10 Register to Driverlib Function Mapping
        1. 16.3.10.1 EPWMXBAR Registers to Driverlib Functions
        2. 16.3.10.2 INPUTXBAR Registers to Driverlib Functions
        3. 16.3.10.3 XBAR Registers to Driverlib Functions
        4. 16.3.10.4 MINDBXBAR Registers to Driverlib Functions
        5. 16.3.10.5 ICLXBAR Registers to Driverlib Functions
        6. 16.3.10.6 CLBXBAR Registers to Driverlib Functions
        7. 16.3.10.7 OUTPUTXBAR Registers to Driverlib Functions
  19. 17Analog Subsystem
    1. 17.1 Introduction
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
    2. 17.2 Optimizing Power-Up Time
    3. 17.3 Digital Inputs on ADC Pins (AIOs)
    4. 17.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 17.5 Analog Subsystem Registers
      1. 17.5.1 ASBSYS Base Address Table
      2. 17.5.2 ANALOG_SUBSYS_REGS Registers
  20. 18Analog-to-Digital Converter (ADC)
    1. 18.1  Introduction
      1. 18.1.1 ADC Related Collateral
      2. 18.1.2 Features
      3. 18.1.3 Block Diagram
    2. 18.2  ADC Configurability
      1. 18.2.1 Clock Configuration
      2. 18.2.2 Resolution
      3. 18.2.3 Voltage Reference
        1. 18.2.3.1 External Reference Mode
        2. 18.2.3.2 Internal Reference Mode
        3. 18.2.3.3 Ganged References
        4. 18.2.3.4 Selecting Reference Mode
      4. 18.2.4 Signal Mode
      5. 18.2.5 Expected Conversion Results
      6. 18.2.6 Interpreting Conversion Results
    3. 18.3  SOC Principle of Operation
      1. 18.3.1 SOC Configuration
      2. 18.3.2 Trigger Operation
        1. 18.3.2.1 Global Software Trigger
        2. 18.3.2.2 Trigger Repeaters
          1. 18.3.2.2.1 Oversampling Mode
          2. 18.3.2.2.2 Undersampling Mode
          3. 18.3.2.2.3 Trigger Phase Delay
          4. 18.3.2.2.4 Re-trigger Spread
          5. 18.3.2.2.5 Trigger Repeater Configuration
            1. 18.3.2.2.5.1 Register Shadow Updates
          6. 18.3.2.2.6 Re-Trigger Logic
          7. 18.3.2.2.7 Multi-Path Triggering Behavior
      3. 18.3.3 ADC Acquisition (Sample and Hold) Window
      4. 18.3.4 ADC Input Models
      5. 18.3.5 Channel Selection
        1. 18.3.5.1 External Channel Selection
          1. 18.3.5.1.1 External Channel Selection Timing
    4. 18.4  SOC Configuration Examples
      1. 18.4.1 Single Conversion from ePWM Trigger
      2. 18.4.2 Oversampled Conversion from ePWM Trigger
      3. 18.4.3 Multiple Conversions from CPU Timer Trigger
      4. 18.4.4 Software Triggering of SOCs
    5. 18.5  ADC Conversion Priority
    6. 18.6  Burst Mode
      1. 18.6.1 Burst Mode Example
      2. 18.6.2 Burst Mode Priority Example
    7. 18.7  EOC and Interrupt Operation
      1. 18.7.1 Interrupt Overflow
      2. 18.7.2 Continue to Interrupt Mode
      3. 18.7.3 Early Interrupt Configuration Mode
    8. 18.8  Post-Processing Blocks
      1. 18.8.1 PPB Offset Correction
      2. 18.8.2 PPB Error Calculation
      3. 18.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 18.8.4 PPB Sample Delay Capture
      5. 18.8.5 PPB Oversampling
        1. 18.8.5.1 Accumulation, Minimum, Maximum, and Average Functions
        2. 18.8.5.2 Outlier Rejection
    9. 18.9  Result Safety Checker
      1. 18.9.1 Result Safety Checker Operation
      2. 18.9.2 Result Safety Checker Interrupts and Events
    10. 18.10 Opens/Shorts Detection Circuit (OSDETECT)
      1. 18.10.1 Implementation
      2. 18.10.2 Detecting an Open Input Pin
      3. 18.10.3 Detecting a Shorted Input Pin
    11. 18.11 Power-Up Sequence
    12. 18.12 ADC Calibration
      1. 18.12.1 ADC Zero Offset Calibration
    13. 18.13 ADC Timings
      1. 18.13.1 ADC Timing Diagrams
      2. 18.13.2 Post-Processing Block Timings
    14. 18.14 Additional Information
      1. 18.14.1 Ensuring Synchronous Operation
        1. 18.14.1.1 Basic Synchronous Operation
        2. 18.14.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 18.14.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 18.14.1.4 Synchronous Operation with Different Resolutions
        5. 18.14.1.5 Non-overlapping Conversions
      2. 18.14.2 Choosing an Acquisition Window Duration
      3. 18.14.3 Achieving Simultaneous Sampling
      4. 18.14.4 Result Register Mapping
      5. 18.14.5 Internal Temperature Sensor
      6. 18.14.6 Designing an External Reference Circuit
      7. 18.14.7 ADC-DAC Loopback Testing
      8. 18.14.8 Internal Test Mode
      9. 18.14.9 ADC Gain and Offset Calibration
    15. 18.15 Software
      1. 18.15.1 ADC Examples
        1. 18.15.1.1  ADC Software Triggering - SINGLE_CORE
        2. 18.15.1.2  ADC ePWM Triggering - SINGLE_CORE
        3. 18.15.1.3  ADC Temperature Sensor Conversion - SINGLE_CORE
        4. 18.15.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync) - SINGLE_CORE
        5. 18.15.1.5  ADC Continuous Triggering (adc_soc_continuous) - SINGLE_CORE
        6. 18.15.1.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) - SINGLE_CORE
        7. 18.15.1.7  ADC PPB Offset (adc_ppb_offset) - SINGLE_CORE
        8. 18.15.1.8  ADC PPB Limits (adc_ppb_limits) - SINGLE_CORE
        9. 18.15.1.9  ADC PPB Delay Capture (adc_ppb_delay) - SINGLE_CORE
        10. 18.15.1.10 ADC ePWM Triggering Multiple SOC - SINGLE_CORE
        11. 18.15.1.11 ADC Burst Mode - SINGLE_CORE
        12. 18.15.1.12 ADC Burst Mode Oversampling - SINGLE_CORE
        13. 18.15.1.13 ADC SOC Oversampling - SINGLE_CORE
        14. 18.15.1.14 ADC PPB PWM trip (adc_ppb_pwm_trip) - SINGLE_CORE
        15. 18.15.1.15 ADC Trigger Repeater Oversampling - SINGLE_CORE
        16. 18.15.1.16 ADC Trigger Repeater Undersampling - SINGLE_CORE
        17. 18.15.1.17 ADC Safety Checker - SINGLE_CORE
    16. 18.16 ADC Registers
      1. 18.16.1 ADC Base Address Table
      2. 18.16.2 ADC_RESULT_REGS Registers
      3. 18.16.3 ADC_REGS Registers
      4. 18.16.4 ADC_SAFECHECK_INTEVT_REGS Registers
      5. 18.16.5 ADC_SAFECHECK_REGS Registers
      6. 18.16.6 ADC Registers to Driverlib Functions
  21. 19Buffered Digital-to-Analog Converter (DAC)
    1. 19.1 Introduction
      1. 19.1.1 DAC Related Collateral
      2. 19.1.2 Features
      3. 19.1.3 Block Diagram
    2. 19.2 Using the DAC
      1. 19.2.1 Initialization Sequence
      2. 19.2.2 DAC Offset Adjustment
      3. 19.2.3 EPWMSYNCPER Signal
    3. 19.3 Lock Registers
    4. 19.4 Software
      1. 19.4.1 DAC Examples
        1. 19.4.1.1 Buffered DAC Enable - SINGLE_CORE
        2. 19.4.1.2 Buffered DAC Random - SINGLE_CORE
    5. 19.5 DAC Registers
      1. 19.5.1 DAC Base Address Table
      2. 19.5.2 DAC_REGS Registers
      3. 19.5.3 DAC Registers to Driverlib Functions
  22. 20Comparator Subsystem (CMPSS)
    1. 20.1 Introduction
      1. 20.1.1 CMPSS Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Block Diagram
    2. 20.2 Comparator
    3. 20.3 Reference DAC
    4. 20.4 Ramp Generator
      1. 20.4.1 Ramp Generator Overview
      2. 20.4.2 Ramp Generator Behavior
      3. 20.4.3 Ramp Generator Behavior at Corner Cases
    5. 20.5 Digital Filter
      1. 20.5.1 Filter Initialization Sequence
    6. 20.6 Using the CMPSS
      1. 20.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 20.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 20.6.3 Calibrating the CMPSS
      4. 20.6.4 Enabling and Disabling the CMPSS Clock
    7. 20.7 Software
      1. 20.7.1 CMPSS Examples
        1. 20.7.1.1 CMPSS Asynchronous Trip - SINGLE_CORE
        2. 20.7.1.2 CMPSS Digital Filter Configuration - SINGLE_CORE
    8. 20.8 CMPSS Registers
      1. 20.8.1 CMPSS Base Address Table
      2. 20.8.2 CMPSS_REGS Registers
      3. 20.8.3 CMPSS Registers to Driverlib Functions
  23. 21Enhanced Capture (eCAP) and High Resolution Capture (HRCAP)
    1. 21.1  Introduction
      1. 21.1.1 Features
      2. 21.1.2 ECAP Related Collateral
    2. 21.2  Description
    3. 21.3  Configuring Device Pins for the eCAP
    4. 21.4  Capture and APWM Operating Mode
    5. 21.5  Capture Mode Description
      1. 21.5.1  Event Prescaler
      2. 21.5.2  Glitch Filter
      3. 21.5.3  Edge Polarity Select and Qualifier
      4. 21.5.4  Continuous/One-Shot Control
      5. 21.5.5  32-Bit Counter and Phase Control
      6. 21.5.6  CAP1-CAP4 Registers
      7. 21.5.7  eCAP Synchronization
        1. 21.5.7.1 Example 1 - Using SWSYNC with ECAP Module
      8. 21.5.8  Interrupt Control
      9. 21.5.9  DMA Interrupt
      10. 21.5.10 ADC SOC Event
      11. 21.5.11 Shadow Load and Lockout Control
      12. 21.5.12 APWM Mode Operation
      13. 21.5.13 Signal Monitoring Unit
        1. 21.5.13.1 Pulse Width and Period Monitoring
        2. 21.5.13.2 Edge Monitoring
    6. 21.6  Application of the eCAP Module
      1. 21.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 21.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 21.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 21.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 21.7  Application of the APWM Mode
      1. 21.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 21.8  High Resolution Capture (HRCAP) Module
      1. 21.8.1 Introduction
        1. 21.8.1.1 HRCAP Related Collateral
        2. 21.8.1.2 Features
        3. 21.8.1.3 Description
      2. 21.8.2 Operational Details
        1. 21.8.2.1 HRCAP Clocking
        2. 21.8.2.2 HRCAP Initialization Sequence
        3. 21.8.2.3 HRCAP Interrupts
        4. 21.8.2.4 HRCAP Calibration
          1. 21.8.2.4.1 Applying the Scale Factor
      3. 21.8.3 Known Exceptions
    9. 21.9  Software
      1. 21.9.1 ECAP Examples
        1. 21.9.1.1 eCAP APWM Example - SINGLE_CORE
        2. 21.9.1.2 eCAP Capture PWM Example - SINGLE_CORE
        3. 21.9.1.3 eCAP APWM Phase-shift Example - SINGLE_CORE
      2. 21.9.2 HRCAP Examples
        1. 21.9.2.1 HRCAP Capture and Calibration Example - SINGLE_CORE
    10. 21.10 eCAP Registers
      1. 21.10.1 ECAP Base Address Table
      2. 21.10.2 ECAP_REGS Registers
      3. 21.10.3 ECAP_SIGNAL_MONITORING Registers
      4. 21.10.4 ECAP Registers to Driverlib Functions
    11. 21.11 HRCAP Registers
      1. 21.11.1 HRCAP Base Address Table
      2. 21.11.2 HRCAP_REGS Registers
      3. 21.11.3 HRCAP Registers to Driverlib Functions
  24. 22Enhanced Pulse Width Modulator (ePWM)
    1. 22.1  Introduction
      1. 22.1.1 EPWM Related Collateral
      2. 22.1.2 Submodule Overview
    2. 22.2  Configuring Device Pins
    3. 22.3  ePWM Modules Overview
    4. 22.4  Time-Base (TB) Submodule
      1. 22.4.1 Purpose of the Time-Base Submodule
      2. 22.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 22.4.3 Calculating PWM Period and Frequency
        1. 22.4.3.1 Time-Base Period Shadow Register
        2. 22.4.3.2 Time-Base Clock Synchronization
        3. 22.4.3.3 Time-Base Counter Synchronization
        4. 22.4.3.4 ePWM SYNC Selection
      4. 22.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 22.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 22.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 22.4.7 Global Load
        1. 22.4.7.1 Global Load Pulse Pre-Scalar
        2. 22.4.7.2 One-Shot Load Mode
        3. 22.4.7.3 One-Shot Sync Mode
    5. 22.5  Counter-Compare (CC) Submodule
      1. 22.5.1 Purpose of the Counter-Compare Submodule
      2. 22.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 22.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 22.5.4 Count Mode Timing Waveforms
    6. 22.6  Action-Qualifier (AQ) Submodule
      1. 22.6.1 Purpose of the Action-Qualifier Submodule
      2. 22.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 22.6.3 Action-Qualifier Event Priority
      4. 22.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 22.6.5 Configuration Requirements for Common Waveforms
    7. 22.7  XCMP Complex Waveform Generator Mode
      1. 22.7.1 XCMP Allocation to CMPA and CMPB
      2. 22.7.2 XCMP Shadow Buffers
      3. 22.7.3 XCMP Operation
    8. 22.8  Dead-Band Generator (DB) Submodule
      1. 22.8.1 Purpose of the Dead-Band Submodule
      2. 22.8.2 Dead-band Submodule Additional Operating Modes
      3. 22.8.3 Operational Highlights for the Dead-Band Submodule
    9. 22.9  PWM Chopper (PC) Submodule
      1. 22.9.1 Purpose of the PWM Chopper Submodule
      2. 22.9.2 Operational Highlights for the PWM Chopper Submodule
      3. 22.9.3 Waveforms
        1. 22.9.3.1 One-Shot Pulse
        2. 22.9.3.2 Duty Cycle Control
    10. 22.10 Trip-Zone (TZ) Submodule
      1. 22.10.1 Purpose of the Trip-Zone Submodule
      2. 22.10.2 Operational Highlights for the Trip-Zone Submodule
        1. 22.10.2.1 Trip-Zone Configurations
      3. 22.10.3 Generating Trip Event Interrupts
    11. 22.11 Diode Emulation (DE) Submodule
      1. 22.11.1 DEACTIVE Mode
      2. 22.11.2 Exiting DE Mode
      3. 22.11.3 Re-Entering DE Mode
      4. 22.11.4 DE Monitor
    12. 22.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
      1. 22.12.1 Minimum Dead-Band (MINDB)
      2. 22.12.2 Illegal Combo Logic (ICL)
    13. 22.13 Event-Trigger (ET) Submodule
      1. 22.13.1 Operational Overview of the ePWM Event-Trigger Submodule
    14. 22.14 Digital Compare (DC) Submodule
      1. 22.14.1 Purpose of the Digital Compare Submodule
      2. 22.14.2 Enhanced Trip Action Using CMPSS
      3. 22.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 22.14.4 Operation Highlights of the Digital Compare Submodule
        1. 22.14.4.1 Digital Compare Events
        2. 22.14.4.2 Event Filtering
        3. 22.14.4.3 Valley Switching
        4. 22.14.4.4 Event Detection
          1. 22.14.4.4.1 Input Signal Detection
          2. 22.14.4.4.2 MIN and MAX Detection Circuit
    15. 22.15 ePWM Crossbar (X-BAR)
    16. 22.16 Applications to Power Topologies
      1. 22.16.1  Overview of Multiple Modules
      2. 22.16.2  Key Configuration Capabilities
      3. 22.16.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 22.16.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 22.16.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 22.16.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 22.16.7  Practical Applications Using Phase Control Between PWM Modules
      8. 22.16.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 22.16.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 22.16.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 22.16.11 Controlling H-Bridge LLC Resonant Converter
    17. 22.17 Register Lock Protection
    18. 22.18 High-Resolution Pulse Width Modulator (HRPWM)
      1. 22.18.1 Operational Description of HRPWM
        1. 22.18.1.1 Controlling the HRPWM Capabilities
        2. 22.18.1.2 HRPWM Source Clock
        3. 22.18.1.3 Configuring the HRPWM
        4. 22.18.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 22.18.1.5 Principle of Operation
          1. 22.18.1.5.1 Edge Positioning
          2. 22.18.1.5.2 Scaling Considerations
          3. 22.18.1.5.3 Duty Cycle Range Limitation
          4. 22.18.1.5.4 High-Resolution Period
            1. 22.18.1.5.4.1 High-Resolution Period Configuration
        6. 22.18.1.6 Deadband High-Resolution Operation
        7. 22.18.1.7 Scale Factor Optimizing Software (SFO)
        8. 22.18.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 22.18.1.8.1 #Defines for HRPWM Header Files
          2. 22.18.1.8.2 Implementing a Simple Buck Converter
            1. 22.18.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 22.18.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 22.18.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 22.18.1.8.3.1 PWM DAC Function Initialization Code
            2. 22.18.1.8.3.2 PWM DAC Function Run-Time Code
      2. 22.18.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 22.18.2.1 Scale Factor Optimizer Function - int SFO()
        2. 22.18.2.2 Software Usage
          1. 22.18.2.2.1 A Sample of How to Add "Include" Files
          2.        1198
          3. 22.18.2.2.2 Declaring an Element
          4.        1200
          5. 22.18.2.2.3 Initializing With a Scale Factor Value
          6.        1202
          7. 22.18.2.2.4 SFO Function Calls
    19. 22.19 Software
      1. 22.19.1 EPWM Examples
        1. 22.19.1.1  ePWM Trip Zone - SINGLE_CORE
        2. 22.19.1.2  ePWM Up Down Count Action Qualifier - SINGLE_CORE
        3. 22.19.1.3  ePWM Synchronization - SINGLE_CORE
        4. 22.19.1.4  ePWM Digital Compare - SINGLE_CORE
        5. 22.19.1.5  ePWM Digital Compare Event Filter Blanking Window - SINGLE_CORE
        6. 22.19.1.6  ePWM Valley Switching - SINGLE_CORE
        7. 22.19.1.7  ePWM Digital Compare Edge Filter - SINGLE_CORE
        8. 22.19.1.8  ePWM Deadband - SINGLE_CORE
        9. 22.19.1.9  ePWM DMA - SINGLE_CORE
        10. 22.19.1.10 ePWM Chopper - SINGLE_CORE
        11. 22.19.1.11 EPWM Configure Signal - SINGLE_CORE
        12. 22.19.1.12 Realization of Monoshot mode - SINGLE_CORE
        13. 22.19.1.13 EPWM Action Qualifier (epwm_up_aq) - SINGLE_CORE
        14. 22.19.1.14 ePWM XCMP Mode - SINGLE_CORE
        15. 22.19.1.15 ePWM Event Detection - SINGLE_CORE
      2. 22.19.2 HRPWM Examples
        1. 22.19.2.1 HRPWM Duty Control with SFO
        2. 22.19.2.2 HRPWM Slider
        3. 22.19.2.3 HRPWM Period Control
        4. 22.19.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 22.19.2.5 HRPWM Slider Test
        6. 22.19.2.6 HRPWM Duty Up Count
        7. 22.19.2.7 HRPWM Period Up-Down Count
    20. 22.20 ePWM Registers
      1. 22.20.1 EPWM Base Address Table
      2. 22.20.2 EPWM_REGS Registers
      3. 22.20.3 EPWM_XCMP_REGS Registers
      4. 22.20.4 DE_REGS Registers
      5. 22.20.5 MINDB_LUT_REGS Registers
      6. 22.20.6 HRPWMCAL_REGS Registers
      7. 22.20.7 Register to Driverlib Function Mapping
        1. 22.20.7.1 EPWM Registers to Driverlib Functions
        2. 22.20.7.2 HRPWM Registers to Driverlib Functions
        3. 22.20.7.3 HRPWMCAL Registers to Driverlib Functions
  25. 23Enhanced Quadrature Encoder Pulse (eQEP)
    1. 23.1  Introduction
      1. 23.1.1 EQEP Related Collateral
    2. 23.2  Configuring Device Pins
    3. 23.3  Description
      1. 23.3.1 EQEP Inputs
      2. 23.3.2 Functional Description
      3. 23.3.3 eQEP Memory Map
    4. 23.4  Quadrature Decoder Unit (QDU)
      1. 23.4.1 Position Counter Input Modes
        1. 23.4.1.1 Quadrature Count Mode
        2. 23.4.1.2 Direction-Count Mode
        3. 23.4.1.3 Up-Count Mode
        4. 23.4.1.4 Down-Count Mode
      2. 23.4.2 eQEP Input Polarity Selection
      3. 23.4.3 Position-Compare Sync Output
    5. 23.5  Position Counter and Control Unit (PCCU)
      1. 23.5.1 Position Counter Operating Modes
        1. 23.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 23.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 23.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 23.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 23.5.2 Position Counter Latch
        1. 23.5.2.1 Index Event Latch
        2. 23.5.2.2 Strobe Event Latch
      3. 23.5.3 Position Counter Initialization
      4. 23.5.4 eQEP Position-compare Unit
    6. 23.6  eQEP Edge Capture Unit
    7. 23.7  eQEP Watchdog
    8. 23.8  eQEP Unit Timer Base
    9. 23.9  QMA Module
      1. 23.9.1 Modes of Operation
        1. 23.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 23.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 23.9.2 Interrupt and Error Generation
    10. 23.10 eQEP Interrupt Structure
    11. 23.11 Software
      1. 23.11.1 EQEP Examples
        1. 23.11.1.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        2. 23.11.1.2 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
    12. 23.12 eQEP Registers
      1. 23.12.1 EQEP Base Address Table
      2. 23.12.2 EQEP_REGS Registers
      3. 23.12.3 EQEP Registers to Driverlib Functions
  26. 24Sigma Delta Filter Module (SDFM)
    1. 24.1  Introduction
      1. 24.1.1 SDFM Related Collateral
      2. 24.1.2 Features
      3. 24.1.3 Block Diagram
    2. 24.2  Configuring Device Pins
    3. 24.3  Input Qualification
    4. 24.4  Input Control Unit
    5. 24.5  SDFM Clock Control
    6. 24.6  Sinc Filter
      1. 24.6.1 Data Rate and Latency of the Sinc Filter
    7. 24.7  Data (Primary) Filter Unit
      1. 24.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 24.7.2 Data FIFO
      3. 24.7.3 SDSYNC Event
    8. 24.8  Comparator (Secondary) Filter Unit
      1. 24.8.1 Higher Threshold (HLT) Comparators
      2. 24.8.2 Lower Threshold (LLT) Comparators
      3. 24.8.3 Digital Filter
    9. 24.9  Theoretical SDFM Filter Output
    10. 24.10 Interrupt Unit
      1. 24.10.1 SDFM (SDyERR) Interrupt Sources
      2. 24.10.2 Data Ready (DRINT) Interrupt Sources
    11. 24.11 Software
      1. 24.11.1 SDFM Examples
        1. 24.11.1.1 SDFM Filter Sync CPU
        2. 24.11.1.2 SDFM Filter Sync CLA
        3. 24.11.1.3 SDFM Filter Sync DMA
        4. 24.11.1.4 SDFM PWM Sync
        5. 24.11.1.5 SDFM Type 1 Filter FIFO
        6. 24.11.1.6 SDFM Filter Sync CLA
    12. 24.12 SDFM Registers
      1. 24.12.1 SDFM Base Address Table
      2. 24.12.2 SDFM_REGS Registers
      3. 24.12.3 SDFM Registers to Driverlib Functions
  27. 25Controller Area Network (CAN)
    1. 25.1  Introduction
      1. 25.1.1 DCAN Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
        1. 25.1.3.1 CAN Core
        2. 25.1.3.2 Message Handler
        3. 25.1.3.3 Message RAM
        4. 25.1.3.4 Registers and Message Object Access (IFx)
    2. 25.2  Functional Description
      1. 25.2.1 Configuring Device Pins
      2. 25.2.2 Address/Data Bus Bridge
    3. 25.3  Operating Modes
      1. 25.3.1 Initialization
      2. 25.3.2 CAN Message Transfer (Normal Operation)
        1. 25.3.2.1 Disabled Automatic Retransmission
        2. 25.3.2.2 Auto-Bus-On
      3. 25.3.3 Test Modes
        1. 25.3.3.1 Silent Mode
        2. 25.3.3.2 Loopback Mode
        3. 25.3.3.3 External Loopback Mode
        4. 25.3.3.4 Loopback Combined with Silent Mode
    4. 25.4  Multiple Clock Source
    5. 25.5  Interrupt Functionality
      1. 25.5.1 Message Object Interrupts
      2. 25.5.2 Status Change Interrupts
      3. 25.5.3 Error Interrupts
      4. 25.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 25.5.5 Interrupt Topologies
    6. 25.6  DMA Functionality
    7. 25.7  Parity Check Mechanism
      1. 25.7.1 Behavior on Parity Error
    8. 25.8  Debug Mode
    9. 25.9  Module Initialization
    10. 25.10 Configuration of Message Objects
      1. 25.10.1 Configuration of a Transmit Object for Data Frames
      2. 25.10.2 Configuration of a Transmit Object for Remote Frames
      3. 25.10.3 Configuration of a Single Receive Object for Data Frames
      4. 25.10.4 Configuration of a Single Receive Object for Remote Frames
      5. 25.10.5 Configuration of a FIFO Buffer
    11. 25.11 Message Handling
      1. 25.11.1  Message Handler Overview
      2. 25.11.2  Receive/Transmit Priority
      3. 25.11.3  Transmission of Messages in Event Driven CAN Communication
      4. 25.11.4  Updating a Transmit Object
      5. 25.11.5  Changing a Transmit Object
      6. 25.11.6  Acceptance Filtering of Received Messages
      7. 25.11.7  Reception of Data Frames
      8. 25.11.8  Reception of Remote Frames
      9. 25.11.9  Reading Received Messages
      10. 25.11.10 Requesting New Data for a Receive Object
      11. 25.11.11 Storing Received Messages in FIFO Buffers
      12. 25.11.12 Reading from a FIFO Buffer
    12. 25.12 CAN Bit Timing
      1. 25.12.1 Bit Time and Bit Rate
        1. 25.12.1.1 Synchronization Segment
        2. 25.12.1.2 Propagation Time Segment
        3. 25.12.1.3 Phase Buffer Segments and Synchronization
        4. 25.12.1.4 Oscillator Tolerance Range
      2. 25.12.2 Configuration of the CAN Bit Timing
        1. 25.12.2.1 Calculation of the Bit Timing Parameters
        2. 25.12.2.2 Example for Bit Timing at High Baudrate
        3. 25.12.2.3 Example for Bit Timing at Low Baudrate
    13. 25.13 Message Interface Register Sets
      1. 25.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 25.13.2 Message Interface Register Set 3 (IF3)
    14. 25.14 Message RAM
      1. 25.14.1 Structure of Message Objects
      2. 25.14.2 Addressing Message Objects in RAM
      3. 25.14.3 Message RAM Representation in Debug Mode
    15. 25.15 Software
      1. 25.15.1 CAN Examples
        1. 25.15.1.1  CAN Dual Core Example - C28X_DUAL
        2. 25.15.1.2  CAN External Loopback
        3. 25.15.1.3  CAN External Loopback - C28X_DUAL
        4. 25.15.1.4  CAN External Loopback with Interrupts
        5. 25.15.1.5  CAN External Loopback with Interrupts - C28X_DUAL
        6. 25.15.1.6  CAN External Loopback with DMA
        7. 25.15.1.7  CAN Transmit and Receive Configurations
        8. 25.15.1.8  CAN Error Generation Example
        9. 25.15.1.9  CAN Remote Request Loopback
        10. 25.15.1.10 CAN example that illustrates the usage of Mask registers
    16. 25.16 CAN Registers
      1. 25.16.1 CAN Base Address Table
      2. 25.16.2 CAN_REGS Registers
      3. 25.16.3 CAN Registers to Driverlib Functions
  28. 26EtherCAT® SubordinateDevice Controller (ESC)
    1. 26.1 Introduction
      1. 26.1.1  ECAT Related Collateral
      2. 26.1.2  ESC Features
      3. 26.1.3  ESC Subsystem Integrated Features
      4. 26.1.4  F28P65x ESC versus Beckhoff ET1100
      5. 26.1.5  EtherCAT IP Block Diagram
      6. 26.1.6  ESC Functional Blocks
        1. 26.1.6.1  Interface to EtherCAT MainDevice
        2. 26.1.6.2  Process Data Interface
        3. 26.1.6.3  General-Purpose Inputs and Outputs
        4. 26.1.6.4  EtherCAT Processing Unit (EPU)
        5. 26.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 26.1.6.6  Sync Manager
        7. 26.1.6.7  Monitoring
        8. 26.1.6.8  Reset Controller
        9. 26.1.6.9  PHY Management
        10. 26.1.6.10 Distributed Clock (DC)
        11. 26.1.6.11 EEPROM
        12. 26.1.6.12 Status / LEDs
      7. 26.1.7  EtherCAT Physical Layer
        1. 26.1.7.1 MII Interface
        2. 26.1.7.2 PHY Management Interface
          1. 26.1.7.2.1 PHY Address Configuration
          2. 26.1.7.2.2 PHY Reset Signal
          3. 26.1.7.2.3 PHY Clock
      8. 26.1.8  EtherCAT Protocol
      9. 26.1.9  EtherCAT State Machine (ESM)
      10. 26.1.10 More Information on EtherCAT
      11. 26.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 26.2 ESC and ESCSS Description
      1. 26.2.1  ESC RAM Parity and Memory Address Maps
        1. 26.2.1.1 ESC RAM Parity Logic
        2. 26.2.1.2 CPU1 and CPU2 ESC Memory Address Map
      2. 26.2.2  Local Host Communication
        1. 26.2.2.1 Byte Accessibility Through PDI
        2. 26.2.2.2 Software Details for Operation Across Clock Domains
      3. 26.2.3  Debug Emulation Mode Operation
      4. 26.2.4  ESC SubSystem
        1. 26.2.4.1 CPU1 Bus Interface
        2. 26.2.4.2 CPU2 Bus Interface
      5. 26.2.5  Interrupts and Interrupt Mapping
      6. 26.2.6  Power, Clocks, and Resets
        1. 26.2.6.1 Power
        2. 26.2.6.2 Clocking
        3. 26.2.6.3 Resets
          1. 26.2.6.3.1 Chip-Level Reset
          2. 26.2.6.3.2 EtherCAT Soft Resets
          3. 26.2.6.3.3 Reset Out (RESET_OUT)
      7. 26.2.7  LED Controls
      8. 26.2.8  SubordinateDevice Node Configuration and EEPROM
      9. 26.2.9  General-Purpose Inputs and Outputs
        1. 26.2.9.1 General-Purpose Inputs
        2. 26.2.9.2 General-Purpose Output
      10. 26.2.10 Distributed Clocks – Sync and Latch
        1. 26.2.10.1 Clock Synchronization
        2. 26.2.10.2 SYNC Signals
          1. 26.2.10.2.1 Seeking Host Intervention
        3. 26.2.10.3 LATCH Signals
          1. 26.2.10.3.1 Timestamping
        4. 26.2.10.4 Device Control and Synchronization
          1. 26.2.10.4.1 Synchronization of PWM
          2. 26.2.10.4.2 ECAP SYNC Inputs
          3. 26.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 26.3 Software Initialization Sequence and Allocating Ownership
    4. 26.4 ESC Configuration Constants
    5. 26.5 EtherCAT IP Registers
      1. 26.5.1 ETHERCAT Base Address Table
      2. 26.5.2 ESCSS_REGS Registers
      3. 26.5.3 ESCSS_CONFIG_REGS Registers
      4. 26.5.4 ESC_SS Registers to Driverlib Functions
  29. 27Fast Serial Interface (FSI)
    1. 27.1 Introduction
      1. 27.1.1 FSI Related Collateral
      2. 27.1.2 FSI Features
    2. 27.2 System-level Integration
      1. 27.2.1 CPU Interface
      2. 27.2.2 Signal Description
        1. 27.2.2.1 Configuring Device Pins
      3. 27.2.3 FSI Interrupts
        1. 27.2.3.1 Transmitter Interrupts
        2. 27.2.3.2 Receiver Interrupts
        3. 27.2.3.3 Configuring Interrupts
        4. 27.2.3.4 Handling Interrupts
      4. 27.2.4 CLA Task Triggering
      5. 27.2.5 DMA Interface
      6. 27.2.6 External Frame Trigger Mux
    3. 27.3 FSI Functional Description
      1. 27.3.1  Introduction to Operation
      2. 27.3.2  FSI Transmitter Module
        1. 27.3.2.1 Initialization
        2. 27.3.2.2 FSI_TX Clocking
        3. 27.3.2.3 Transmitting Frames
          1. 27.3.2.3.1 Software Triggered Frames
          2. 27.3.2.3.2 Externally Triggered Frames
          3. 27.3.2.3.3 Ping Frame Generation
            1. 27.3.2.3.3.1 Automatic Ping Frames
            2. 27.3.2.3.3.2 Software Triggered Ping Frame
            3. 27.3.2.3.3.3 Externally Triggered Ping Frame
          4. 27.3.2.3.4 Transmitting Frames with DMA
        4. 27.3.2.4 Transmit Buffer Management
        5. 27.3.2.5 CRC Submodule
        6. 27.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 27.3.2.7 Reset
      3. 27.3.3  FSI Receiver Module
        1. 27.3.3.1  Initialization
        2. 27.3.3.2  FSI_RX Clocking
        3. 27.3.3.3  Receiving Frames
          1. 27.3.3.3.1 Receiving Frames with DMA
        4. 27.3.3.4  Ping Frame Watchdog
        5. 27.3.3.5  Frame Watchdog
        6. 27.3.3.6  Delay Line Control
        7. 27.3.3.7  Buffer Management
        8. 27.3.3.8  CRC Submodule
        9. 27.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 27.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 27.3.3.11 FSI_RX Reset
      4. 27.3.4  Frame Format
        1. 27.3.4.1 FSI Frame Phases
        2. 27.3.4.2 Frame Types
          1. 27.3.4.2.1 Ping Frames
          2. 27.3.4.2.2 Error Frames
          3. 27.3.4.2.3 Data Frames
        3. 27.3.4.3 Multi-Lane Transmission
      5. 27.3.5  Flush Sequence
      6. 27.3.6  Internal Loopback
      7. 27.3.7  CRC Generation
      8. 27.3.8  ECC Module
      9. 27.3.9  Tag Matching
      10. 27.3.10 User Data Filtering (UDATA Matching)
      11. 27.3.11 TDM Configurations
      12. 27.3.12 FSI Trigger Generation
      13. 27.3.13 FSI-SPI Compatibility Mode
        1. 27.3.13.1 Available SPI Modes
          1. 27.3.13.1.1 FSITX as SPI Controller, Transmit Only
            1. 27.3.13.1.1.1 Initialization
            2. 27.3.13.1.1.2 Operation
          2. 27.3.13.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 27.3.13.1.2.1 Initialization
            2. 27.3.13.1.2.2 Operation
          3. 27.3.13.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 27.3.13.1.3.1 Initialization
            2. 27.3.13.1.3.2 Operation
    4. 27.4 FSI Programing Guide
      1. 27.4.1 Establishing the Communication Link
        1. 27.4.1.1 Establishing the Communication Link from the Main Device
        2. 27.4.1.2 Establishing the Communication Link from the Remote Device
      2. 27.4.2 Register Protection
      3. 27.4.3 Emulation Mode
    5. 27.5 Software
      1. 27.5.1 FSI Examples
        1. 27.5.1.1 FSI Loopback:CPU Control - SINGLE_CORE
        2. 27.5.1.2 FSI data transfers upon CPU Timer event - SINGLE_CORE
    6. 27.6 FSI Registers
      1. 27.6.1 FSI Base Address Table
      2. 27.6.2 FSI_TX_REGS Registers
      3. 27.6.3 FSI_RX_REGS Registers
      4. 27.6.4 FSI Registers to Driverlib Functions
  30. 28Inter-Integrated Circuit Module (I2C)
    1. 28.1 Introduction
      1. 28.1.1 I2C Related Collateral
      2. 28.1.2 Features
      3. 28.1.3 Features Not Supported
      4. 28.1.4 Functional Overview
      5. 28.1.5 Clock Generation
      6. 28.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 28.1.6.1 Formula for the Controller Clock Period
    2. 28.2 Configuring Device Pins
    3. 28.3 I2C Module Operational Details
      1. 28.3.1  Input and Output Voltage Levels
      2. 28.3.2  Selecting Pullup Resistors
      3. 28.3.3  Data Validity
      4. 28.3.4  Operating Modes
      5. 28.3.5  I2C Module START and STOP Conditions
      6. 28.3.6  Non-repeat Mode versus Repeat Mode
      7. 28.3.7  Serial Data Formats
        1. 28.3.7.1 7-Bit Addressing Format
        2. 28.3.7.2 10-Bit Addressing Format
        3. 28.3.7.3 Free Data Format
        4. 28.3.7.4 Using a Repeated START Condition
      8. 28.3.8  Clock Synchronization
      9. 28.3.9  Arbitration
      10. 28.3.10 Digital Loopback Mode
      11. 28.3.11 NACK Bit Generation
    4. 28.4 Interrupt Requests Generated by the I2C Module
      1. 28.4.1 Basic I2C Interrupt Requests
      2. 28.4.2 I2C FIFO Interrupts
    5. 28.5 Resetting or Disabling the I2C Module
    6. 28.6 Software
      1. 28.6.1 I2C Examples
        1. 28.6.1.1 I2C Digital Loopback with FIFO Interrupts - SINGLE_CORE
        2. 28.6.1.2 I2C EEPROM - SINGLE_CORE
        3. 28.6.1.3 I2C Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        4. 28.6.1.4 I2C Extended Clock Stretching Controller TX - SINGLE_CORE
        5. 28.6.1.5 I2C Extended Clock Stretching Target RX - SINGLE_CORE
    7. 28.7 I2C Registers
      1. 28.7.1 I2C Base Address Table
      2. 28.7.2 I2C_REGS Registers
      3. 28.7.3 I2C Registers to Driverlib Functions
  31. 29Power Management Bus Module (PMBus)
    1. 29.1 Introduction
      1. 29.1.1 PMBUS Related Collateral
      2. 29.1.2 Features
      3. 29.1.3 Block Diagram
    2. 29.2 Configuring Device Pins
    3. 29.3 Target Mode Operation
      1. 29.3.1 Configuration
      2. 29.3.2 Message Handling
        1. 29.3.2.1  Quick Command
        2. 29.3.2.2  Send Byte
        3. 29.3.2.3  Receive Byte
        4. 29.3.2.4  Write Byte and Write Word
        5. 29.3.2.5  Read Byte and Read Word
        6. 29.3.2.6  Process Call
        7. 29.3.2.7  Block Write
        8. 29.3.2.8  Block Read
        9. 29.3.2.9  Block Write-Block Read Process Call
        10. 29.3.2.10 Alert Response
        11. 29.3.2.11 Extended Command
        12. 29.3.2.12 Group Command
    4. 29.4 Controller Mode Operation
      1. 29.4.1 Configuration
      2. 29.4.2 Message Handling
        1. 29.4.2.1  Quick Command
        2. 29.4.2.2  Send Byte
        3. 29.4.2.3  Receive Byte
        4. 29.4.2.4  Write Byte and Write Word
        5. 29.4.2.5  Read Byte and Read Word
        6. 29.4.2.6  Process Call
        7. 29.4.2.7  Block Write
        8. 29.4.2.8  Block Read
        9. 29.4.2.9  Block Write-Block Read Process Call
        10. 29.4.2.10 Alert Response
        11. 29.4.2.11 Extended Command
        12. 29.4.2.12 Group Command
    5. 29.5 PMBUS Registers
      1. 29.5.1 PMBUS Base Address Table
      2. 29.5.2 PMBUS_REGS Registers
      3. 29.5.3 PMBUS Registers to Driverlib Functions
  32. 30Serial Communications Interface (SCI)
    1. 30.1  Introduction
      1. 30.1.1 Features
      2. 30.1.2 SCI Related Collateral
      3. 30.1.3 Block Diagram
    2. 30.2  Architecture
    3. 30.3  SCI Module Signal Summary
    4. 30.4  Configuring Device Pins
    5. 30.5  Multiprocessor and Asynchronous Communication Modes
    6. 30.6  SCI Programmable Data Format
    7. 30.7  SCI Multiprocessor Communication
      1. 30.7.1 Recognizing the Address Byte
      2. 30.7.2 Controlling the SCI TX and RX Features
      3. 30.7.3 Receipt Sequence
    8. 30.8  Idle-Line Multiprocessor Mode
      1. 30.8.1 Idle-Line Mode Steps
      2. 30.8.2 Block Start Signal
      3. 30.8.3 Wake-Up Temporary (WUT) Flag
        1. 30.8.3.1 Sending a Block Start Signal
      4. 30.8.4 Receiver Operation
    9. 30.9  Address-Bit Multiprocessor Mode
      1. 30.9.1 Sending an Address
    10. 30.10 SCI Communication Format
      1. 30.10.1 Receiver Signals in Communication Modes
      2. 30.10.2 Transmitter Signals in Communication Modes
    11. 30.11 SCI Port Interrupts
      1. 30.11.1 Break Detect
    12. 30.12 SCI Baud Rate Calculations
    13. 30.13 SCI Enhanced Features
      1. 30.13.1 SCI FIFO Description
      2. 30.13.2 SCI Auto-Baud
      3. 30.13.3 Autobaud-Detect Sequence
    14. 30.14 Software
      1. 30.14.1 SCI Examples
        1. 30.14.1.1 Tune Baud Rate via UART Example
        2. 30.14.1.2 SCI FIFO Digital Loop Back
        3. 30.14.1.3 SCI Digital Loop Back with Interrupts
        4. 30.14.1.4 SCI Echoback
        5. 30.14.1.5 stdout redirect example
    15. 30.15 SCI Registers
      1. 30.15.1 SCI Base Address Table
      2. 30.15.2 SCI_REGS Registers
      3. 30.15.3 SCI Registers to Driverlib Functions
  33. 31Serial Peripheral Interface (SPI)
    1. 31.1 Introduction
      1. 31.1.1 Features
      2. 31.1.2 SPI Related Collateral
      3. 31.1.3 Block Diagram
    2. 31.2 System-Level Integration
      1. 31.2.1 SPI Module Signals
      2. 31.2.2 Configuring Device Pins
        1. 31.2.2.1 GPIOs Required for High-Speed Mode
      3. 31.2.3 SPI Interrupts
      4. 31.2.4 DMA Support
    3. 31.3 SPI Operation
      1. 31.3.1  Introduction to Operation
      2. 31.3.2  Controller Mode
      3. 31.3.3  Peripheral Mode
      4. 31.3.4  Data Format
        1. 31.3.4.1 Transmission of Bit from SPIRXBUF
      5. 31.3.5  Baud Rate Selection
        1. 31.3.5.1 Baud Rate Determination
        2. 31.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 31.3.6  SPI Clocking Schemes
      7. 31.3.7  SPI FIFO Description
      8. 31.3.8  SPI DMA Transfers
        1. 31.3.8.1 Transmitting Data Using SPI with DMA
        2. 31.3.8.2 Receiving Data Using SPI with DMA
      9. 31.3.9  SPI High-Speed Mode
      10. 31.3.10 SPI 3-Wire Mode Description
    4. 31.4 Programming Procedure
      1. 31.4.1 Initialization Upon Reset
      2. 31.4.2 Configuring the SPI
      3. 31.4.3 Configuring the SPI for High-Speed Mode
      4. 31.4.4 Data Transfer Example
      5. 31.4.5 SPI 3-Wire Mode Code Examples
        1. 31.4.5.1 3-Wire Controller Mode Transmit
        2.       1721
          1. 31.4.5.2.1 3-Wire Controller Mode Receive
        3.       1723
          1. 31.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1725
          1. 31.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 31.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 31.5 Software
      1. 31.5.1 SPI Examples
        1. 31.5.1.1 SPI Digital Loopback - SINGLE_CORE
        2. 31.5.1.2 SPI Digital Loopback with FIFO Interrupts - SINGLE_CORE
        3. 31.5.1.3 SPI Digital External Loopback without FIFO Interrupts - SINGLE_CORE
        4. 31.5.1.4 SPI Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        5. 31.5.1.5 SPI Digital Loopback with DMA - SINGLE_CORE
    6. 31.6 SPI Registers
      1. 31.6.1 SPI Base Address Table
      2. 31.6.2 SPI_REGS Registers
      3. 31.6.3 SPI Registers to Driverlib Functions
  34. 32Universal Serial Bus (USB) Controller
    1. 32.1 Introduction
      1. 32.1.1 Features
      2. 32.1.2 USB Related Collateral
      3. 32.1.3 Block Diagram
        1. 32.1.3.1 Signal Description
        2. 32.1.3.2 VBus Recommendations
    2. 32.2 Functional Description
      1. 32.2.1 Operation as a Device
        1. 32.2.1.1 Control and Configurable Endpoints
          1. 32.2.1.1.1 IN Transactions as a Device
          2. 32.2.1.1.2 Out Transactions as a Device
          3. 32.2.1.1.3 Scheduling
          4. 32.2.1.1.4 Additional Actions
          5. 32.2.1.1.5 Device Mode Suspend
          6. 32.2.1.1.6 Start of Frame
          7. 32.2.1.1.7 USB Reset
          8. 32.2.1.1.8 Connect/Disconnect
      2. 32.2.2 Operation as a Host
        1. 32.2.2.1 Endpoint Registers
        2. 32.2.2.2 IN Transactions as a Host
        3. 32.2.2.3 OUT Transactions as a Host
        4. 32.2.2.4 Transaction Scheduling
        5. 32.2.2.5 USB Hubs
        6. 32.2.2.6 Babble
        7. 32.2.2.7 Host SUSPEND
        8. 32.2.2.8 USB RESET
        9. 32.2.2.9 Connect/Disconnect
      3. 32.2.3 DMA Operation
      4. 32.2.4 Address/Data Bus Bridge
    3. 32.3 Initialization and Configuration
      1. 32.3.1 Pin Configuration
      2. 32.3.2 Endpoint Configuration
    4. 32.4 USB Global Interrupts
    5. 32.5 Software
      1. 32.5.1 USB Examples
        1. 32.5.1.1  USB CDC serial example
        2. 32.5.1.2  USB HID Mouse Device
        3. 32.5.1.3  USB Device Keyboard
        4. 32.5.1.4  USB Generic Bulk Device
        5. 32.5.1.5  USB HID Mouse Host
        6. 32.5.1.6  USB HID Keyboard Host
        7. 32.5.1.7  USB Mass Storage Class Host
        8. 32.5.1.8  USB Dual Detect
        9. 32.5.1.9  USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk)
        10. 32.5.1.10 USB HUB Host example
    6. 32.6 USB Registers
      1. 32.6.1 USB Base Address Table
      2. 32.6.2 USB_REGS Registers
      3. 32.6.3 USB Registers to Driverlib Functions
  35. 33Advanced Encryption Standard (AES) Accelerator
    1. 33.1 Introduction
      1. 33.1.1 AES Block Diagram
        1. 33.1.1.1 Interfaces
        2. 33.1.1.2 AES Subsystem
        3. 33.1.1.3 AES Wide-Bus Engine
      2. 33.1.2 AES Algorithm
    2. 33.2 AES Operating Modes
      1. 33.2.1  GCM Operation
      2. 33.2.2  CCM Operation
      3. 33.2.3  XTS Operation
      4. 33.2.4  ECB Feedback Mode
      5. 33.2.5  CBC Feedback Mode
      6. 33.2.6  CTR and ICM Feedback Modes
      7. 33.2.7  CFB Mode
      8. 33.2.8  F8 Mode
      9. 33.2.9  F9 Operation
      10. 33.2.10 CBC-MAC Operation
    3. 33.3 Extended and Combined Modes of Operations
      1. 33.3.1 GCM Protocol Operation
      2. 33.3.2 CCM Protocol Operation
      3. 33.3.3 Hardware Requests
    4. 33.4 AES Module Programming Guide
      1. 33.4.1 AES Low-Level Programming Models
        1. 33.4.1.1 Global Initialization
        2. 33.4.1.2 AES Operating Modes Configuration
        3. 33.4.1.3 AES Mode Configurations
        4. 33.4.1.4 AES Events Servicing
    5. 33.5 Software
      1. 33.5.1 AES Examples
        1. 33.5.1.1 AES ECB Encryption Example
        2. 33.5.1.2 AES ECB De-cryption Example
        3. 33.5.1.3 AES GCM Encryption Example
        4. 33.5.1.4 AES GCM Decryption Example
    6. 33.6 AES Registers
      1. 33.6.1 AES Base Address Table
      2. 33.6.2 AES_REGS Registers
      3. 33.6.3 AES_SS_REGS Registers
      4. 33.6.4 Register to Driverlib Function Mapping
        1. 33.6.4.1 AES Registers to Driverlib Functions
        2. 33.6.4.2 AES_SS Registers to Driverlib Functions
  36. 34Embedded Pattern Generator (EPG)
    1. 34.1 Introduction
      1. 34.1.1 Features
      2. 34.1.2 EPG Block Diagram
      3. 34.1.3 EPG Related Collateral
    2. 34.2 Clock Generator Modules
      1. 34.2.1 DCLK (50% duty cycle clock)
      2. 34.2.2 Clock Stop
    3. 34.3 Signal Generator Module
    4. 34.4 EPG Peripheral Signal Mux Selection
    5. 34.5 Application Software Notes
    6. 34.6 EPG Example Use Cases
      1. 34.6.1 EPG Example: Synchronous Clocks with Offset
        1. 34.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 34.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 34.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 34.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 34.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
      4. 34.6.4 EPG Example: Clock and Data Pair
        1. 34.6.4.1 Clock and Data Pair Register Configuration
      5. 34.6.5 EPG Example: Clock and Skewed Data Pair
        1. 34.6.5.1 Clock and Skewed Data Pair Register Configuration
      6. 34.6.6 EPG Example: Capturing Serial Data with a Known Baud Rate
        1. 34.6.6.1 Capturing Serial Data with a Known Baud Rate Register Configuration
    7. 34.7 EPG Interrupt
    8. 34.8 Software
      1. 34.8.1 EPG Examples
        1. 34.8.1.1 EPG Generating Synchronous Clocks - SINGLE_CORE
        2. 34.8.1.2 EPG Generating Two Offset Clocks - SINGLE_CORE
        3. 34.8.1.3 EPG Generating Two Offset Clocks With SIGGEN - SINGLE_CORE
        4. 34.8.1.4 EPG Generate Serial Data - SINGLE_CORE
        5. 34.8.1.5 EPG Generate Serial Data Shift Mode - SINGLE_CORE
    9. 34.9 EPG Registers
      1. 34.9.1 EPG Base Address Table
      2. 34.9.2 EPG_REGS Registers
      3. 34.9.3 EPG_MUX_REGS Registers
      4. 34.9.4 EPG Registers to Driverlib Functions
  37. 35Modular Controller Area Network (MCAN)
    1. 35.1 MCAN Introduction
      1. 35.1.1 MCAN Related Collateral
      2. 35.1.2 MCAN Features
    2. 35.2 MCAN Environment
    3. 35.3 CAN Network Basics
    4. 35.4 MCAN Integration
    5. 35.5 MCAN Functional Description
      1. 35.5.1  Module Clocking Requirements
      2. 35.5.2  Interrupt Requests
      3. 35.5.3  Operating Modes
        1. 35.5.3.1 Software Initialization
        2. 35.5.3.2 Normal Operation
        3. 35.5.3.3 CAN FD Operation
      4. 35.5.4  Transmitter Delay Compensation
        1. 35.5.4.1 Description
        2. 35.5.4.2 Transmitter Delay Compensation Measurement
      5. 35.5.5  Restricted Operation Mode
      6. 35.5.6  Bus Monitoring Mode
      7. 35.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 35.5.7.1 Frame Transmission in DAR Mode
      8. 35.5.8  Clock Stop Mode
        1. 35.5.8.1 Suspend Mode
        2. 35.5.8.2 Wakeup Request
      9. 35.5.9  Test Modes
        1. 35.5.9.1 External Loop Back Mode
        2. 35.5.9.2 Internal Loop Back Mode
      10. 35.5.10 Timestamp Generation
        1. 35.5.10.1 External Timestamp Counter
      11. 35.5.11 Timeout Counter
      12. 35.5.12 Safety
        1. 35.5.12.1 ECC Wrapper
        2. 35.5.12.2 ECC Aggregator
          1. 35.5.12.2.1 ECC Aggregator Overview
          2. 35.5.12.2.2 ECC Aggregator Registers
        3. 35.5.12.3 Reads to ECC Control and Status Registers
        4. 35.5.12.4 ECC Interrupts
      13. 35.5.13 Rx Handling
        1. 35.5.13.1 Acceptance Filtering
          1. 35.5.13.1.1 Range Filter
          2. 35.5.13.1.2 Filter for Specific IDs
          3. 35.5.13.1.3 Classic Bit Mask Filter
          4. 35.5.13.1.4 Standard Message ID Filtering
          5. 35.5.13.1.5 Extended Message ID Filtering
        2. 35.5.13.2 Rx FIFOs
          1. 35.5.13.2.1 Rx FIFO Blocking Mode
          2. 35.5.13.2.2 Rx FIFO Overwrite Mode
        3. 35.5.13.3 Dedicated Rx Buffers
          1. 35.5.13.3.1 Rx Buffer Handling
      14. 35.5.14 Tx Handling
        1. 35.5.14.1 Transmit Pause
        2. 35.5.14.2 Dedicated Tx Buffers
        3. 35.5.14.3 Tx FIFO
        4. 35.5.14.4 Tx Queue
        5. 35.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 35.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 35.5.14.7 Transmit Cancellation
        8. 35.5.14.8 Tx Event Handling
      15. 35.5.15 FIFO Acknowledge Handling
      16. 35.5.16 Message RAM
        1. 35.5.16.1 Message RAM Configuration
        2. 35.5.16.2 Rx Buffer and FIFO Element
        3. 35.5.16.3 Tx Buffer Element
        4. 35.5.16.4 Tx Event FIFO Element
        5. 35.5.16.5 Standard Message ID Filter Element
        6. 35.5.16.6 Extended Message ID Filter Element
    6. 35.6 Software
      1. 35.6.1 MCAN Examples
        1. 35.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        2. 35.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
    7. 35.7 MCAN Registers
      1. 35.7.1 MCAN Base Address Table
      2. 35.7.2 MCANSS_REGS Registers
      3. 35.7.3 MCAN_REGS Registers
      4. 35.7.4 MCAN_ERROR_REGS Registers
      5. 35.7.5 MCAN Registers to Driverlib Functions
  38. 36Universal Asynchronous Receiver/Transmitter (UART)
    1. 36.1 Introduction
      1. 36.1.1 Features
      2. 36.1.2 Block Diagram
    2. 36.2 Functional Description
      1. 36.2.1 Transmit and Receive Logic
      2. 36.2.2 Baud-Rate Generation
      3. 36.2.3 Data Transmission
      4. 36.2.4 Serial IR (SIR)
      5. 36.2.5 9-Bit UART Mode
      6. 36.2.6 FIFO Operation
      7. 36.2.7 Interrupts
      8. 36.2.8 Loopback Operation
      9. 36.2.9 DMA Operation
        1. 36.2.9.1 Receiving Data Using UART with DMA
        2. 36.2.9.2 Transmitting Data Using UART with DMA
    3. 36.3 Initialization and Configuration
    4. 36.4 Software
      1. 36.4.1 UART Examples
        1. 36.4.1.1 UART Loopback - SINGLE_CORE
        2. 36.4.1.2 UART Loopback with Interrupt - SINGLE_CORE
        3. 36.4.1.3 UART Loopback with DMA - SINGLE_CORE
    5. 36.5 UART Registers
      1. 36.5.1 UART Base Address Table
      2. 36.5.2 UART_REGS Registers
      3. 36.5.3 UART_REGS_WRITE Registers
      4. 36.5.4 UART Registers to Driverlib Functions
  39. 37Local Interconnect Network (LIN)
    1. 37.1 LIN Overview
      1. 37.1.1 SCI Features
      2. 37.1.2 LIN Features
      3. 37.1.3 LIN Related Collateral
      4. 37.1.4 Block Diagram
    2. 37.2 Serial Communications Interface Module
      1. 37.2.1 SCI Communication Formats
        1. 37.2.1.1 SCI Frame Formats
        2. 37.2.1.2 SCI Asynchronous Timing Mode
        3. 37.2.1.3 SCI Baud Rate
          1. 37.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 37.2.1.4 SCI Multiprocessor Communication Modes
          1. 37.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 37.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 37.2.1.5 SCI Multibuffered Mode
      2. 37.2.2 SCI Interrupts
        1. 37.2.2.1 Transmit Interrupt
        2. 37.2.2.2 Receive Interrupt
        3. 37.2.2.3 WakeUp Interrupt
        4. 37.2.2.4 Error Interrupts
      3. 37.2.3 SCI DMA Interface
        1. 37.2.3.1 Receive DMA Requests
        2. 37.2.3.2 Transmit DMA Requests
      4. 37.2.4 SCI Configurations
        1. 37.2.4.1 Receiving Data
          1. 37.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 37.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 37.2.4.2 Transmitting Data
          1. 37.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 37.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 37.2.5 SCI Low-Power Mode
        1. 37.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 37.3 Local Interconnect Network Module
      1. 37.3.1 LIN Communication Formats
        1. 37.3.1.1  LIN Standards
        2. 37.3.1.2  Message Frame
          1. 37.3.1.2.1 Message Header
          2. 37.3.1.2.2 Response
        3. 37.3.1.3  Synchronizer
        4. 37.3.1.4  Baud Rate
          1. 37.3.1.4.1 Fractional Divider
          2. 37.3.1.4.2 Superfractional Divider
            1. 37.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 37.3.1.5  Header Generation
          1. 37.3.1.5.1 Event Triggered Frame Handling
          2. 37.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 37.3.1.6  Extended Frames Handling
        7. 37.3.1.7  Timeout Control
          1. 37.3.1.7.1 No-Response Error (NRE)
          2. 37.3.1.7.2 Bus Idle Detection
          3. 37.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 37.3.1.8  TXRX Error Detector (TED)
          1. 37.3.1.8.1 Bit Errors
          2. 37.3.1.8.2 Physical Bus Errors
          3. 37.3.1.8.3 ID Parity Errors
          4. 37.3.1.8.4 Checksum Errors
        9. 37.3.1.9  Message Filtering and Validation
        10. 37.3.1.10 Receive Buffers
        11. 37.3.1.11 Transmit Buffers
      2. 37.3.2 LIN Interrupts
      3. 37.3.3 Servicing LIN Interrupts
      4. 37.3.4 LIN DMA Interface
        1. 37.3.4.1 LIN Receive DMA Requests
        2. 37.3.4.2 LIN Transmit DMA Requests
      5. 37.3.5 LIN Configurations
        1. 37.3.5.1 Receiving Data
          1. 37.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 37.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 37.3.5.2 Transmitting Data
          1. 37.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 37.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 37.4 Low-Power Mode
      1. 37.4.1 Entering Sleep Mode
      2. 37.4.2 Wakeup
      3. 37.4.3 Wakeup Timeouts
    5. 37.5 Emulation Mode
    6. 37.6 Software
      1. 37.6.1 LIN Examples
        1. 37.6.1.1 LIN Internal Loopback with Interrupts - SINGLE_CORE
        2. 37.6.1.2 LIN SCI Mode Internal Loopback with Interrupts - SINGLE_CORE
        3. 37.6.1.3 LIN SCI MODE Internal Loopback with DMA - SINGLE_CORE
        4. 37.6.1.4 LIN Internal Loopback without interrupts (polled mode) - SINGLE_CORE
        5. 37.6.1.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA - SINGLE_CORE
    7. 37.7 SCI/LIN Registers
      1. 37.7.1 LIN Base Address Table
      2. 37.7.2 LIN_REGS Registers
      3. 37.7.3 LIN Registers to Driverlib Functions
  40. 38Lockstep Compare Module (LCM)
    1. 38.1 Introduction
      1. 38.1.1 Features
      2. 38.1.2 Block Diagram
    2. 38.2 Enabling LCM Comparators
    3. 38.3 Disabling LCM Redundant Module
    4. 38.4 LCM Error Handling
    5. 38.5 LCM Error Flags
    6. 38.6 Debug Mode with LCM
    7. 38.7 Register Parity Error Protection
    8. 38.8 Functional Logic
      1. 38.8.1 Comparator Logic
      2. 38.8.2 Self-Test Logic
        1. 38.8.2.1 Match Test Mode
        2. 38.8.2.2 Mismatch Test Mode
      3. 38.8.3 Error Injection Tests
        1. 38.8.3.1 Comparator Error Force Test
        2. 38.8.3.2 Register Parity Error Test
    9. 38.9 LCM Registers
      1. 38.9.1 LCM Base Address Table
      2. 38.9.2 LCM_REGS Registers
      3. 38.9.3 LCM Registers to Driverlib Functions
  41. 39Revision History

8.10.2 CLB_LOGIC_CONFIG_REGS Registers

Table 8-21 lists the memory-mapped registers for the CLB_LOGIC_CONFIG_REGS registers. All register offset addresses not listed in Table 8-21 should be considered as reserved locations and the register contents should not be modified.

Table 8-21 CLB_LOGIC_CONFIG_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
2hCLB_COUNT_RESETCounter Block RESETEALLOW, LOCKGo
4hCLB_COUNT_MODE_1Counter Block MODE_1EALLOW, LOCKGo
6hCLB_COUNT_MODE_0Counter Block MODE_0EALLOW, LOCKGo
8hCLB_COUNT_EVENTCounter Block EVENTEALLOW, LOCKGo
AhCLB_FSM_EXTRA_IN0FSM Extra EXT_IN0EALLOW, LOCKGo
ChCLB_FSM_EXTERNAL_IN0FSM EXT_IN0EALLOW, LOCKGo
EhCLB_FSM_EXTERNAL_IN1FSM_EXT_IN1EALLOW, LOCKGo
10hCLB_FSM_EXTRA_IN1FSM Extra_EXT_IN1EALLOW, LOCKGo
12hCLB_LUT4_IN0LUT4_0/1/2 IN0 input sourceEALLOW, LOCKGo
14hCLB_LUT4_IN1LUT4_0/1/2 IN1 input sourceEALLOW, LOCKGo
16hCLB_LUT4_IN2LUT4_0/1/2 IN2 input sourceEALLOW, LOCKGo
18hCLB_LUT4_IN3LUT4_0/1/2 IN3 input sourceEALLOW, LOCKGo
1ChCLB_FSM_LUT_FN1_0LUT function for FSM Unit 1 and Unit 0EALLOW, LOCKGo
1EhCLB_FSM_LUT_FN2LUT function for FSM Unit 2EALLOW, LOCKGo
20hCLB_LUT4_FN1_0LUT function for LUT4 block of Unit 1 and 0EALLOW, LOCKGo
22hCLB_LUT4_FN2LUT function for LUT4 block of Unit 2EALLOW, LOCKGo
24hCLB_FSM_NEXT_STATE_0FSM Next state equations for Unit 0EALLOW, LOCKGo
26hCLB_FSM_NEXT_STATE_1FSM Next state equations for Unit 1EALLOW, LOCKGo
28hCLB_FSM_NEXT_STATE_2FSM Next state equations for Unit 2EALLOW, LOCKGo
2AhCLB_MISC_CONTROLStatic controls for Ctr,FSMEALLOW, LOCKGo
2ChCLB_OUTPUT_LUT_0Inp Sel, LUT fns for Out0EALLOW, LOCKGo
2EhCLB_OUTPUT_LUT_1Inp Sel, LUT fns for Out1EALLOW, LOCKGo
30hCLB_OUTPUT_LUT_2Inp Sel, LUT fns for Out2EALLOW, LOCKGo
32hCLB_OUTPUT_LUT_3Inp Sel, LUT fns for Out3EALLOW, LOCKGo
34hCLB_OUTPUT_LUT_4Inp Sel, LUT fns for Out4EALLOW, LOCKGo
36hCLB_OUTPUT_LUT_5Inp Sel, LUT fns for Out5EALLOW, LOCKGo
38hCLB_OUTPUT_LUT_6Inp Sel, LUT fns for Out6EALLOW, LOCKGo
3AhCLB_OUTPUT_LUT_7Inp Sel, LUT fns for Out7EALLOW, LOCKGo
3ChCLB_HLC_EVENT_SELEvent Selector register for the High Level controllerEALLOW, LOCKGo
3EhCLB_COUNT_MATCH_TAP_SELCounter tap values for match1 and match2 outputsEALLOW, LOCKGo
40hCLB_OUTPUT_COND_CTRL_0Output conditioning control for output 0EALLOW, LOCKGo
42hCLB_OUTPUT_COND_CTRL_1Output conditioning control for output 1EALLOW, LOCKGo
44hCLB_OUTPUT_COND_CTRL_2Output conditioning control for output 2EALLOW, LOCKGo
46hCLB_OUTPUT_COND_CTRL_3Output conditioning control for output 3EALLOW, LOCKGo
48hCLB_OUTPUT_COND_CTRL_4Output conditioning control for output 4EALLOW, LOCKGo
4AhCLB_OUTPUT_COND_CTRL_5Output conditioning control for output 5EALLOW, LOCKGo
4ChCLB_OUTPUT_COND_CTRL_6Output conditioning control for output 6EALLOW, LOCKGo
4EhCLB_OUTPUT_COND_CTRL_7Output conditioning control for output 7EALLOW, LOCKGo
50hCLB_MISC_ACCESS_CTRLMiscellaneous Access and enable controlEALLOW, LOCKGo
51hCLB_SPI_DATA_CTRL_HICLB to SPI buffer control HighEALLOW, LOCKGo

Complex bit access types are encoded to fit into small table cells. Table 8-22 shows the codes that are used for access types in this section.

Table 8-22 CLB_LOGIC_CONFIG_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

8.10.2.1 CLB_COUNT_RESET Register (Offset = 2h) [Reset = 00000000h]

CLB_COUNT_RESET is shown in Figure 8-22 and described in Table 8-23.

Return to the Summary Table.

Counter Block RESET

Figure 8-22 CLB_COUNT_RESET Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-23 CLB_COUNT_RESET Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hCounter reset select inputs for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hCounter reset select inputs for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hCounter reset select inputs for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.2 CLB_COUNT_MODE_1 Register (Offset = 4h) [Reset = 00000000h]

CLB_COUNT_MODE_1 is shown in Figure 8-23 and described in Table 8-24.

Return to the Summary Table.

Counter Block MODE_1

Figure 8-23 CLB_COUNT_MODE_1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-24 CLB_COUNT_MODE_1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hCounter MODE_1 select inputs for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hCounter MODE_1 select inputs for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hCounter MODE_1 select inputs for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.3 CLB_COUNT_MODE_0 Register (Offset = 6h) [Reset = 00000000h]

CLB_COUNT_MODE_0 is shown in Figure 8-24 and described in Table 8-25.

Return to the Summary Table.

Counter Block MODE_0

Figure 8-24 CLB_COUNT_MODE_0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-25 CLB_COUNT_MODE_0 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hCounter MODE_0 select inputs for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hCounter MODE_0 select inputs for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hCounter MODE_0 select inputs for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.4 CLB_COUNT_EVENT Register (Offset = 8h) [Reset = 00000000h]

CLB_COUNT_EVENT is shown in Figure 8-25 and described in Table 8-26.

Return to the Summary Table.

Counter Block EVENT

Figure 8-25 CLB_COUNT_EVENT Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-26 CLB_COUNT_EVENT Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hCounter event select inputs for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hCounter event select inputs for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hCounter event select inputs for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.5 CLB_FSM_EXTRA_IN0 Register (Offset = Ah) [Reset = 00000000h]

CLB_FSM_EXTRA_IN0 is shown in Figure 8-26 and described in Table 8-27.

Return to the Summary Table.

FSM Extra EXT_IN0

Figure 8-26 CLB_FSM_EXTRA_IN0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-27 CLB_FSM_EXTRA_IN0 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hFSM block extra external IN0 select inputs for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hFSM block extra external IN0 select inputs for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hFSM block extra external IN0 select inputs for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.6 CLB_FSM_EXTERNAL_IN0 Register (Offset = Ch) [Reset = 00000000h]

CLB_FSM_EXTERNAL_IN0 is shown in Figure 8-27 and described in Table 8-28.

Return to the Summary Table.

FSM EXT_IN0

Figure 8-27 CLB_FSM_EXTERNAL_IN0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-28 CLB_FSM_EXTERNAL_IN0 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hFSM block EXT_IN0 select input for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hFSM block EXT_IN0 select input for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hFSM block EXT_IN0 select input for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.7 CLB_FSM_EXTERNAL_IN1 Register (Offset = Eh) [Reset = 00000000h]

CLB_FSM_EXTERNAL_IN1 is shown in Figure 8-28 and described in Table 8-29.

Return to the Summary Table.

FSM_EXT_IN1

Figure 8-28 CLB_FSM_EXTERNAL_IN1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-29 CLB_FSM_EXTERNAL_IN1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hFSM block EXT_IN1 select input for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hFSM block EXT_IN1 select input for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hFSM block EXT_IN1 select input for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.8 CLB_FSM_EXTRA_IN1 Register (Offset = 10h) [Reset = 00000000h]

CLB_FSM_EXTRA_IN1 is shown in Figure 8-29 and described in Table 8-30.

Return to the Summary Table.

FSM Extra_EXT_IN1

Figure 8-29 CLB_FSM_EXTRA_IN1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-30 CLB_FSM_EXTRA_IN1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hFSM block extra external IN1 select inputs for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hFSM block extra external IN1 select inputs for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hFSM block extra external IN1 select inputs for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.9 CLB_LUT4_IN0 Register (Offset = 12h) [Reset = 00000000h]

CLB_LUT4_IN0 is shown in Figure 8-30 and described in Table 8-31.

Return to the Summary Table.

LUT4_0/1/2 IN0 input source

Figure 8-30 CLB_LUT4_IN0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-31 CLB_LUT4_IN0 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hLUT4 block IN0 select inputs for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hLUT4 block IN0 select inputs for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hLUT4 block IN0 select inputs for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.10 CLB_LUT4_IN1 Register (Offset = 14h) [Reset = 00000000h]

CLB_LUT4_IN1 is shown in Figure 8-31 and described in Table 8-32.

Return to the Summary Table.

LUT4_0/1/2 IN1 input source

Figure 8-31 CLB_LUT4_IN1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-32 CLB_LUT4_IN1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hLUT4 block IN1 select inputs for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hLUT4 block IN1 select inputs for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hLUT4 block IN1 select inputs for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.11 CLB_LUT4_IN2 Register (Offset = 16h) [Reset = 00000000h]

CLB_LUT4_IN2 is shown in Figure 8-32 and described in Table 8-33.

Return to the Summary Table.

LUT4_0/1/2 IN2 input source

Figure 8-32 CLB_LUT4_IN2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-33 CLB_LUT4_IN2 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hLUT4 block IN2 select inputs for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hLUT4 block IN2 select inputs for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hLUT4 block IN2 select inputs for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.12 CLB_LUT4_IN3 Register (Offset = 18h) [Reset = 00000000h]

CLB_LUT4_IN3 is shown in Figure 8-33 and described in Table 8-34.

Return to the Summary Table.

LUT4_0/1/2 IN3 input source

Figure 8-33 CLB_LUT4_IN3 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEL_2SEL_1SEL_0
R/W1C-0hR/W-0hR/W-0hR/W-0h
Table 8-34 CLB_LUT4_IN3 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14-10SEL_2R/W0hLUT4 block IN3 select inputs for unit 2. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5SEL_1R/W0hLUT4 block IN3 select inputs for unit 1. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0SEL_0R/W0hLUT4 block IN3 select inputs for unit 0. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.13 CLB_FSM_LUT_FN1_0 Register (Offset = 1Ch) [Reset = 00000000h]

CLB_FSM_LUT_FN1_0 is shown in Figure 8-34 and described in Table 8-35.

Return to the Summary Table.

LUT function for FSM Unit 1 and Unit 0

Figure 8-34 CLB_FSM_LUT_FN1_0 Register
313029282726252423222120191817161514131211109876543210
FN1FN0
R/W-0hR/W-0h
Table 8-35 CLB_FSM_LUT_FN1_0 Register Field Descriptions
BitFieldTypeResetDescription
31-16FN1R/W0hFSM block LUT output function for unit 1

Reset type: SYSRSn

15-0FN0R/W0hFSM block LUT output function for unit 0

Reset type: SYSRSn

8.10.2.14 CLB_FSM_LUT_FN2 Register (Offset = 1Eh) [Reset = 00000000h]

CLB_FSM_LUT_FN2 is shown in Figure 8-35 and described in Table 8-36.

Return to the Summary Table.

LUT function for FSM Unit 2

Figure 8-35 CLB_FSM_LUT_FN2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDFN1
R/W1C-0hR/W-0h
Table 8-36 CLB_FSM_LUT_FN2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W1C0hReserved
15-0FN1R/W0hLUT4 output function for unit 2

Reset type: SYSRSn

8.10.2.15 CLB_LUT4_FN1_0 Register (Offset = 20h) [Reset = 00000000h]

CLB_LUT4_FN1_0 is shown in Figure 8-36 and described in Table 8-37.

Return to the Summary Table.

LUT function for LUT4 block of Unit 1 and 0

Figure 8-36 CLB_LUT4_FN1_0 Register
313029282726252423222120191817161514131211109876543210
FN1FN0
R/W-0hR/W-0h
Table 8-37 CLB_LUT4_FN1_0 Register Field Descriptions
BitFieldTypeResetDescription
31-16FN1R/W0hLUT4 output function for unit 1

Reset type: SYSRSn

15-0FN0R/W0hLUT4 output function for unit 0

Reset type: SYSRSn

8.10.2.16 CLB_LUT4_FN2 Register (Offset = 22h) [Reset = 00000000h]

CLB_LUT4_FN2 is shown in Figure 8-37 and described in Table 8-38.

Return to the Summary Table.

LUT function for LUT4 block of Unit 2

Figure 8-37 CLB_LUT4_FN2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDFN1
R/W1C-0hR/W-0h
Table 8-38 CLB_LUT4_FN2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W1C0hReserved
15-0FN1R/W0hLUT4 output function for unit 2

Reset type: SYSRSn

8.10.2.17 CLB_FSM_NEXT_STATE_0 Register (Offset = 24h) [Reset = 00000000h]

CLB_FSM_NEXT_STATE_0 is shown in Figure 8-38 and described in Table 8-39.

Return to the Summary Table.

FSM Next state equations for Unit 0

Figure 8-38 CLB_FSM_NEXT_STATE_0 Register
313029282726252423222120191817161514131211109876543210
S1S0
R/W-0hR/W-0h
Table 8-39 CLB_FSM_NEXT_STATE_0 Register Field Descriptions
BitFieldTypeResetDescription
31-16S1R/W0hFSM next state function for S1, unit0

Reset type: SYSRSn

15-0S0R/W0hFSM next state function for S0, unit0

Reset type: SYSRSn

8.10.2.18 CLB_FSM_NEXT_STATE_1 Register (Offset = 26h) [Reset = 00000000h]

CLB_FSM_NEXT_STATE_1 is shown in Figure 8-39 and described in Table 8-40.

Return to the Summary Table.

FSM Next state equations for Unit 1

Figure 8-39 CLB_FSM_NEXT_STATE_1 Register
313029282726252423222120191817161514131211109876543210
S1S0
R/W-0hR/W-0h
Table 8-40 CLB_FSM_NEXT_STATE_1 Register Field Descriptions
BitFieldTypeResetDescription
31-16S1R/W0hFSM next state function for S1, unit1

Reset type: SYSRSn

15-0S0R/W0hFSM next state function for S0, unit1

Reset type: SYSRSn

8.10.2.19 CLB_FSM_NEXT_STATE_2 Register (Offset = 28h) [Reset = 00000000h]

CLB_FSM_NEXT_STATE_2 is shown in Figure 8-40 and described in Table 8-41.

Return to the Summary Table.

FSM Next state equations for Unit 2

Figure 8-40 CLB_FSM_NEXT_STATE_2 Register
313029282726252423222120191817161514131211109876543210
S1S0
R/W-0hR/W-0h
Table 8-41 CLB_FSM_NEXT_STATE_2 Register Field Descriptions
BitFieldTypeResetDescription
31-16S1R/W0hFSM next state function for S1, unit2

Reset type: SYSRSn

15-0S0R/W0hFSM next state function for S0, unit2

Reset type: SYSRSn

8.10.2.20 CLB_MISC_CONTROL Register (Offset = 2Ah) [Reset = 00000000h]

CLB_MISC_CONTROL is shown in Figure 8-41 and described in Table 8-42.

Return to the Summary Table.

Static controls for Ctr,FSM

Figure 8-41 CLB_MISC_CONTROL Register
3130292827262524
RESERVEDCOUNT2_LFSR_ENCOUNT1_LFSR_ENCOUNT0_LFSR_EN
R-0-0hR/W-0hR/W-0hR/W-0h
2322212019181716
COUNT2_MATCH2_TAP_ENCOUNT1_MATCH2_TAP_ENCOUNT0_MATCH2_TAP_ENCOUNT2_MATCH1_TAP_ENCOUNT1_MATCH1_TAP_ENCOUNT0_MATCH1_TAP_ENFSM_EXTRA_SEL1_2FSM_EXTRA_SEL0_2
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
FSM_EXTRA_SEL1_1FSM_EXTRA_SEL0_1FSM_EXTRA_SEL1_0FSM_EXTRA_SEL0_0COUNT_SERIALIZER_2COUNT_SERIALIZER_1COUNT_SERIALIZER_0COUNT_EVENT_CTRL_2
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
COUNT_DIR_2COUNT_ADD_SHIFT_2COUNT_EVENT_CTRL_1COUNT_DIR_1COUNT_ADD_SHIFT_1COUNT_EVENT_CTRL_0COUNT_DIR_0COUNT_ADD_SHIFT_0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-42 CLB_MISC_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR-00hReserved
26COUNT2_LFSR_ENR/W0hDefines if Counter 2 should operate in LFSR mode. This should be set to 1 only if it is in the SERIALIZER mode.
0 = Selects normal serializer operation
1 = Selects LFSR mode of operation

Reset type: SYSRSn

25COUNT1_LFSR_ENR/W0hDefines if Counter 1 should operate in LFSR mode. This should be set to 1 only if it is in the SERIALIZER mode.
0 = Selects normal serializer operation
1 = Selects LFSR mode of operation

Reset type: SYSRSn

24COUNT0_LFSR_ENR/W0hDefines if Counter 0 should operate in LFSR mode. This should be set to 1 only if it is in the SERIALIZER mode.
0 = Selects normal serializer operation
1 = Selects LFSR mode of operation

Reset type: SYSRSn

23COUNT2_MATCH2_TAP_ENR/W0hDefines if the Match2 output should come from the match unit or tapped from a bit position of the counter
0 = Selects Match2 comaprison output
1 = Selects Bit position defined by Match2_Tap_val

Reset type: SYSRSn

22COUNT1_MATCH2_TAP_ENR/W0hDefines if the Match2 output should come from the match unit or tapped from a bit position of the counter
0 = Selects Match2 comaprison output
1 = Selects Bit position defined by Match2_Tap_val

Reset type: SYSRSn

21COUNT0_MATCH2_TAP_ENR/W0hDefines if the Match2 output should come from the match unit or tapped from a bit position of the counter
0 = Selects Match2 comaprison output
1 = Selects Bit position defined by Match2_Tap_val

Reset type: SYSRSn

20COUNT2_MATCH1_TAP_ENR/W0hDefines if the Match1 output should come from the match unit or tapped from a bit position of the counter
0 = Selects Match1 comaprison output
1 = Selects Bit position defined by Match1_Tap_val

Reset type: SYSRSn

19COUNT1_MATCH1_TAP_ENR/W0hDefines if the Match1 output should come from the match unit or tapped from a bit position of the counter
0 = Selects Match1 comaprison output
1 = Selects Bit position defined by Match1_Tap_val

Reset type: SYSRSn

18COUNT0_MATCH1_TAP_ENR/W0hDefines if the Match1 output should come from the match unit or tapped from a bit position of the counter
0 = Selects Match1 comaprison output
1 = Selects Bit position defined by Match1_Tap_val

Reset type: SYSRSn

17FSM_EXTRA_SEL1_2R/W0hDefines which input should be selected for the FSM LUT of UNIT 2
0 = Selects State S1 for the FSM LUT
1 = Selects EXTRA_EXT_IN1 for the FSM LUT

Reset type: SYSRSn

16FSM_EXTRA_SEL0_2R/W0hDefines which input should be selected for the FSM LUT of UNIT 2
0 = Selects State S0 for the FSM LUT
1 = Selects EXTRA_EXT_IN0 for the FSM LUT

Reset type: SYSRSn

15FSM_EXTRA_SEL1_1R/W0hDefines which input should be selected for the FSM LUT of UNIT 1
0 = Selects State S1 for the FSM LUT
1 = Selects EXTRA_EXT_IN1 for the FSM LUT

Reset type: SYSRSn

14FSM_EXTRA_SEL0_1R/W0hDefines which input should be selected for the FSM LUT of UNIT 1
0 = Selects State S0 for the FSM LUT
1 = Selects EXTRA_EXT_IN0 for the FSM LUT

Reset type: SYSRSn

13FSM_EXTRA_SEL1_0R/W0hDefines which input should be selected for the FSM LUT of UNIT 0
0 = Selects State S1 for the FSM LUT
1 = Selects EXTRA_EXT_IN1 for the FSM LUT

Reset type: SYSRSn

12FSM_EXTRA_SEL0_0R/W0hDefines which input should be selected for the FSM LUT of UNIT 0
0 = Selects State S0 for the FSM LUT
1 = Selects EXTRA_EXT_IN0 for the FSM LUT

Reset type: SYSRSn

11COUNT_SERIALIZER_2R/W0hControls if the Counter of UNIT 2 is the Serialzer mode or not.
0 = Normal mode
1 = Serializer mode

Reset type: SYSRSn

10COUNT_SERIALIZER_1R/W0hControls if the Counter of UNIT 1 is the Serialzer mode or not.
0 = Normal mode
1 = Serializer mode

Reset type: SYSRSn

9COUNT_SERIALIZER_0R/W0hControls if the Counter of UNIT 0 is the Serialzer mode or not.
0 = Normal mode
1 = Serializer mode

Reset type: SYSRSn

8COUNT_EVENT_CTRL_2R/W0hControls the actions on an EVENT for UNIT2. Must be 0 for indirect loads and HLC loads of the counter to take effect.
0 = No add or shift, but load the predefined value
1 = Based on other bits, add/shift with the predefined value

Reset type: SYSRSn

7COUNT_DIR_2R/W0hControls add/shift direction for UNIT 2
0 = right shift or subtract
1 = left shift or add

Reset type: SYSRSn

6COUNT_ADD_SHIFT_2R/W0hControls whether the UNIT 2 counter will do an ADD or a SHIFT on an EVENT.
0 =Shift
1 = ADD

Reset type: SYSRSn

5COUNT_EVENT_CTRL_1R/W0hControls the actions on an EVENT for UNIT1. Must be 0 for indirect loads and HLC loads of the counter to take effect.
0 = No add or shift, but load the predefined value
1 = Based on other bits, add/shift with the predefined value

Reset type: SYSRSn

4COUNT_DIR_1R/W0hControls add/shift direction for UNIT 1
0 = right shift or subtract
1 = left shift or add

Reset type: SYSRSn

3COUNT_ADD_SHIFT_1R/W0hControls whether the UNIT 1 counter will do an ADD or a SHIFT on an EVENT.
0 = Shift
1 = ADD

Reset type: SYSRSn

2COUNT_EVENT_CTRL_0R/W0hControls the actions on an EVENT for UNIT1. Must be 0 for indirect loads and HLC loads of the counter to take effect.
0 = No add or shift, but load the predefined value
1 = Based on other bits, add/shift with the predefined value

Reset type: SYSRSn

1COUNT_DIR_0R/W0hControls add/shift direction for UNIT 0
0 = right shift or subtract
1 = left shift or add

Reset type: SYSRSn

0COUNT_ADD_SHIFT_0R/W0hControls whether the UNIT 0 counter will do an ADD or a SHIFT on an EVENT.
0 = Shift
1 = ADD

Reset type: SYSRSn

8.10.2.21 CLB_OUTPUT_LUT_0 Register (Offset = 2Ch) [Reset = 00000000h]

CLB_OUTPUT_LUT_0 is shown in Figure 8-42 and described in Table 8-43.

Return to the Summary Table.

Inp Sel, LUT fns for Out0

Figure 8-42 CLB_OUTPUT_LUT_0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDFNIN2IN1IN0
R/W1C-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-43 CLB_OUTPUT_LUT_0 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/W1C0hReserved
22-15FNR/W0hOutput function for output LUT

Reset type: SYSRSn

14-10IN2R/W0hSelect value for IN2 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5IN1R/W0hSelect value for IN1 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0IN0R/W0hSelect value for IN0 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.22 CLB_OUTPUT_LUT_1 Register (Offset = 2Eh) [Reset = 00000000h]

CLB_OUTPUT_LUT_1 is shown in Figure 8-43 and described in Table 8-44.

Return to the Summary Table.

Inp Sel, LUT fns for Out1

Figure 8-43 CLB_OUTPUT_LUT_1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDFNIN2IN1IN0
R/W1C-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-44 CLB_OUTPUT_LUT_1 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/W1C0hReserved
22-15FNR/W0hOutput function for output LUT

Reset type: SYSRSn

14-10IN2R/W0hSelect value for IN2 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5IN1R/W0hSelect value for IN1 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0IN0R/W0hSelect value for IN0 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.23 CLB_OUTPUT_LUT_2 Register (Offset = 30h) [Reset = 00000000h]

CLB_OUTPUT_LUT_2 is shown in Figure 8-44 and described in Table 8-45.

Return to the Summary Table.

Inp Sel, LUT fns for Out2

Figure 8-44 CLB_OUTPUT_LUT_2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDFNIN2IN1IN0
R/W1C-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-45 CLB_OUTPUT_LUT_2 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/W1C0hReserved
22-15FNR/W0hOutput function for output LUT

Reset type: SYSRSn

14-10IN2R/W0hSelect value for IN2 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5IN1R/W0hSelect value for IN1 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0IN0R/W0hSelect value for IN0 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.24 CLB_OUTPUT_LUT_3 Register (Offset = 32h) [Reset = 00000000h]

CLB_OUTPUT_LUT_3 is shown in Figure 8-45 and described in Table 8-46.

Return to the Summary Table.

Inp Sel, LUT fns for Out3

Figure 8-45 CLB_OUTPUT_LUT_3 Register
313029282726252423222120191817161514131211109876543210
RESERVEDFNIN2IN1IN0
R/W1C-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-46 CLB_OUTPUT_LUT_3 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/W1C0hReserved
22-15FNR/W0hOutput function for output LUT

Reset type: SYSRSn

14-10IN2R/W0hSelect value for IN2 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5IN1R/W0hSelect value for IN1 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0IN0R/W0hSelect value for IN0 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.25 CLB_OUTPUT_LUT_4 Register (Offset = 34h) [Reset = 00000000h]

CLB_OUTPUT_LUT_4 is shown in Figure 8-46 and described in Table 8-47.

Return to the Summary Table.

Inp Sel, LUT fns for Out4

Figure 8-46 CLB_OUTPUT_LUT_4 Register
313029282726252423222120191817161514131211109876543210
RESERVEDFNIN2IN1IN0
R/W1C-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-47 CLB_OUTPUT_LUT_4 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/W1C0hReserved
22-15FNR/W0hOutput function for output LUT

Reset type: SYSRSn

14-10IN2R/W0hSelect value for IN2 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5IN1R/W0hSelect value for IN1 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0IN0R/W0hSelect value for IN0 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.26 CLB_OUTPUT_LUT_5 Register (Offset = 36h) [Reset = 00000000h]

CLB_OUTPUT_LUT_5 is shown in Figure 8-47 and described in Table 8-48.

Return to the Summary Table.

Inp Sel, LUT fns for Out5

Figure 8-47 CLB_OUTPUT_LUT_5 Register
313029282726252423222120191817161514131211109876543210
RESERVEDFNIN2IN1IN0
R/W1C-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-48 CLB_OUTPUT_LUT_5 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/W1C0hReserved
22-15FNR/W0hOutput function for output LUT

Reset type: SYSRSn

14-10IN2R/W0hSelect value for IN2 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5IN1R/W0hSelect value for IN1 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0IN0R/W0hSelect value for IN0 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.27 CLB_OUTPUT_LUT_6 Register (Offset = 38h) [Reset = 00000000h]

CLB_OUTPUT_LUT_6 is shown in Figure 8-48 and described in Table 8-49.

Return to the Summary Table.

Inp Sel, LUT fns for Out6

Figure 8-48 CLB_OUTPUT_LUT_6 Register
313029282726252423222120191817161514131211109876543210
RESERVEDFNIN2IN1IN0
R/W1C-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-49 CLB_OUTPUT_LUT_6 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/W1C0hReserved
22-15FNR/W0hOutput function for output LUT

Reset type: SYSRSn

14-10IN2R/W0hSelect value for IN2 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5IN1R/W0hSelect value for IN1 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0IN0R/W0hSelect value for IN0 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.28 CLB_OUTPUT_LUT_7 Register (Offset = 3Ah) [Reset = 00000000h]

CLB_OUTPUT_LUT_7 is shown in Figure 8-49 and described in Table 8-50.

Return to the Summary Table.

Inp Sel, LUT fns for Out7

Figure 8-49 CLB_OUTPUT_LUT_7 Register
313029282726252423222120191817161514131211109876543210
RESERVEDFNIN2IN1IN0
R/W1C-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-50 CLB_OUTPUT_LUT_7 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/W1C0hReserved
22-15FNR/W0hOutput function for output LUT

Reset type: SYSRSn

14-10IN2R/W0hSelect value for IN2 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5IN1R/W0hSelect value for IN1 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0IN0R/W0hSelect value for IN0 of output LUT. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.29 CLB_HLC_EVENT_SEL Register (Offset = 3Ch) [Reset = 00000000h]

CLB_HLC_EVENT_SEL is shown in Figure 8-50 and described in Table 8-51.

Return to the Summary Table.

Event Selector register for the High Level controller

Figure 8-50 CLB_HLC_EVENT_SEL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
ALT_EVENT3_SELALT_EVENT2_SELALT_EVENT1_SELALT_EVENT0_SELEVENT3_SEL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
EVENT3_SELEVENT2_SELEVENT1_SEL
R/W-0hR/W-0hR/W-0h
76543210
EVENT1_SELEVENT0_SEL
R/W-0hR/W-0h
Table 8-51 CLB_HLC_EVENT_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR-00hReserved
23ALT_EVENT3_SELR/W0hDefines selection of alternate inputs for EVENT3

Reset type: SYSRSn

22ALT_EVENT2_SELR/W0hDefines selection of alternate inputs for EVENT2

Reset type: SYSRSn

21ALT_EVENT1_SELR/W0hDefines selection of alternate inputs for EVENT1

Reset type: SYSRSn

20ALT_EVENT0_SELR/W0hDefines selection of alternate inputs for EVENT0

Reset type: SYSRSn

19-15EVENT3_SELR/W0h5 bit select value for EVENT3 of the High Level Controller. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

14-10EVENT2_SELR/W0h5 bit select value for EVENT2 of the High Level Controller. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

9-5EVENT1_SELR/W0h5 bit select value for EVENT1 of the High Level Controller. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

4-0EVENT0_SELR/W0h5 bit select value for EVENT0 of the High Level Controller. See the Static Switch Block Output Mux Table.

Reset type: SYSRSn

8.10.2.30 CLB_COUNT_MATCH_TAP_SEL Register (Offset = 3Eh) [Reset = 00000000h]

CLB_COUNT_MATCH_TAP_SEL is shown in Figure 8-51 and described in Table 8-52.

Return to the Summary Table.

Counter tap values for match1 and match2 outputs

Figure 8-51 CLB_COUNT_MATCH_TAP_SEL Register
3130292827262524
RESERVEDCOUNT2_MATCH2COUNT1_MATCH2
R-0-0hR/W-0hR/W-0h
2322212019181716
COUNT1_MATCH2COUNT0_MATCH2
R/W-0hR/W-0h
15141312111098
RESERVEDCOUNT2_MATCH1COUNT1_MATCH1
R-0-0hR/W-0hR/W-0h
76543210
COUNT1_MATCH1COUNT0_MATCH1
R/W-0hR/W-0h
Table 8-52 CLB_COUNT_MATCH_TAP_SEL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR-00hReserved
30-26COUNT2_MATCH2R/W0h5 bit MUX Select for Match2 Tap for Counter Unit 2

Reset type: SYSRSn

25-21COUNT1_MATCH2R/W0h5 bit MUX Select for Match2 Tap for Counter Unit 1

Reset type: SYSRSn

20-16COUNT0_MATCH2R/W0h5 bit MUX Select for Match2 Tap for Counter Unit 0

Reset type: SYSRSn

15RESERVEDR-00hReserved
14-10COUNT2_MATCH1R/W0h5 bit MUX Select for Match1 Tap for Counter Unit 2

Reset type: SYSRSn

9-5COUNT1_MATCH1R/W0h5 bit MUX Select for Match1 Tap for Counter Unit 1

Reset type: SYSRSn

4-0COUNT0_MATCH1R/W0h5 bit MUX Select for Match1 Tap for Counter Unit 0

Reset type: SYSRSn

8.10.2.31 CLB_OUTPUT_COND_CTRL_0 Register (Offset = 40h) [Reset = 00000000h]

CLB_OUTPUT_COND_CTRL_0 is shown in Figure 8-52 and described in Table 8-53.

Return to the Summary Table.

Output conditioning control for output 0

Figure 8-52 CLB_OUTPUT_COND_CTRL_0 Register
3130292827262524
RESERVED
R/W1C-0h
2322212019181716
RESERVED
R/W1C-0h
15141312111098
RESERVEDASYNC_COND_ENSEL_RAW_INHW_RLS_CTRL_SELHW_GATING_CTRL_SELSEL_RELEASE_CTRL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
SEL_GATING_CTRLLEVEL_3_SELLEVEL_2_SELLEVEL_1_SEL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 8-53 CLB_OUTPUT_COND_CTRL_0 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14ASYNC_COND_ENR/W1C0hControls whether the output will pass through the asynchronous conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path

Reset type: SYSRSn

13SEL_RAW_INR/W1C0hControls whether the CELL outputs or inputs are sent to the output conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.

Reset type: SYSRSn

12HW_RLS_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control

Reset type: SYSRSn

11HW_GATING_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control

Reset type: SYSRSn

10-8SEL_RELEASE_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Release control.

Reset type: SYSRSn

7-5SEL_GATING_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Gating control.

Reset type: SYSRSn

4-3LEVEL_3_SELR/W1C0hControls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of the output
10 Rising edge of Input signal will cause asynchronous SET of the output
11 Input Signal delayed by 1 clock cycle will be sent to the output

Reset type: SYSRSn

2-1LEVEL_2_SELR/W1C0hControls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level

Reset type: SYSRSn

0LEVEL_1_SELR/W1C0hFirst level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level

Reset type: SYSRSn

8.10.2.32 CLB_OUTPUT_COND_CTRL_1 Register (Offset = 42h) [Reset = 00000000h]

CLB_OUTPUT_COND_CTRL_1 is shown in Figure 8-53 and described in Table 8-54.

Return to the Summary Table.

Output conditioning control for output 1

Figure 8-53 CLB_OUTPUT_COND_CTRL_1 Register
3130292827262524
RESERVED
R/W1C-0h
2322212019181716
RESERVED
R/W1C-0h
15141312111098
RESERVEDASYNC_COND_ENSEL_RAW_INHW_RLS_CTRL_SELHW_GATING_CTRL_SELSEL_RELEASE_CTRL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
SEL_GATING_CTRLLEVEL_3_SELLEVEL_2_SELLEVEL_1_SEL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 8-54 CLB_OUTPUT_COND_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14ASYNC_COND_ENR/W1C0hControls whether the output will pass through the asynchronous conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path

Reset type: SYSRSn

13SEL_RAW_INR/W1C0hControls whether the CELL outputs or inputs are sent to the output conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.

Reset type: SYSRSn

12HW_RLS_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control

Reset type: SYSRSn

11HW_GATING_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control

Reset type: SYSRSn

10-8SEL_RELEASE_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Release control.

Reset type: SYSRSn

7-5SEL_GATING_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Gating control.

Reset type: SYSRSn

4-3LEVEL_3_SELR/W1C0hControls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of the output
10 Rising edge of Input signal will cause asynchronous SET of the output
11 Input Signal delayed by 1 clock cycle will be sent to the output

Reset type: SYSRSn

2-1LEVEL_2_SELR/W1C0hControls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level

Reset type: SYSRSn

0LEVEL_1_SELR/W1C0hFirst level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level

Reset type: SYSRSn

8.10.2.33 CLB_OUTPUT_COND_CTRL_2 Register (Offset = 44h) [Reset = 00000000h]

CLB_OUTPUT_COND_CTRL_2 is shown in Figure 8-54 and described in Table 8-55.

Return to the Summary Table.

Output conditioning control for output 2

Figure 8-54 CLB_OUTPUT_COND_CTRL_2 Register
3130292827262524
RESERVED
R/W1C-0h
2322212019181716
RESERVED
R/W1C-0h
15141312111098
RESERVEDASYNC_COND_ENSEL_RAW_INHW_RLS_CTRL_SELHW_GATING_CTRL_SELSEL_RELEASE_CTRL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
SEL_GATING_CTRLLEVEL_3_SELLEVEL_2_SELLEVEL_1_SEL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 8-55 CLB_OUTPUT_COND_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14ASYNC_COND_ENR/W1C0hControls whether the output will pass through the asynchronous conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path

Reset type: SYSRSn

13SEL_RAW_INR/W1C0hControls whether the CELL outputs or inputs are sent to the output conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.

Reset type: SYSRSn

12HW_RLS_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control

Reset type: SYSRSn

11HW_GATING_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control

Reset type: SYSRSn

10-8SEL_RELEASE_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Release control.

Reset type: SYSRSn

7-5SEL_GATING_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Gating control.

Reset type: SYSRSn

4-3LEVEL_3_SELR/W1C0hControls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of the output
10 Rising edge of Input signal will cause asynchronous SET of the output
11 Input Signal delayed by 1 clock cycle will be sent to the output

Reset type: SYSRSn

2-1LEVEL_2_SELR/W1C0hControls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level

Reset type: SYSRSn

0LEVEL_1_SELR/W1C0hFirst level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level

Reset type: SYSRSn

8.10.2.34 CLB_OUTPUT_COND_CTRL_3 Register (Offset = 46h) [Reset = 00000000h]

CLB_OUTPUT_COND_CTRL_3 is shown in Figure 8-55 and described in Table 8-56.

Return to the Summary Table.

Output conditioning control for output 3

Figure 8-55 CLB_OUTPUT_COND_CTRL_3 Register
3130292827262524
RESERVED
R/W1C-0h
2322212019181716
RESERVED
R/W1C-0h
15141312111098
RESERVEDASYNC_COND_ENSEL_RAW_INHW_RLS_CTRL_SELHW_GATING_CTRL_SELSEL_RELEASE_CTRL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
SEL_GATING_CTRLLEVEL_3_SELLEVEL_2_SELLEVEL_1_SEL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 8-56 CLB_OUTPUT_COND_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14ASYNC_COND_ENR/W1C0hControls whether the output will pass through the asynchronous conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path

Reset type: SYSRSn

13SEL_RAW_INR/W1C0hControls whether the CELL outputs or inputs are sent to the output conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.

Reset type: SYSRSn

12HW_RLS_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control

Reset type: SYSRSn

11HW_GATING_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control

Reset type: SYSRSn

10-8SEL_RELEASE_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Release control.

Reset type: SYSRSn

7-5SEL_GATING_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Gating control.

Reset type: SYSRSn

4-3LEVEL_3_SELR/W1C0hControls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of the output
10 Rising edge of Input signal will cause asynchronous SET of the output
11 Input Signal delayed by 1 clock cycle will be sent to the output

Reset type: SYSRSn

2-1LEVEL_2_SELR/W1C0hControls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level

Reset type: SYSRSn

0LEVEL_1_SELR/W1C0hFirst level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level

Reset type: SYSRSn

8.10.2.35 CLB_OUTPUT_COND_CTRL_4 Register (Offset = 48h) [Reset = 00000000h]

CLB_OUTPUT_COND_CTRL_4 is shown in Figure 8-56 and described in Table 8-57.

Return to the Summary Table.

Output conditioning control for output 4

Figure 8-56 CLB_OUTPUT_COND_CTRL_4 Register
3130292827262524
RESERVED
R/W1C-0h
2322212019181716
RESERVED
R/W1C-0h
15141312111098
RESERVEDASYNC_COND_ENSEL_RAW_INHW_RLS_CTRL_SELHW_GATING_CTRL_SELSEL_RELEASE_CTRL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
SEL_GATING_CTRLLEVEL_3_SELLEVEL_2_SELLEVEL_1_SEL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 8-57 CLB_OUTPUT_COND_CTRL_4 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14ASYNC_COND_ENR/W1C0hControls whether the output will pass through the asynchronous conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path

Reset type: SYSRSn

13SEL_RAW_INR/W1C0hControls whether the CELL outputs or inputs are sent to the output conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.

Reset type: SYSRSn

12HW_RLS_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control

Reset type: SYSRSn

11HW_GATING_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control

Reset type: SYSRSn

10-8SEL_RELEASE_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Release control.

Reset type: SYSRSn

7-5SEL_GATING_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Gating control.

Reset type: SYSRSn

4-3LEVEL_3_SELR/W1C0hControls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of the output
10 Rising edge of Input signal will cause asynchronous SET of the output
11 Input Signal delayed by 1 clock cycle will be sent to the output

Reset type: SYSRSn

2-1LEVEL_2_SELR/W1C0hControls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level

Reset type: SYSRSn

0LEVEL_1_SELR/W1C0hFirst level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level

Reset type: SYSRSn

8.10.2.36 CLB_OUTPUT_COND_CTRL_5 Register (Offset = 4Ah) [Reset = 00000000h]

CLB_OUTPUT_COND_CTRL_5 is shown in Figure 8-57 and described in Table 8-58.

Return to the Summary Table.

Output conditioning control for output 5

Figure 8-57 CLB_OUTPUT_COND_CTRL_5 Register
3130292827262524
RESERVED
R/W1C-0h
2322212019181716
RESERVED
R/W1C-0h
15141312111098
RESERVEDASYNC_COND_ENSEL_RAW_INHW_RLS_CTRL_SELHW_GATING_CTRL_SELSEL_RELEASE_CTRL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
SEL_GATING_CTRLLEVEL_3_SELLEVEL_2_SELLEVEL_1_SEL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 8-58 CLB_OUTPUT_COND_CTRL_5 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14ASYNC_COND_ENR/W1C0hControls whether the output will pass through the asynchronous conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path

Reset type: SYSRSn

13SEL_RAW_INR/W1C0hControls whether the CELL outputs or inputs are sent to the output conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.

Reset type: SYSRSn

12HW_RLS_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control

Reset type: SYSRSn

11HW_GATING_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control

Reset type: SYSRSn

10-8SEL_RELEASE_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Release control.

Reset type: SYSRSn

7-5SEL_GATING_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Gating control.

Reset type: SYSRSn

4-3LEVEL_3_SELR/W1C0hControls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of the output
10 Rising edge of Input signal will cause asynchronous SET of the output
11 Input Signal delayed by 1 clock cycle will be sent to the output

Reset type: SYSRSn

2-1LEVEL_2_SELR/W1C0hControls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level

Reset type: SYSRSn

0LEVEL_1_SELR/W1C0hFirst level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level

Reset type: SYSRSn

8.10.2.37 CLB_OUTPUT_COND_CTRL_6 Register (Offset = 4Ch) [Reset = 00000000h]

CLB_OUTPUT_COND_CTRL_6 is shown in Figure 8-58 and described in Table 8-59.

Return to the Summary Table.

Output conditioning control for output 6

Figure 8-58 CLB_OUTPUT_COND_CTRL_6 Register
3130292827262524
RESERVED
R/W1C-0h
2322212019181716
RESERVED
R/W1C-0h
15141312111098
RESERVEDASYNC_COND_ENSEL_RAW_INHW_RLS_CTRL_SELHW_GATING_CTRL_SELSEL_RELEASE_CTRL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
SEL_GATING_CTRLLEVEL_3_SELLEVEL_2_SELLEVEL_1_SEL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 8-59 CLB_OUTPUT_COND_CTRL_6 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14ASYNC_COND_ENR/W1C0hControls whether the output will pass through the asynchronous conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path

Reset type: SYSRSn

13SEL_RAW_INR/W1C0hControls whether the CELL outputs or inputs are sent to the output conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.

Reset type: SYSRSn

12HW_RLS_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control

Reset type: SYSRSn

11HW_GATING_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control

Reset type: SYSRSn

10-8SEL_RELEASE_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Release control.

Reset type: SYSRSn

7-5SEL_GATING_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Gating control.

Reset type: SYSRSn

4-3LEVEL_3_SELR/W1C0hControls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of the output
10 Rising edge of Input signal will cause asynchronous SET of the output
11 Input Signal delayed by 1 clock cycle will be sent to the output

Reset type: SYSRSn

2-1LEVEL_2_SELR/W1C0hControls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level

Reset type: SYSRSn

0LEVEL_1_SELR/W1C0hFirst level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level

Reset type: SYSRSn

8.10.2.38 CLB_OUTPUT_COND_CTRL_7 Register (Offset = 4Eh) [Reset = 00000000h]

CLB_OUTPUT_COND_CTRL_7 is shown in Figure 8-59 and described in Table 8-60.

Return to the Summary Table.

Output conditioning control for output 7

Figure 8-59 CLB_OUTPUT_COND_CTRL_7 Register
3130292827262524
RESERVED
R/W1C-0h
2322212019181716
RESERVED
R/W1C-0h
15141312111098
RESERVEDASYNC_COND_ENSEL_RAW_INHW_RLS_CTRL_SELHW_GATING_CTRL_SELSEL_RELEASE_CTRL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
SEL_GATING_CTRLLEVEL_3_SELLEVEL_2_SELLEVEL_1_SEL
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 8-60 CLB_OUTPUT_COND_CTRL_7 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W1C0hReserved
14ASYNC_COND_ENR/W1C0hControls whether the output will pass through the asynchronous conditioning block or bypass it.
0 Bypass the asynchronous conditioning block
1 Enable the asynchronous conditioning path

Reset type: SYSRSn

13SEL_RAW_INR/W1C0hControls whether the CELL outputs or inputs are sent to the output conditioning block logic.
0 = CELL output (internally delayed by 1 cycle) is used.
1 = CELL input (raw) is used.

Reset type: SYSRSn

12HW_RLS_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the release control
0 SW register value will act as release control
1 Selected CELL output will act as release control

Reset type: SYSRSn

11HW_GATING_CTRL_SELR/W1C0hControls whether the HW (CELL outputs) or software (GP_REG) will act as the gating control
0 SW register value will act as gating control
1 Selected CELL output will act as gating control

Reset type: SYSRSn

10-8SEL_RELEASE_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Release control.

Reset type: SYSRSn

7-5SEL_GATING_CTRLR/W1C0h3 bit MUX selects which will select one of the 8 CELL outputs for Gating control.

Reset type: SYSRSn

4-3LEVEL_3_SELR/W1C0hControls Third level Mux select
00 Input Signal will be sent as is to the output
01 Rising edge of Input signal will cause asynchronous CLEAR of the output
10 Rising edge of Input signal will cause asynchronous SET of the output
11 Input Signal delayed by 1 clock cycle will be sent to the output

Reset type: SYSRSn

2-1LEVEL_2_SELR/W1C0hControls Second level Mux select
00 Input Signal sent as output to next level
01 Input Signal AND Gating_control sent as output to next level
10 Input Signal OR Gating_control sent as output to next level
11 Input Signal XOR Gating_control sent as output to next level

Reset type: SYSRSn

0LEVEL_1_SELR/W1C0hFirst level MUX select value
0 Direct signal sent as output to next level
1 Inverted signal sent as output to the next level

Reset type: SYSRSn

8.10.2.39 CLB_MISC_ACCESS_CTRL Register (Offset = 50h) [Reset = 0000h]

CLB_MISC_ACCESS_CTRL is shown in Figure 8-60 and described in Table 8-61.

Return to the Summary Table.

Miscellaneous Access and enable control

Figure 8-60 CLB_MISC_ACCESS_CTRL Register
15141312111098
RESERVED
R/W1C-0h
76543210
RESERVEDBLKENSPIEN
R/W1C-0hR/W1C-0hR/W1C-0h
Table 8-61 CLB_MISC_ACCESS_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR/W1C0hReserved
1BLKENR/W1C0hThis bit is used to block writes to CLB_OUT_EN
0 Writes to CLB_OUT_EN are allowed
1 Writes to CLB_OUT_EN are blocked

Reset type: SYSRSn

0SPIENR/W1C0hThis bit indicates the status of the SPI buffers ability to export CLB output data.
0 Feature Disabled
1 Feature Enabled

Reset type: SYSRSn

8.10.2.40 CLB_SPI_DATA_CTRL_HI Register (Offset = 51h) [Reset = 0000h]

CLB_SPI_DATA_CTRL_HI is shown in Figure 8-61 and described in Table 8-62.

Return to the Summary Table.

CLB to SPI buffer control High

Figure 8-61 CLB_SPI_DATA_CTRL_HI Register
15141312111098
RESERVEDSHIFT
R/W1C-0hR/W1C-0h
76543210
STRB_DELRESERVEDSTRB
R/W1C-0hR/W1C-0hR/W1C-0h
Table 8-62 CLB_SPI_DATA_CTRL_HI Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR/W1C0hReserved
12-8SHIFTR/W1C0hThis is a 5 bit value which denotes the first bit position of register R0 from which the Least Significant Bit of the output data should start.
00000 Output data is R0[15:0]
00001 Output data is R0[16:1]
00010 Output data is R0[17:2]
00011 Output data is R0[18:3]
...
...
10000 Output data is R0[31:16]

Reset type: SYSRSn

7STRB_DELR/W1C0h0 Selected strobe event goes directly to SPI module
1 Selected strobe event is delayed by 4 CLB clock cycles to SPI module
(This is done to facilitate use of STROBE as the same event to initiate a HLC task that can get the required data on to R0 for SPI data transfer before Strobe becomes valid at SPI block)

Reset type: SYSRSn

6-5RESERVEDR/W1C0hReserved
4-0STRBR/W1C0hThis is a 5 bit value which selects one of the HLC_EVENT inputs to be treated as the data_valid strobe

Reset type: SYSRSn