SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
Table 18-65 lists the memory-mapped registers for the ADC_REGS registers. All register offset addresses not listed in Table 18-65 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Write Protection | Section |
|---|---|---|---|---|
| 0h | ADCCTL1 | ADC Control 1 Register | EALLOW | Go |
| 1h | ADCCTL2 | ADC Control 2 Register | EALLOW | Go |
| 2h | ADCBURSTCTL | ADC Burst Control Register | EALLOW | Go |
| 3h | ADCINTFLG | ADC Interrupt Flag Register | Go | |
| 4h | ADCINTFLGCLR | ADC Interrupt Flag Clear Register | Go | |
| 5h | ADCINTOVF | ADC Interrupt Overflow Register | Go | |
| 6h | ADCINTOVFCLR | ADC Interrupt Overflow Clear Register | Go | |
| 7h | ADCINTSEL1N2 | ADC Interrupt 1 and 2 Selection Register | EALLOW | Go |
| 8h | ADCINTSEL3N4 | ADC Interrupt 3 and 4 Selection Register | EALLOW | Go |
| 9h | ADCSOCPRICTL | ADC SOC Priority Control Register | EALLOW | Go |
| Ah | ADCINTSOCSEL1 | ADC Interrupt SOC Selection 1 Register | EALLOW | Go |
| Bh | ADCINTSOCSEL2 | ADC Interrupt SOC Selection 2 Register | EALLOW | Go |
| Ch | ADCSOCFLG1 | ADC SOC Flag 1 Register | Go | |
| Dh | ADCSOCFRC1 | ADC SOC Force 1 Register | Go | |
| Eh | ADCSOCOVF1 | ADC SOC Overflow 1 Register | Go | |
| Fh | ADCSOCOVFCLR1 | ADC SOC Overflow Clear 1 Register | Go | |
| 10h | ADCSOC0CTL | ADC SOC0 Control Register | EALLOW | Go |
| 12h | ADCSOC1CTL | ADC SOC1 Control Register | EALLOW | Go |
| 14h | ADCSOC2CTL | ADC SOC2 Control Register | EALLOW | Go |
| 16h | ADCSOC3CTL | ADC SOC3 Control Register | EALLOW | Go |
| 18h | ADCSOC4CTL | ADC SOC4 Control Register | EALLOW | Go |
| 1Ah | ADCSOC5CTL | ADC SOC5 Control Register | EALLOW | Go |
| 1Ch | ADCSOC6CTL | ADC SOC6 Control Register | EALLOW | Go |
| 1Eh | ADCSOC7CTL | ADC SOC7 Control Register | EALLOW | Go |
| 20h | ADCSOC8CTL | ADC SOC8 Control Register | EALLOW | Go |
| 22h | ADCSOC9CTL | ADC SOC9 Control Register | EALLOW | Go |
| 24h | ADCSOC10CTL | ADC SOC10 Control Register | EALLOW | Go |
| 26h | ADCSOC11CTL | ADC SOC11 Control Register | EALLOW | Go |
| 28h | ADCSOC12CTL | ADC SOC12 Control Register | EALLOW | Go |
| 2Ah | ADCSOC13CTL | ADC SOC13 Control Register | EALLOW | Go |
| 2Ch | ADCSOC14CTL | ADC SOC14 Control Register | EALLOW | Go |
| 2Eh | ADCSOC15CTL | ADC SOC15 Control Register | EALLOW | Go |
| 30h | ADCEVTSTAT | ADC Event Status Register | Go | |
| 32h | ADCEVTCLR | ADC Event Clear Register | Go | |
| 34h | ADCEVTSEL | ADC Event Selection Register | EALLOW | Go |
| 36h | ADCEVTINTSEL | ADC Event Interrupt Selection Register | EALLOW | Go |
| 38h | ADCOSDETECT | ADC Open and Shorts Detect Register | EALLOW | Go |
| 39h | ADCCOUNTER | ADC Counter Register | Go | |
| 3Ah | ADCREV | ADC Revision Register | Go | |
| 3Bh | ADCOFFTRIM | ADC Offset Trim Register | EALLOW | Go |
| 3Ch | ADCOFFTRIM2 | ADC Offset Trim Register | EALLOW | Go |
| 3Dh | ADCOFFTRIM3 | ADC Offset Trim Register | EALLOW | Go |
| 40h | ADCPPB1CONFIG | ADC PPB1 Config Register | EALLOW | Go |
| 41h | ADCPPB1STAMP | ADC PPB1 Sample Delay Time Stamp Register | Go | |
| 42h | ADCPPB1OFFCAL | ADC PPB1 Offset Calibration Register | EALLOW | Go |
| 43h | ADCPPB1OFFREF | ADC PPB1 Offset Reference Register | Go | |
| 44h | ADCPPB1TRIPHI | ADC PPB1 Trip High Register | EALLOW | Go |
| 46h | ADCPPB1TRIPLO | ADC PPB1 Trip Low/Trigger Time Stamp Register | EALLOW | Go |
| 48h | ADCPPB2CONFIG | ADC PPB2 Config Register | EALLOW | Go |
| 49h | ADCPPB2STAMP | ADC PPB2 Sample Delay Time Stamp Register | Go | |
| 4Ah | ADCPPB2OFFCAL | ADC PPB2 Offset Calibration Register | EALLOW | Go |
| 4Bh | ADCPPB2OFFREF | ADC PPB2 Offset Reference Register | Go | |
| 4Ch | ADCPPB2TRIPHI | ADC PPB2 Trip High Register | EALLOW | Go |
| 4Eh | ADCPPB2TRIPLO | ADC PPB2 Trip Low/Trigger Time Stamp Register | EALLOW | Go |
| 50h | ADCPPB3CONFIG | ADC PPB3 Config Register | EALLOW | Go |
| 51h | ADCPPB3STAMP | ADC PPB3 Sample Delay Time Stamp Register | Go | |
| 52h | ADCPPB3OFFCAL | ADC PPB3 Offset Calibration Register | EALLOW | Go |
| 53h | ADCPPB3OFFREF | ADC PPB3 Offset Reference Register | Go | |
| 54h | ADCPPB3TRIPHI | ADC PPB3 Trip High Register | EALLOW | Go |
| 56h | ADCPPB3TRIPLO | ADC PPB3 Trip Low/Trigger Time Stamp Register | EALLOW | Go |
| 58h | ADCPPB4CONFIG | ADC PPB4 Config Register | EALLOW | Go |
| 59h | ADCPPB4STAMP | ADC PPB4 Sample Delay Time Stamp Register | Go | |
| 5Ah | ADCPPB4OFFCAL | ADC PPB4 Offset Calibration Register | EALLOW | Go |
| 5Bh | ADCPPB4OFFREF | ADC PPB4 Offset Reference Register | Go | |
| 5Ch | ADCPPB4TRIPHI | ADC PPB4 Trip High Register | EALLOW | Go |
| 5Eh | ADCPPB4TRIPLO | ADC PPB4 Trip Low/Trigger Time Stamp Register | EALLOW | Go |
| 60h | ADCSAFECHECKRESEN | ADC Safe Check Result Enable Register | Go | |
| 6Fh | ADCINTCYCLE | ADC Early Interrupt Generation Cycle | EALLOW | Go |
| 70h | ADCINLTRIM1 | ADC Linearity Trim 1 Register | EALLOW | Go |
| 72h | ADCINLTRIM2 | ADC Linearity Trim 2 Register | EALLOW | Go |
| 74h | ADCINLTRIM3 | ADC Linearity Trim 3 Register | EALLOW | Go |
| 76h | ADCINLTRIM4 | ADC Linearity Trim 4 Register | EALLOW | Go |
| 78h | ADCINLTRIM5 | ADC Linearity Trim 5 Register | EALLOW | Go |
| 7Ah | ADCINLTRIM6 | ADC Linearity Trim 6 Register | EALLOW | Go |
| 7Dh | ADCREV2 | ADC Wrapper Revision Register | Go | |
| 80h | REP1CTL | ADC Trigger Repeater 1 Control Register | EALLOW | Go |
| 82h | REP1N | ADC Trigger Repeater 1 N Select Register | EALLOW | Go |
| 84h | REP1PHASE | ADC Trigger Repeater 1 Phase Select Register | EALLOW | Go |
| 86h | REP1SPREAD | ADC Trigger Repeater 1 Spread Select Register | EALLOW | Go |
| 88h | REP1FRC | ADC Trigger Repeater 1 Software Force Register | EALLOW | Go |
| 90h | REP2CTL | ADC Trigger Repeater 2 Control Register | EALLOW | Go |
| 92h | REP2N | ADC Trigger Repeater 2 N Select Register | EALLOW | Go |
| 94h | REP2PHASE | ADC Trigger Repeater 2 Phase Select Register | EALLOW | Go |
| 96h | REP2SPREAD | ADC Trigger Repeater 2 Spread Select Register | EALLOW | Go |
| 98h | REP2FRC | ADC Trigger Repeater 2 Software Force Register | EALLOW | Go |
| A0h | ADCPPB1LIMIT | ADC PPB1Conversion Count Limit Register | EALLOW | Go |
| A2h | ADCPPBP1PCOUNT | ADC PPB1 Partial Conversion Count Register | Go | |
| A4h | ADCPPB1CONFIG2 | ADC PPB1 Sum Shift Register | Go | |
| A6h | ADCPPB1PSUM | ADC PPB1 Partial Sum Register | Go | |
| A8h | ADCPPB1PMAX | ADC PPB1 Partial Max Register | Go | |
| AAh | ADCPPB1PMAXI | ADC PPB1 Partial Max Index Register | Go | |
| ACh | ADCPPB1PMIN | ADC PPB1 Partial MIN Register | Go | |
| AEh | ADCPPB1PMINI | ADC PPB1 Partial Min Index Register | Go | |
| B0h | ADCPPB1TRIPLO2 | ADC PPB1 Extended Trip Low Register | Go | |
| BAh | ADCPPB2LIMIT | ADC PPB2Conversion Count Limit Register | EALLOW | Go |
| BCh | ADCPPBP2PCOUNT | ADC PPB2 Partial Conversion Count Register | Go | |
| BEh | ADCPPB2CONFIG2 | ADC PPB2 Sum Shift Register | Go | |
| C0h | ADCPPB2PSUM | ADC PPB2 Partial Sum Register | Go | |
| C2h | ADCPPB2PMAX | ADC PPB2 Partial Max Register | Go | |
| C4h | ADCPPB2PMAXI | ADC PPB2 Partial Max Index Register | Go | |
| C6h | ADCPPB2PMIN | ADC PPB2 Partial MIN Register | Go | |
| C8h | ADCPPB2PMINI | ADC PPB2 Partial Min Index Register | Go | |
| CAh | ADCPPB2TRIPLO2 | ADC PPB2 Extended Trip Low Register | Go | |
| D4h | ADCPPB3LIMIT | ADC PPB3Conversion Count Limit Register | EALLOW | Go |
| D6h | ADCPPBP3PCOUNT | ADC PPB3 Partial Conversion Count Register | Go | |
| D8h | ADCPPB3CONFIG2 | ADC PPB3 Sum Shift Register | Go | |
| DAh | ADCPPB3PSUM | ADC PPB3 Partial Sum Register | Go | |
| DCh | ADCPPB3PMAX | ADC PPB3 Partial Max Register | Go | |
| DEh | ADCPPB3PMAXI | ADC PPB3 Partial Max Index Register | Go | |
| E0h | ADCPPB3PMIN | ADC PPB3 Partial MIN Register | Go | |
| E2h | ADCPPB3PMINI | ADC PPB3 Partial Min Index Register | Go | |
| E4h | ADCPPB3TRIPLO2 | ADC PPB3 Extended Trip Low Register | Go | |
| EEh | ADCPPB4LIMIT | ADC PPB4Conversion Count Limit Register | EALLOW | Go |
| F0h | ADCPPBP4PCOUNT | ADC PPB4 Partial Conversion Count Register | Go | |
| F2h | ADCPPB4CONFIG2 | ADC PPB4 Sum Shift Register | Go | |
| F4h | ADCPPB4PSUM | ADC PPB4 Partial Sum Register | Go | |
| F6h | ADCPPB4PMAX | ADC PPB4 Partial Max Register | Go | |
| F8h | ADCPPB4PMAXI | ADC PPB4 Partial Max Index Register | Go | |
| FAh | ADCPPB4PMIN | ADC PPB4 Partial MIN Register | Go | |
| FCh | ADCPPB4PMINI | ADC PPB4 Partial Min Index Register | Go | |
| FEh | ADCPPB4TRIPLO2 | ADC PPB4 Extended Trip Low Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 18-66 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| R-0 | R -0 | Read Returns 0s |
| Write Type | ||
| W | W | Write |
| W1C | W 1C | Write 1 to clear |
| W1S | W 1S | Write 1 to set |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
| Register Array Variables | ||
| i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
| y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. | |
ADCCTL1 is shown in Figure 18-89 and described in Table 18-67.
Return to the Summary Table.
ADC Control 1 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TDMAEN | EXTMUXPRESELECTEN | ADCBSY | RESERVED | ADCBSYCHN | |||
| R/W-0h | R/W-0h | R-0h | R-0h | R-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADCPWDNZ | RESERVED | INTPULSEPOS | RESERVED | ||||
| R/W-0h | R-0h | R/W-0h | R-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | TDMAEN | R/W | 0h | Enable Alternate DMA Timings. This bit controls when the DMA is triggered. 0 DMA is triggered at the same time as the CPU interrupt 1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt mode Reset type: SYSRSn |
| 14 | EXTMUXPRESELECTEN | R/W | 0h | If th the ADC SOC sequence is deterministic, the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the external mux settling time to be pipelined with the previous conversion's conversion time. However, this will not work in the case where high-priority SOCs can arrive asynchronously. 0 ADCEXTMUX pins only change at beginning of S+H window 1 ADCEXTMUX pins are set after the end of S+H window based on pending SOCs Reset type: SYSRSn |
| 13 | ADCBSY | R | 0h | ADC Busy. Set when ADC SOC is generated, cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy and cannot sample another channel Reset type: SYSRSn |
| 12 | RESERVED | R | 0h | Reserved |
| 11-8 | ADCBSYCHN | R | 0h | ADC Busy Channel. Set when an ADC Start of Conversion (SOC) is generated. When ADCBSY=0: holds the value of the last converted SOC When ADCBSY=1: reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted 1h SOC1 is currently processing or was last SOC converted 2h SOC2 is currently processing or was last SOC converted 3h SOC3 is currently processing or was last SOC converted 4h SOC4 is currently processing or was last SOC converted 5h SOC5 is currently processing or was last SOC converted 6h SOC6 is currently processing or was last SOC converted 7h SOC7 is currently processing or was last SOC converted 8h SOC8 is currently processing or was last SOC converted 9h SOC9 is currently processing or was last SOC converted Ah SOC10 is currently processing or was last SOC converted Bh SOC11 is currently processing or was last SOC converted Ch SOC12 is currently processing or was last SOC converted Dh SOC13 is currently processing or was last SOC converted Eh SOC14 is currently processing or was last SOC converted Fh SOC15 is currently processing or was last SOC converted Reset type: SYSRSn |
| 7 | ADCPWDNZ | R/W | 0h | ADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up Reset type: SYSRSn |
| 6-3 | RESERVED | R | 0h | Reserved |
| 2 | INTPULSEPOS | R/W | 0h | ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion (at the end of the acquisition window) plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse generation occurs at the end of the conversion, 1 cycle prior to the ADC result latching into its result register Reset type: SYSRSn |
| 1-0 | RESERVED | R | 0h | Reserved |
ADCCTL2 is shown in Figure 18-90 and described in Table 18-68.
Return to the Summary Table.
ADC Control 2 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | OFFTRIMMODE | |||||
| R-0h | R-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGNALMODE | RESOLUTION | RESERVED | PRESCALE | ||||
| R/W-0h | R/W-0h | R-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12-9 | RESERVED | R | 0h | Reserved |
| 8 | OFFTRIMMODE | R/W | 0h | ADC offset trim mode. 0 = Offset trim supplied by ADCOFFTRIM.OFFTRIM regardless of resolution or signal mode 1 = Offset trim for each combination of resolution, signalmode, and even or odd is supplied by a different field in ADCOFFTRIM, ADCOFFTRIM2, or ADCOFFTRIM3 Reset type: SYSRSn |
| 7 | SIGNALMODE | R/W | 0h | SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential Reset type: SYSRSn |
| 6 | RESOLUTION | R/W | 0h | SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution 1 16-bit resolution Reset type: SYSRSn |
| 5-4 | RESERVED | R | 0h | Reserved |
| 3-0 | PRESCALE | R/W | 0h | ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK = Input Clock / 4.5 1000 ADCCLK = Input Clock / 5.0 1001 ADCCLK = Input Clock / 5.5 1010 ADCCLK = Input Clock / 6.0 1011 ADCCLK = Input Clock / 6.5 1100 ADCCLK = Input Clock / 7.0 1101 ADCCLK = Input Clock / 7.5 1110 ADCCLK = Input Clock / 8.0 1111 ADCCLK = Input Clock / 8.5 Reset type: SYSRSn |
ADCBURSTCTL is shown in Figure 18-91 and described in Table 18-69.
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ADC Burst Control Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| BURSTEN | RESERVED | BURSTSIZE | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BURSTTRIGSEL | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | BURSTEN | R/W | 0h | SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled. Reset type: SYSRSn |
| 14-12 | RESERVED | R | 0h | Reserved |
| 11-8 | BURSTSIZE | R/W | 0h | SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer, which is advanced as each SOC is converted. 0h 1 SOC converted 1h 2 SOCs converted 2h 3 SOCs converted 3h 4 SOCs converted 4h 5 SOCs converted 5h 6 SOCs converted 6h 7 SOCs converted 7h 8 SOCs converted 8h 9 SOCs converted 9h 10 SOCs converted Ah 11 SOCs converted Bh 12 SOCs converted Ch 13 SOCs converted Dh 14 SOCs converted Eh 15 SOCs converted Fh 16 SOCs converted Note: If the burst causes SOCs to be set for conversion that were already pending, the corresponding bits in the ADCSOCOVF register will be set. Reset type: SYSRSn |
| 7 | RESERVED | R | 0h | Reserved |
| 6-0 | BURSTTRIGSEL | R/W | 0h | SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h BURSTTRIG0 - Software only 01h BURSTTRIG1 - CPU1 Timer 0, TINT0n 02h BURSTTRIG2 - CPU1 Timer 1, TINT1n 03h BURSTTRIG3 - CPU1 Timer 2, TINT2n 04h BURSTTRIG4 - GPIO, Input X-Bar INPUT5 05h BURSTTRIG5 - ePWM1, ADCSOCA 06h BURSTTRIG6 - ePWM1, ADCSOCB 07h BURSTTRIG7 - ePWM2, ADCSOCA 08h BURSTTRIG8 - ePWM2, ADCSOCB 09h BURSTTRIG9 - ePWM3, ADCSOCA 0Ah BURSTTRIG10 - ePWM3, ADCSOCB 0Bh BURSTTRIG11 - ePWM4, ADCSOCA 0Ch BURSTTRIG12 - ePWM4, ADCSOCB 0Dh BURSTTRIG13 - ePWM5, ADCSOCA 0Eh BURSTTRIG14 - ePWM5, ADCSOCB 0Fh BURSTTRIG15 - ePWM6, ADCSOCA 10h BURSTTRIG16 - ePWM6, ADCSOCB 11h BURSTTRIG17 - ePWM7, ADCSOCA 12h BURSTTRIG18 - ePWM7, ADCSOCB 13h BURSTTRIG19 - ePWM8, ADCSOCA 14h BURSTTRIG20 - ePWM8, ADCSOCB 15h BURSTTRIG21 - ePWM9, ADCSOCA 16h BURSTTRIG22 - ePWM9, ADCSOCB 17h BURSTTRIG23 - ePWM10, ADCSOCA 18h BURSTTRIG24 - ePWM10, ADCSOCB 19h BURSTTRIG25 - ePWM11, ADCSOCA 1Ah BURSTTRIG26 - ePWM11, ADCSOCB 1Bh BURSTTRIG27 - ePWM12, ADCSOCA 1Ch BURSTTRIG28 - ePWM12, ADCSOCB 1Dh BURSTTRIG29 - CPU2 Timer 0, TINT0n 1Eh BURSTTRIG30 - CPU2 Timer 1, TINT1n 1Fh BURSTTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h BURSTTRIG40 - REP1TRIG 29h BURSTTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h BURSTTRIG80 eCAP1 51h BURSTTRIG81 eCAP2 52h BURSTTRIG82 eCAP3 53h BURSTTRIG83 eCAP4 54h BURSTTRIG84 eCAP5 55h BURSTTRIG85 eCAP6 56h BURSTTRIG86 eCAP7 57h BURSTTRIG87 eCAP8 58h BURSTTRIG88 - ePWM13, ADCSOCA 59h BURSTTRIG89 - ePWM13, ADCSOCB 5Ah BURSTTRIG90 - ePWM14, ADCSOCA 5Bh BURSTTRIG91 - ePWM14, ADCSOCB 5Ch BURSTTRIG92 - ePWM15, ADCSOCA 5Dh BURSTTRIG93 - ePWM15, ADCSOCB 5Eh BURSTTRIG94 - ePWM16, ADCSOCA 5Fh BURSTTRIG95 - ePWM16, ADCSOCB 60h BURSTTRIG96 - ePWM17, ADCSOCA 61h BURSTTRIG97 - ePWM17, ADCSOCB 62h BURSTTRIG98 - ePWM18, ADCSOCA 63h BURSTTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
ADCINTFLG is shown in Figure 18-92 and described in Table 18-70.
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ADC Interrupt Flag Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADCINT4RESULT | ADCINT3RESULT | ADCINT2RESULT | ADCINT1RESULT | ADCINT4 | ADCINT3 | ADCINT2 | ADCINT1 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0h | Reserved |
| 7 | ADCINT4RESULT | R | 0h | ADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT4 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE. In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn |
| 6 | ADCINT3RESULT | R | 0h | ADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT3 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE. In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn |
| 5 | ADCINT2RESULT | R | 0h | ADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT2 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE. In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn |
| 4 | ADCINT1RESULT | R | 0h | ADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register. This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT1 flag. In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE. In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch. Reset type: SYSRSn |
| 3 | ADCINT4 | R | 0h | ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn |
| 2 | ADCINT3 | R | 0h | ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn |
| 1 | ADCINT2 | R | 0h | ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn |
| 0 | ADCINT1 | R | 0h | ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register. Reset type: SYSRSn |
ADCINTFLGCLR is shown in Figure 18-93 and described in Table 18-71.
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ADC Interrupt Flag Clear Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ADCINT4 | ADCINT3 | ADCINT2 | ADCINT1 | |||
| R-0h | R-0/W1C-0h | R-0/W1C-0h | R-0/W1C-0h | R-0/W1C-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3 | ADCINT4 | R-0/W1C | 0h | ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT4 and ADCINT4RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn |
| 2 | ADCINT3 | R-0/W1C | 0h | ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT3 and ADCINT3RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn |
| 1 | ADCINT2 | R-0/W1C | 0h | ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT2 and ADCINT2RESULT flags in the ADCINTFLG register. . If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn |
| 0 | ADCINT1 | R-0/W1C | 0h | ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT1 and ADCINT1RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn |
ADCINTOVF is shown in Figure 18-94 and described in Table 18-72.
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ADC Interrupt Overflow Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ADCINT4 | ADCINT3 | ADCINT2 | ADCINT1 | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3 | ADCINT4 | R | 0h | ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn |
| 2 | ADCINT3 | R | 0h | ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn |
| 1 | ADCINT2 | R | 0h | ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn |
| 0 | ADCINT1 | R | 0h | ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection. Reset type: SYSRSn |
ADCINTOVFCLR is shown in Figure 18-95 and described in Table 18-73.
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ADC Interrupt Overflow Clear Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ADCINT4 | ADCINT3 | ADCINT2 | ADCINT1 | |||
| R-0h | R-0/W1C-0h | R-0/W1C-0h | R-0/W1C-0h | R-0/W1C-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3 | ADCINT4 | R-0/W1C | 0h | ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn |
| 2 | ADCINT3 | R-0/W1C | 0h | ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn |
| 1 | ADCINT2 | R-0/W1C | 0h | ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn |
| 0 | ADCINT1 | R-0/W1C | 0h | ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. Reset type: SYSRSn |
ADCINTSEL1N2 is shown in Figure 18-96 and described in Table 18-74.
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ADC Interrupt 1 and 2 Selection Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | INT2CONT | INT2E | INT2SEL | ||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | INT1CONT | INT1E | INT1SEL | ||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14 | INT2CONT | R/W | 0h | ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn |
| 13 | INT2E | R/W | 0h | ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled Reset type: SYSRSn |
| 12-8 | INT2SEL | R/W | 0h | ADCINT2 EOC Source Select 00h EOC0 is trigger for ADCINT2 01h EOC1 is trigger for ADCINT2 02h EOC2 is trigger for ADCINT2 03h EOC3 is trigger for ADCINT2 04h EOC4 is trigger for ADCINT2 05h EOC5 is trigger for ADCINT2 06h EOC6 is trigger for ADCINT2 07h EOC7 is trigger for ADCINT2 08h EOC8 is trigger for ADCINT2 09h EOC9 is trigger for ADCINT2 0Ah EOC10 is trigger for ADCINT2 0Bh EOC11 is trigger for ADCINT2 0Ch EOC12 is trigger for ADCINT2 0Dh EOC13 is trigger for ADCINT2 0Eh EOC14 is trigger for ADCINT2 0Fh EOC15 is trigger for ADCINT2 10h OSINT1 is trigger for ADCINT2 11h OSINT2 is trigger for ADCINT2 12h OSINT3 is trigger for ADCINT2 13h OSINT4 is trigger for ADCINT2 Reset type: SYSRSn |
| 7 | RESERVED | R | 0h | Reserved |
| 6 | INT1CONT | R/W | 0h | ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn |
| 5 | INT1E | R/W | 0h | ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled Reset type: SYSRSn |
| 4-0 | INT1SEL | R/W | 0h | ADCINT1 EOC Source Select 00h EOC0 is trigger for ADCINT1 01h EOC1 is trigger for ADCINT1 02h EOC2 is trigger for ADCINT1 03h EOC3 is trigger for ADCINT1 04h EOC4 is trigger for ADCINT1 05h EOC5 is trigger for ADCINT1 06h EOC6 is trigger for ADCINT1 07h EOC7 is trigger for ADCINT1 08h EOC8 is trigger for ADCINT1 09h EOC9 is trigger for ADCINT1 0Ah EOC10 is trigger for ADCINT1 0Bh EOC11 is trigger for ADCINT1 0Ch EOC12 is trigger for ADCINT1 0Dh EOC13 is trigger for ADCINT1 0Eh EOC14 is trigger for ADCINT1 0Fh EOC15 is trigger for ADCINT1 10h OSINT1 is trigger for ADCINT1 11h OSINT2 is trigger for ADCINT1 12h OSINT3 is trigger for ADCINT1 13h OSINT4 is trigger for ADCINT1 Reset type: SYSRSn |
ADCINTSEL3N4 is shown in Figure 18-97 and described in Table 18-75.
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ADC Interrupt 3 and 4 Selection Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | INT4CONT | INT4E | INT4SEL | ||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | INT3CONT | INT3E | INT3SEL | ||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14 | INT4CONT | R/W | 0h | ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn |
| 13 | INT4E | R/W | 0h | ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled Reset type: SYSRSn |
| 12-8 | INT4SEL | R/W | 0h | ADCINT4 EOC Source Select 00h EOC0 is trigger for ADCINT4 01h EOC1 is trigger for ADCINT4 02h EOC2 is trigger for ADCINT4 03h EOC3 is trigger for ADCINT4 04h EOC4 is trigger for ADCINT4 05h EOC5 is trigger for ADCINT4 06h EOC6 is trigger for ADCINT4 07h EOC7 is trigger for ADCINT4 08h EOC8 is trigger for ADCINT4 09h EOC9 is trigger for ADCINT4 0Ah EOC10 is trigger for ADCINT4 0Bh EOC11 is trigger for ADCINT4 0Ch EOC12 is trigger for ADCINT4 0Dh EOC13 is trigger for ADCINT4 0Eh EOC14 is trigger for ADCINT4 0Fh EOC15 is trigger for ADCINT4 10h OSINT1 is trigger for ADCINT4 11h OSINT2 is trigger for ADCINT4 12h OSINT3 is trigger for ADCINT4 13h OSINT4 is trigger for ADCINT4 Reset type: SYSRSn |
| 7 | RESERVED | R | 0h | Reserved |
| 6 | INT3CONT | R/W | 0h | ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not. Reset type: SYSRSn |
| 5 | INT3E | R/W | 0h | ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled Reset type: SYSRSn |
| 4-0 | INT3SEL | R/W | 0h | ADCINT3 EOC Source Select 00h EOC0 is trigger for ADCINT3 01h EOC1 is trigger for ADCINT3 02h EOC2 is trigger for ADCINT3 03h EOC3 is trigger for ADCINT3 04h EOC4 is trigger for ADCINT3 05h EOC5 is trigger for ADCINT3 06h EOC6 is trigger for ADCINT3 07h EOC7 is trigger for ADCINT3 08h EOC8 is trigger for ADCINT3 09h EOC9 is trigger for ADCINT3 0Ah EOC10 is trigger for ADCINT3 0Bh EOC11 is trigger for ADCINT3 0Ch EOC12 is trigger for ADCINT3 0Dh EOC13 is trigger for ADCINT3 0Eh EOC14 is trigger for ADCINT3 0Fh EOC15 is trigger for ADCINT3 10h OSINT1 is trigger for ADCINT3 11h OSINT2 is trigger for ADCINT3 12h OSINT3 is trigger for ADCINT3 13h OSINT4 is trigger for ADCINT3 Reset type: SYSRSn |
ADCSOCPRICTL is shown in Figure 18-98 and described in Table 18-76.
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ADC SOC Priority Control Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RRPOINTER | ||||||
| R-0h | R-10h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RRPOINTER | SOCPRIORITY | ||||||
| R-10h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-5 | RRPOINTER | R | 10h | Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert, SOC1 is highest round robin priority. 01h SOC1 was last round robin SOC to convert, SOC2 is highest round robin priority. 02h SOC2 was last round robin SOC to convert, SOC3 is highest round robin priority. 03h SOC3 was last round robin SOC to convert, SOC4 is highest round robin priority. 04h SOC4 was last round robin SOC to convert, SOC5 is highest round robin priority. 05h SOC5 was last round robin SOC to convert, SOC6 is highest round robin priority. 06h SOC6 was last round robin SOC to convert, SOC7 is highest round robin priority. 07h SOC7 was last round robin SOC to convert, SOC8 is highest round robin priority. 08h SOC8 was last round robin SOC to convert, SOC9 is highest round robin priority. 09h SOC9 was last round robin SOC to convert, SOC10 is highest round robin priority. 0Ah SOC10 was last round robin SOC to convert, SOC11 is highest round robin priority. 0Bh SOC11 was last round robin SOC to convert, SOC12 is highest round robin priority. 0Ch SOC12 was last round robin SOC to convert, SOC13 is highest round robin priority. 0Dh SOC13 was last round robin SOC to convert, SOC14 is highest round robin priority. 0Eh SOC14 was last round robin SOC to convert, SOC15 is highest round robin priority. 0Fh SOC15 was last round robin SOC to convert, SOC0 is highest round robin priority. 10h Reset value to indicate no SOC has been converted. SOC0 is highest round robin priority. Set to this value when the ADC module is reset by SOFTPRES or when the ADCSOCPRICTL register is written. In the latter case, if a conversion is currently in progress, it will complete and then the new priority will take effect. Others Invalid value. Reset type: SYSRSn |
| 4-0 | SOCPRIORITY | R/W | 0h | SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority, rest of channels are in round robin mode. 02h SOC0-SOC1 are high priority, SOC2-SOC15 are in round robin mode. 03h SOC0-SOC2 are high priority, SOC3-SOC15 are in round robin mode. 04h SOC0-SOC3 are high priority, SOC4-SOC15 are in round robin mode. 05h SOC0-SOC4 are high priority, SOC5-SOC15 are in round robin mode. 06h SOC0-SOC5 are high priority, SOC6-SOC15 are in round robin mode. 07h SOC0-SOC6 are high priority, SOC7-SOC15 are in round robin mode. 08h SOC0-SOC7 are high priority, SOC8-SOC15 are in round robin mode. 09h SOC0-SOC8 are high priority, SOC9-SOC15 are in round robin mode. 0Ah SOC0-SOC9 are high priority, SOC10-SOC15 are in round robin mode. 0Bh SOC0-SOC10 are high priority, SOC11-SOC15 are in round robin mode. 0Ch SOC0-SOC11 are high priority, SOC12-SOC15 are in round robin mode. 0Dh SOC0-SOC12 are high priority, SOC13-SOC15 are in round robin mode. 0Eh SOC0-SOC13 are high priority, SOC14-SOC15 are in round robin mode. 0Fh SOC0-SOC14 are high priority, SOC15 is in round robin mode. 10h All SOCs are in high priority mode, arbitrated by SOC number. Others Invalid selection. Reset type: SYSRSn |
ADCINTSOCSEL1 is shown in Figure 18-99 and described in Table 18-77.
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ADC Interrupt SOC Selection 1 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SOC7 | SOC6 | SOC5 | SOC4 | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SOC3 | SOC2 | SOC1 | SOC0 | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | SOC7 | R/W | 0h | SOC7 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC7. 10 ADCINT2 will trigger SOC7. 11 Invalid selection. Reset type: SYSRSn |
| 13-12 | SOC6 | R/W | 0h | SOC6 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC6. 10 ADCINT2 will trigger SOC6. 11 Invalid selection. Reset type: SYSRSn |
| 11-10 | SOC5 | R/W | 0h | SOC5 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC5. 10 ADCINT2 will trigger SOC5. 11 Invalid selection. Reset type: SYSRSn |
| 9-8 | SOC4 | R/W | 0h | SOC4 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC4. 10 ADCINT2 will trigger SOC4. 11 Invalid selection. Reset type: SYSRSn |
| 7-6 | SOC3 | R/W | 0h | SOC3 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC3. 10 ADCINT2 will trigger SOC3. 11 Invalid selection. Reset type: SYSRSn |
| 5-4 | SOC2 | R/W | 0h | SOC2 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC2. 10 ADCINT2 will trigger SOC2. 11 Invalid selection. Reset type: SYSRSn |
| 3-2 | SOC1 | R/W | 0h | SOC1 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC1. 10 ADCINT2 will trigger SOC1. 11 Invalid selection. Reset type: SYSRSn |
| 1-0 | SOC0 | R/W | 0h | SOC0 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC0. 10 ADCINT2 will trigger SOC0. 11 Invalid selection. Reset type: SYSRSn |
ADCINTSOCSEL2 is shown in Figure 18-100 and described in Table 18-78.
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ADC Interrupt SOC Selection 2 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SOC15 | SOC14 | SOC13 | SOC12 | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SOC11 | SOC10 | SOC9 | SOC8 | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | SOC15 | R/W | 0h | SOC15 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC15. 10 ADCINT2 will trigger SOC15. 11 Invalid selection. Reset type: SYSRSn |
| 13-12 | SOC14 | R/W | 0h | SOC14 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC14. 10 ADCINT2 will trigger SOC14. 11 Invalid selection. Reset type: SYSRSn |
| 11-10 | SOC13 | R/W | 0h | SOC13 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC13. 10 ADCINT2 will trigger SOC13. 11 Invalid selection. Reset type: SYSRSn |
| 9-8 | SOC12 | R/W | 0h | SOC12 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC12. 10 ADCINT2 will trigger SOC12. 11 Invalid selection. Reset type: SYSRSn |
| 7-6 | SOC11 | R/W | 0h | SOC11 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC11. 10 ADCINT2 will trigger SOC11. 11 Invalid selection. Reset type: SYSRSn |
| 5-4 | SOC10 | R/W | 0h | SOC10 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC10. 10 ADCINT2 will trigger SOC10. 11 Invalid selection. Reset type: SYSRSn |
| 3-2 | SOC9 | R/W | 0h | SOC9 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC9. 10 ADCINT2 will trigger SOC9. 11 Invalid selection. Reset type: SYSRSn |
| 1-0 | SOC8 | R/W | 0h | SOC8 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0 trigger. 01 ADCINT1 will trigger SOC8. 10 ADCINT2 will trigger SOC8. 11 Invalid selection. Reset type: SYSRSn |
ADCSOCFLG1 is shown in Figure 18-101 and described in Table 18-79.
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ADC SOC Flag 1 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SOC15 | SOC14 | SOC13 | SOC12 | SOC11 | SOC10 | SOC9 | SOC8 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SOC7 | SOC6 | SOC5 | SOC4 | SOC3 | SOC2 | SOC1 | SOC0 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | SOC15 | R | 0h | SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 14 | SOC14 | R | 0h | SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 13 | SOC13 | R | 0h | SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 12 | SOC12 | R | 0h | SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 11 | SOC11 | R | 0h | SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 10 | SOC10 | R | 0h | SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 9 | SOC9 | R | 0h | SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 8 | SOC8 | R | 0h | SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 7 | SOC7 | R | 0h | SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 6 | SOC6 | R | 0h | SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 5 | SOC5 | R | 0h | SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 4 | SOC4 | R | 0h | SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 3 | SOC3 | R | 0h | SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 2 | SOC2 | R | 0h | SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 1 | SOC1 | R | 0h | SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
| 0 | SOC0 | R | 0h | SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. Reset type: SYSRSn |
ADCSOCFRC1 is shown in Figure 18-102 and described in Table 18-80.
Return to the Summary Table.
ADC SOC Force 1 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SOC15 | SOC14 | SOC13 | SOC12 | SOC11 | SOC10 | SOC9 | SOC8 |
| R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SOC7 | SOC6 | SOC5 | SOC4 | SOC3 | SOC2 | SOC1 | SOC0 |
| R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | SOC15 | R-0/W1S | 0h | SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC15 flag bit to 1. This will cause a conversion to start once priority is given to SOC15. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC15 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 14 | SOC14 | R-0/W1S | 0h | SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC14 flag bit to 1. This will cause a conversion to start once priority is given to SOC14. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC14 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 13 | SOC13 | R-0/W1S | 0h | SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC13 flag bit to 1. This will cause a conversion to start once priority is given to SOC13. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC13 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 12 | SOC12 | R-0/W1S | 0h | SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC12 flag bit to 1. This will cause a conversion to start once priority is given to SOC12. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC12 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 11 | SOC11 | R-0/W1S | 0h | SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC11 flag bit to 1. This will cause a conversion to start once priority is given to SOC11. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC11 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 10 | SOC10 | R-0/W1S | 0h | SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC10 flag bit to 1. This will cause a conversion to start once priority is given to SOC10. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC10 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 9 | SOC9 | R-0/W1S | 0h | SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC9 flag bit to 1. This will cause a conversion to start once priority is given to SOC9. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC9 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 8 | SOC8 | R-0/W1S | 0h | SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC8 flag bit to 1. This will cause a conversion to start once priority is given to SOC8. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC8 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 7 | SOC7 | R-0/W1S | 0h | SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC7 flag bit to 1. This will cause a conversion to start once priority is given to SOC7. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC7 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 6 | SOC6 | R-0/W1S | 0h | SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC6 flag bit to 1. This will cause a conversion to start once priority is given to SOC6. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC6 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 5 | SOC5 | R-0/W1S | 0h | SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC5 flag bit to 1. This will cause a conversion to start once priority is given to SOC5. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC5 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 4 | SOC4 | R-0/W1S | 0h | SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC4 flag bit to 1. This will cause a conversion to start once priority is given to SOC4. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC4 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 3 | SOC3 | R-0/W1S | 0h | SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC3 flag bit to 1. This will cause a conversion to start once priority is given to SOC3. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC3 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 2 | SOC2 | R-0/W1S | 0h | SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC2 flag bit to 1. This will cause a conversion to start once priority is given to SOC2. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC2 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 1 | SOC1 | R-0/W1S | 0h | SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC1 flag bit to 1. This will cause a conversion to start once priority is given to SOC1. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC1 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
| 0 | SOC0 | R-0/W1S | 0h | SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1 Force SOC0 flag bit to 1. This will cause a conversion to start once priority is given to SOC0. If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC0 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. Reset type: SYSRSn |
ADCSOCOVF1 is shown in Figure 18-103 and described in Table 18-81.
Return to the Summary Table.
ADC SOC Overflow 1 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SOC15 | SOC14 | SOC13 | SOC12 | SOC11 | SOC10 | SOC9 | SOC8 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SOC7 | SOC6 | SOC5 | SOC4 | SOC3 | SOC2 | SOC1 | SOC0 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | SOC15 | R | 0h | SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 14 | SOC14 | R | 0h | SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 13 | SOC13 | R | 0h | SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 12 | SOC12 | R | 0h | SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 11 | SOC11 | R | 0h | SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 10 | SOC10 | R | 0h | SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 9 | SOC9 | R | 0h | SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 8 | SOC8 | R | 0h | SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 7 | SOC7 | R | 0h | SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 6 | SOC6 | R | 0h | SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 5 | SOC5 | R | 0h | SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 4 | SOC4 | R | 0h | SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 3 | SOC3 | R | 0h | SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 2 | SOC2 | R | 0h | SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 1 | SOC1 | R | 0h | SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
| 0 | SOC0 | R | 0h | SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit. Reset type: SYSRSn |
ADCSOCOVFCLR1 is shown in Figure 18-104 and described in Table 18-82.
Return to the Summary Table.
ADC SOC Overflow Clear 1 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SOC15 | SOC14 | SOC13 | SOC12 | SOC11 | SOC10 | SOC9 | SOC8 |
| R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SOC7 | SOC6 | SOC5 | SOC4 | SOC3 | SOC2 | SOC1 | SOC0 |
| R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | SOC15 | R-0/W1S | 0h | SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 14 | SOC14 | R-0/W1S | 0h | SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 13 | SOC13 | R-0/W1S | 0h | SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 12 | SOC12 | R-0/W1S | 0h | SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 11 | SOC11 | R-0/W1S | 0h | SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 10 | SOC10 | R-0/W1S | 0h | SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 9 | SOC9 | R-0/W1S | 0h | SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 8 | SOC8 | R-0/W1S | 0h | SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 7 | SOC7 | R-0/W1S | 0h | SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 6 | SOC6 | R-0/W1S | 0h | SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 5 | SOC5 | R-0/W1S | 0h | SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 4 | SOC4 | R-0/W1S | 0h | SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 3 | SOC3 | R-0/W1S | 0h | SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 2 | SOC2 | R-0/W1S | 0h | SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 1 | SOC1 | R-0/W1S | 0h | SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
| 0 | SOC0 | R-0/W1S | 0h | SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.. Reset type: SYSRSn |
ADCSOC0CTL is shown in Figure 18-105 and described in Table 18-83.
Return to the Summary Table.
ADC SOC0 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC0 External Channel Mux Select. Selects the external mux combination to output when SOC0 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC1CTL is shown in Figure 18-106 and described in Table 18-84.
Return to the Summary Table.
ADC SOC1 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC1 External Channel Mux Select. Selects the external mux combination to output when SOC1 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC2CTL is shown in Figure 18-107 and described in Table 18-85.
Return to the Summary Table.
ADC SOC2 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC3CTL is shown in Figure 18-108 and described in Table 18-86.
Return to the Summary Table.
ADC SOC3 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC3 External Channel Mux Select. Selects the external mux combination to output when SOC3 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC4CTL is shown in Figure 18-109 and described in Table 18-87.
Return to the Summary Table.
ADC SOC4 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC4 External Channel Mux Select. Selects the external mux combination to output when SOC4 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC5CTL is shown in Figure 18-110 and described in Table 18-88.
Return to the Summary Table.
ADC SOC5 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC5 External Channel Mux Select. Selects the external mux combination to output when SOC5 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC6CTL is shown in Figure 18-111 and described in Table 18-89.
Return to the Summary Table.
ADC SOC6 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC6 External Channel Mux Select. Selects the external mux combination to output when SOC6 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC7CTL is shown in Figure 18-112 and described in Table 18-90.
Return to the Summary Table.
ADC SOC7 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC7 External Channel Mux Select. Selects the external mux combination to output when SOC7 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC8CTL is shown in Figure 18-113 and described in Table 18-91.
Return to the Summary Table.
ADC SOC8 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC8 External Channel Mux Select. Selects the external mux combination to output when SOC8 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC9CTL is shown in Figure 18-114 and described in Table 18-92.
Return to the Summary Table.
ADC SOC9 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC9 External Channel Mux Select. Selects the external mux combination to output when SOC9 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC10CTL is shown in Figure 18-115 and described in Table 18-93.
Return to the Summary Table.
ADC SOC10 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC10 External Channel Mux Select. Selects the external mux combination to output when SOC10 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC11CTL is shown in Figure 18-116 and described in Table 18-94.
Return to the Summary Table.
ADC SOC11 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC11 External Channel Mux Select. Selects the external mux combination to output when SOC11 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC12CTL is shown in Figure 18-117 and described in Table 18-95.
Return to the Summary Table.
ADC SOC12 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC12 External Channel Mux Select. Selects the external mux combination to output when SOC12 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC13CTL is shown in Figure 18-118 and described in Table 18-96.
Return to the Summary Table.
ADC SOC13 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC13 External Channel Mux Select. Selects the external mux combination to output when SOC13 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC14CTL is shown in Figure 18-119 and described in Table 18-97.
Return to the Summary Table.
ADC SOC14 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC14 External Channel Mux Select. Selects the external mux combination to output when SOC14 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCSOC15CTL is shown in Figure 18-120 and described in Table 18-98.
Return to the Summary Table.
ADC SOC15 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EXTCHSEL | RESERVED | TRIGSEL | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIGSEL | CHSEL | ||||||
| R/W-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHSEL | RESERVED | RESERVED | RESERVED | ACQPS | |||
| R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACQPS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | EXTCHSEL | R/W | 0h | SOC15 External Channel Mux Select. Selects the external mux combination to output when SOC15 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h ADCEXTMUX[3:0] = 0000 1h ADCEXTMUX[3:0] = 0001 2h ADCEXTMUX[3:0] = 0010 3h ADCEXTMUX[3:0] = 0011 4h ADCEXTMUX[3:0] = 0100 5h ADCEXTMUX[3:0] = 0101 6h ADCEXTMUX[3:0] = 0110 7h ADCEXTMUX[3:0] = 0111 8h ADCEXTMUX[3:0] = 1000 9h ADCEXTMUX[3:0] = 1001 Ah ADCEXTMUX[3:0] = 1010 Bh ADCEXTMUX[3:0] = 1011 Ch ADCEXTMUX[3:0] = 1100 Dh ADCEXTMUX[3:0] = 1101 Eh ADCEXTMUX[3:0] = 1110 Fh ADCEXTMUX[3:0] = 1111 Reset type: SYSRSn |
| 27 | RESERVED | R | 0h | Reserved |
| 26-20 | TRIGSEL | R/W | 0h | SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - CPU1 Timer 0, TINT0n 02h ADCTRIG2 - CPU1 Timer 1, TINT1n 03h ADCTRIG3 - CPU1 Timer 2, TINT2n 04h ADCTRIG4 - GPIO, Input X-Bar INPUT5 05h ADCTRIG5 - ePWM1, ADCSOCA 06h ADCTRIG6 - ePWM1, ADCSOCB 07h ADCTRIG7 - ePWM2, ADCSOCA 08h ADCTRIG8 - ePWM2, ADCSOCB 09h ADCTRIG9 - ePWM3, ADCSOCA 0Ah ADCTRIG10 - ePWM3, ADCSOCB 0Bh ADCTRIG11 - ePWM4, ADCSOCA 0Ch ADCTRIG12 - ePWM4, ADCSOCB 0Dh ADCTRIG13 - ePWM5, ADCSOCA 0Eh ADCTRIG14 - ePWM5, ADCSOCB 0Fh ADCTRIG15 - ePWM6, ADCSOCA 10h ADCTRIG16 - ePWM6, ADCSOCB 11h ADCTRIG17 - ePWM7, ADCSOCA 12h ADCTRIG18 - ePWM7, ADCSOCB 13h ADCTRIG19 - ePWM8, ADCSOCA 14h ADCTRIG20 - ePWM8, ADCSOCB 15h ADCTRIG21 - ePWM9, ADCSOCA 16h ADCTRIG22 - ePWM9, ADCSOCB 17h ADCTRIG23 - ePWM10, ADCSOCA 18h ADCTRIG24 - ePWM10, ADCSOCB 19h ADCTRIG25 - ePWM11, ADCSOCA 1Ah ADCTRIG26 - ePWM11, ADCSOCB 1Bh ADCTRIG27 - ePWM12, ADCSOCA 1Ch ADCTRIG28 - ePWM12, ADCSOCB 1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n 1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n 1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n 20h - 27h - Reserved 28h ADCTRIG40 - REP1TRIG 29h ADCTRIG41 - REP2TRIG 2Ah - 4Fh - Reserved 50h ADCTRIG80 eCAP1 51h ADCTRIG81 eCAP2 52h ADCTRIG82 eCAP3 53h ADCTRIG83 eCAP4 54h ADCTRIG84 eCAP5 55h ADCTRIG85 eCAP6 56h ADCTRIG86 eCAP7 57h ADCTRIG87 eCAP8 58h ADCTRIG88 - ePWM13, ADCSOCA 59h ADCTRIG89 - ePWM13, ADCSOCB 5Ah ADCTRIG90 - ePWM14, ADCSOCA 5Bh ADCTRIG91 - ePWM14, ADCSOCB 5Ch ADCTRIG92 - ePWM15, ADCSOCA 5Dh ADCTRIG93 - ePWM15, ADCSOCB 5Eh ADCTRIG94 - ePWM16, ADCSOCA 5Fh ADCTRIG95 - ePWM16, ADCSOCB 60h ADCTRIG96 - ePWM17, ADCSOCA 61h ADCTRIG97 - ePWM17, ADCSOCB 62h ADCTRIG98 - ePWM18, ADCSOCA 63h ADCTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 19-15 | CHSEL | R/W | 0h | SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. Single-ended Signaling Mode (SIGNALMODE = 0): 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode (SIGNALMODE = 1): 00h ADCIN0 (non-inverting) and ADCIN1 (inverting) 01h ADCIN0 (non-inverting) and ADCIN1 (inverting) 02h ADCIN2 (non-inverting) and ADCIN3 (inverting) 03h ADCIN2 (non-inverting) and ADCIN3 (inverting) 04h ADCIN4 (non-inverting) and ADCIN5 (inverting) 05h ADCIN4 (non-inverting) and ADCIN5 (inverting) ... 0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting) 0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting) 10h ADCIN28 (non-inverting) and ADCIN29 (inverting) 11h ADCIN28 (non-inverting) and ADCIN29 (inverting) 1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting) 1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting) Reset type: SYSRSn |
| 14-12 | RESERVED | R/W | 0h | Reserved |
| 11-10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8-0 | ACQPS | R/W | 0h | SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration. Reset type: SYSRSn |
ADCEVTSTAT is shown in Figure 18-121 and described in Table 18-99.
Return to the Summary Table.
ADC Event Status Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PPB4ZERO | PPB4TRIPLO | PPB4TRIPHI | RESERVED | PPB3ZERO | PPB3TRIPLO | PPB3TRIPHI |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PPB2ZERO | PPB2TRIPLO | PPB2TRIPHI | RESERVED | PPB1ZERO | PPB1TRIPLO | PPB1TRIPHI |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14 | PPB4ZERO | R | 0h | Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 13 | PPB4TRIPLO | R | 0h | Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 12 | PPB4TRIPHI | R | 0h | Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 11 | RESERVED | R | 0h | Reserved |
| 10 | PPB3ZERO | R | 0h | Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 9 | PPB3TRIPLO | R | 0h | Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 8 | PPB3TRIPHI | R | 0h | Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 7 | RESERVED | R | 0h | Reserved |
| 6 | PPB2ZERO | R | 0h | Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 5 | PPB2TRIPLO | R | 0h | Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 4 | PPB2TRIPHI | R | 0h | Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | PPB1ZERO | R | 0h | Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 1 | PPB1TRIPLO | R | 0h | Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 0 | PPB1TRIPHI | R | 0h | Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
ADCEVTCLR is shown in Figure 18-122 and described in Table 18-100.
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ADC Event Clear Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PPB4ZERO | PPB4TRIPLO | PPB4TRIPHI | RESERVED | PPB3ZERO | PPB3TRIPLO | PPB3TRIPHI |
| R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PPB2ZERO | PPB2TRIPLO | PPB2TRIPHI | RESERVED | PPB1ZERO | PPB1TRIPLO | PPB1TRIPHI |
| R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14 | PPB4ZERO | R-0/W1S | 0h | Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 13 | PPB4TRIPLO | R-0/W1S | 0h | Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 12 | PPB4TRIPHI | R-0/W1S | 0h | Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 11 | RESERVED | R | 0h | Reserved |
| 10 | PPB3ZERO | R-0/W1S | 0h | Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 9 | PPB3TRIPLO | R-0/W1S | 0h | Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 8 | PPB3TRIPHI | R-0/W1S | 0h | Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 7 | RESERVED | R | 0h | Reserved |
| 6 | PPB2ZERO | R-0/W1S | 0h | Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 5 | PPB2TRIPLO | R-0/W1S | 0h | Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 4 | PPB2TRIPHI | R-0/W1S | 0h | Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | PPB1ZERO | R-0/W1S | 0h | Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 1 | PPB1TRIPLO | R-0/W1S | 0h | Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
| 0 | PPB1TRIPHI | R-0/W1S | 0h | Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority Reset type: SYSRSn |
ADCEVTSEL is shown in Figure 18-123 and described in Table 18-101.
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ADC Event Selection Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PPB4ZERO | PPB4TRIPLO | PPB4TRIPHI | RESERVED | PPB3ZERO | PPB3TRIPLO | PPB3TRIPHI |
| R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PPB2ZERO | PPB2TRIPLO | PPB2TRIPHI | RESERVED | PPB1ZERO | PPB1TRIPLO | PPB1TRIPHI |
| R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14 | PPB4ZERO | R/W | 0h | Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 13 | PPB4TRIPLO | R/W | 0h | Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 12 | PPB4TRIPHI | R/W | 0h | Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 11 | RESERVED | R | 0h | Reserved |
| 10 | PPB3ZERO | R/W | 0h | Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 9 | PPB3TRIPLO | R/W | 0h | Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 8 | PPB3TRIPHI | R/W | 0h | Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 7 | RESERVED | R | 0h | Reserved |
| 6 | PPB2ZERO | R/W | 0h | Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 5 | PPB2TRIPLO | R/W | 0h | Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 4 | PPB2TRIPHI | R/W | 0h | Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | PPB1ZERO | R/W | 0h | Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 1 | PPB1TRIPLO | R/W | 0h | Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
| 0 | PPB1TRIPHI | R/W | 0h | Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks. Reset type: SYSRSn |
ADCEVTINTSEL is shown in Figure 18-124 and described in Table 18-102.
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ADC Event Interrupt Selection Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PPB4ZERO | PPB4TRIPLO | PPB4TRIPHI | RESERVED | PPB3ZERO | PPB3TRIPLO | PPB3TRIPHI |
| R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PPB2ZERO | PPB2TRIPLO | PPB2TRIPHI | RESERVED | PPB1ZERO | PPB1TRIPLO | PPB1TRIPHI |
| R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14 | PPB4ZERO | R/W | 0h | Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 13 | PPB4TRIPLO | R/W | 0h | Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 12 | PPB4TRIPHI | R/W | 0h | Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 11 | RESERVED | R | 0h | Reserved |
| 10 | PPB3ZERO | R/W | 0h | Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 9 | PPB3TRIPLO | R/W | 0h | Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 8 | PPB3TRIPHI | R/W | 0h | Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 7 | RESERVED | R | 0h | Reserved |
| 6 | PPB2ZERO | R/W | 0h | Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 5 | PPB2TRIPLO | R/W | 0h | Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 4 | PPB2TRIPHI | R/W | 0h | Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | PPB1ZERO | R/W | 0h | Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 1 | PPB1TRIPLO | R/W | 0h | Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
| 0 | PPB1TRIPHI | R/W | 0h | Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE. Reset type: SYSRSn |
ADCOSDETECT is shown in Figure 18-125 and described in Table 18-103.
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ADC Open and Shorts Detect Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DETECTCFG | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-3 | RESERVED | R | 0h | Reserved |
| 2-0 | DETECTCFG | R/W | 0h | ADC Opens and Shorts Detect Configuration. This bit field defines the open/shorts detection circuit state. 0h Open/Shorts detection circuit is disabled. 1h Open/Shorts detection circuit is enabled at zero scale. 2h Open/Shorts detection circuit is enabled at full scale. 3h Open/Shorts detection circuit is enabled at (nominal) 5/12 scale. 4h Open/Shorts detection circuit is enabled at (nominal) 7/12 scale. 5h Open/Shorts detection circuit is enabled with a (nominal) 5K pulldown to VSSA. 6h Open/Shorts detection circuit is enabled with a (nominal) 5K pullup to VDDA. 7h Open/Shorts detection circuit is enabled with a (nominal) 7K pulldown to VSSA. Reset type: SYSRSn |
ADCCOUNTER is shown in Figure 18-126 and described in Table 18-104.
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ADC Counter Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | FREECOUNT | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FREECOUNT | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11-0 | FREECOUNT | R | 0h | ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter. Reset type: SYSRSn |
ADCREV is shown in Figure 18-127 and described in Table 18-105.
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ADC Revision Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| REV | |||||||
| R-1h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TYPE | |||||||
| R-5h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | REV | R | 1h | ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h. Reset type: SYSRSn |
| 7-0 | TYPE | R | 5h | ADC Type. Always set to 5 for this ADC. Reset type: SYSRSn |
ADCOFFTRIM is shown in Figure 18-128 and described in Table 18-106.
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ADC Offset Trim Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OFFTRIM12BSEODD | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFTRIM | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | OFFTRIM12BSEODD | R/W | 0h | If ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 12-bit single-ended mode for odd channels. Range is +127 steps to -128 steps (2's compliment format). Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536. Reset type: XRSn |
| 7-0 | OFFTRIM | R/W | 0h | ADC Offset Trim. Adjusts the conversion results of the converter up or down to account for offset error in the ADC. A different offset trim is required for each combination of resolution and signal mode. If ADCCTL2.OFFTRIMMODE = 0, then using the AdcSetMode function to set the resolution and signal mode will ensure that the correct offset trim is loaded into this register. If ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim only when the ADC is in 12-bit single-ended mode and only for even channels. Range is +127 steps to -128 steps (2's compliment format). Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536. Reset type: XRSn |
ADCOFFTRIM2 is shown in Figure 18-129 and described in Table 18-107.
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ADC Offset Trim Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OFFTRIM16BSEODD | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFTRIM16BSEEVEN | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | OFFTRIM16BSEODD | R/W | 0h | If ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 16-bit single-ended mode for odd channels. Range is +127 steps to -128 steps (2's compliment format). Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536. Reset type: XRSn |
| 7-0 | OFFTRIM16BSEEVEN | R/W | 0h | If ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 16-bit single-ended mode for even channels. Range is +127 steps to -128 steps (2's compliment format). Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536. Reset type: XRSn |
ADCOFFTRIM3 is shown in Figure 18-130 and described in Table 18-108.
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ADC Offset Trim Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OFFTRIM16BDE | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFTRIM12BDE | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | OFFTRIM16BDE | R/W | 0h | If ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 16-bit differential mode. Range is +127 steps to -128 steps (2's compliment format). Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536. Reset type: XRSn |
| 7-0 | OFFTRIM12BDE | R/W | 0h | If ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 12-bit differential mode. Range is +127 steps to -128 steps (2's compliment format). Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536. Reset type: XRSn |
ADCPPB1CONFIG is shown in Figure 18-131 and described in Table 18-109.
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ADC PPB1 Config Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ABSEN | CBCEN | TWOSCOMPEN | CONFIG | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0h | Reserved |
| 6 | ABSEN | R/W | 0h | ADC Post Processing Block 1 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB1. This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT) 0 ADCPPB1RESULT = ADCRESULTx - ADCPPB1OFFREF 1 ADCPPB1RESULT = abs(ADCRESULTx - ADCPPB1OFFREF) Reset type: SYSRSn |
| 5 | CBCEN | R/W | 0h | ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn |
| 4 | TWOSCOMPEN | R/W | 0h | ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB1RESULT register. 0 ADCPPB1RESULT = ADCRESULTx - ADCPPB1OFFREF 1 ADCPPB1RESULT = ADCPPB1OFFREF - ADCRESULTx Reset type: SYSRSn |
| 3-0 | CONFIG | R/W | 0h | ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated with post processing block 1 0010 SOC2/EOC2/RESULT2 is associated with post processing block 1 0011 SOC3/EOC3/RESULT3 is associated with post processing block 1 0100 SOC4/EOC4/RESULT4 is associated with post processing block 1 0101 SOC5/EOC5/RESULT5 is associated with post processing block 1 0110 SOC6/EOC6/RESULT6 is associated with post processing block 1 0111 SOC7/EOC7/RESULT7 is associated with post processing block 1 1000 SOC8/EOC8/RESULT8 is associated with post processing block 1 1001 SOC9/EOC9/RESULT9 is associated with post processing block 1 1010 SOC10/EOC10/RESULT10 is associated with post processing block 1 1011 SOC11/EOC11/RESULT11 is associated with post processing block 1 1100 SOC12/EOC12/RESULT12 is associated with post processing block 1 1101 SOC13/EOC13/RESULT13 is associated with post processing block 1 1110 SOC14/EOC14/RESULT14 is associated with post processing block 1 1111 SOC15/EOC15/RESULT15 is associated with post processing block 1 Reset type: SYSRSn |
ADCPPB1STAMP is shown in Figure 18-132 and described in Table 18-110.
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ADC PPB1 Sample Delay Time Stamp Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DLYSTAMP | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DLYSTAMP | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11-0 | DLYSTAMP | R | 0h | ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample. Reset type: SYSRSn |
ADCPPB1OFFCAL is shown in Figure 18-133 and described in Table 18-111.
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ADC PPB1 Offset Calibration Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | OFFCAL | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFCAL | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | OFFCAL | R/W | 0h | ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register. 000h No change. The ADC output is stored directly into ADCRESULT. 001h ADC output - 1 is stored into ADCRESULT. 002h ADC output - 2 is stored into ADCRESULT. ... 200h ADC output + 512 is stored into ADCRESULT. ... 3FFh ADC output + 1 is stored into ADCRESULT. NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register. Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied. Reset type: SYSRSn |
ADCPPB1OFFREF is shown in Figure 18-134 and described in Table 18-112.
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ADC PPB1 Offset Reference Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OFFREF | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFREF | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | OFFREF | R/W | 0h | ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB1RESULT register. This subtraction is not saturated. 0000h No change. The ADCRESULT value is passed on. 0001h ADCRESULT - 1 is passed on. 0002h ADCRESULT - 2 is passed on. ... 8000h ADCRESULT - 32,768 is passed on. ... FFFFh ADCRESULT - 65,535 is passed on. NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode. Reset type: SYSRSn |
ADCPPB1TRIPHI is shown in Figure 18-135 and described in Table 18-113.
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ADC PPB1 Trip High Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LIMITHI | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | LIMITHI | R/W | 0h | ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will be ignored in 12 bit mode Reset type: SYSRSn |
ADCPPB1TRIPLO is shown in Figure 18-136 and described in Table 18-114.
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ADC PPB1 Trip Low/Trigger Time Stamp Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| REQSTAMP | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| REQSTAMP | LIMITLO2EN | RESERVED | LSIGN | ||||
| R-0h | R/W-0h | R-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| LIMITLO | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LIMITLO | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | REQSTAMP | R | 0h | ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field. Reset type: SYSRSn |
| 19 | LIMITLO2EN | R/W | 0h | Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB1TRIPLO register. Not compatible with comparison with ADCPPB1PSUM or ADCPPB1SUM 1 = Low limit set by ADCPPB1TRIPLO2 register Reset type: SYSRSn |
| 18-17 | RESERVED | R | 0h | Reserved |
| 16 | LSIGN | R/W | 0h | Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode. Reset type: SYSRSn |
| 15-0 | LIMITLO | R/W | 0h | ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB1RESULT register. Reset type: SYSRSn |
ADCPPB2CONFIG is shown in Figure 18-137 and described in Table 18-115.
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ADC PPB2 Config Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ABSEN | CBCEN | TWOSCOMPEN | CONFIG | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0h | Reserved |
| 6 | ABSEN | R/W | 0h | ADC Post Processing Block 2 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB2. This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT) 0 ADCPPB2RESULT = ADCRESULTx - ADCPPB2OFFREF 1 ADCPPB2RESULT = abs(ADCRESULTx - ADCPPB2OFFREF) Reset type: SYSRSn |
| 5 | CBCEN | R/W | 0h | ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn |
| 4 | TWOSCOMPEN | R/W | 0h | ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB2RESULT register. 0 ADCPPB2RESULT = ADCRESULTx - ADCPPB2OFFREF 1 ADCPPB2RESULT = ADCPPB2OFFREF - ADCRESULTx Reset type: SYSRSn |
| 3-0 | CONFIG | R/W | 1h | ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated with post processing block 2 0010 SOC2/EOC2/RESULT2 is associated with post processing block 2 0011 SOC3/EOC3/RESULT3 is associated with post processing block 2 0100 SOC4/EOC4/RESULT4 is associated with post processing block 2 0101 SOC5/EOC5/RESULT5 is associated with post processing block 2 0110 SOC6/EOC6/RESULT6 is associated with post processing block 2 0111 SOC7/EOC7/RESULT7 is associated with post processing block 2 1000 SOC8/EOC8/RESULT8 is associated with post processing block 2 1001 SOC9/EOC9/RESULT9 is associated with post processing block 2 1010 SOC10/EOC10/RESULT10 is associated with post processing block 2 1011 SOC11/EOC11/RESULT11 is associated with post processing block 2 1100 SOC12/EOC12/RESULT12 is associated with post processing block 2 1101 SOC13/EOC13/RESULT13 is associated with post processing block 2 1110 SOC14/EOC14/RESULT14 is associated with post processing block 2 1111 SOC15/EOC15/RESULT15 is associated with post processing block 2 Reset type: SYSRSn |
ADCPPB2STAMP is shown in Figure 18-138 and described in Table 18-116.
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ADC PPB2 Sample Delay Time Stamp Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DLYSTAMP | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DLYSTAMP | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11-0 | DLYSTAMP | R | 0h | ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample. Reset type: SYSRSn |
ADCPPB2OFFCAL is shown in Figure 18-139 and described in Table 18-117.
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ADC PPB2 Offset Calibration Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | OFFCAL | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFCAL | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | OFFCAL | R/W | 0h | ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register. 000h No change. The ADC output is stored directly into ADCRESULT. 001h ADC output - 1 is stored into ADCRESULT. 002h ADC output - 2 is stored into ADCRESULT. ... 200h ADC output + 512 is stored into ADCRESULT. ... 3FFh ADC output + 1 is stored into ADCRESULT. NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register. Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied. Reset type: SYSRSn |
ADCPPB2OFFREF is shown in Figure 18-140 and described in Table 18-118.
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ADC PPB2 Offset Reference Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OFFREF | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFREF | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | OFFREF | R/W | 0h | ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB2RESULT register. This subtraction is not saturated. 0000h No change. The ADCRESULT value is passed on. 0001h ADCRESULT - 1 is passed on. 0002h ADCRESULT - 2 is passed on. ... 8000h ADCRESULT - 32,768 is passed on. ... FFFFh ADCRESULT - 65,535 is passed on. NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode. Reset type: SYSRSn |
ADCPPB2TRIPHI is shown in Figure 18-141 and described in Table 18-119.
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ADC PPB2 Trip High Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LIMITHI | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | LIMITHI | R/W | 0h | ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will be ignored in 12 bit mode Reset type: SYSRSn |
ADCPPB2TRIPLO is shown in Figure 18-142 and described in Table 18-120.
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ADC PPB2 Trip Low/Trigger Time Stamp Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| REQSTAMP | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| REQSTAMP | LIMITLO2EN | RESERVED | LSIGN | ||||
| R-0h | R/W-0h | R-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| LIMITLO | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LIMITLO | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | REQSTAMP | R | 0h | ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field. Reset type: SYSRSn |
| 19 | LIMITLO2EN | R/W | 0h | Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB2TRIPLO register. Not compatible with comparison with ADCPPB2PSUM or ADCPPB2SUM 1 = Low limit set by ADCPPB2TRIPLO2 register Reset type: SYSRSn |
| 18-17 | RESERVED | R | 0h | Reserved |
| 16 | LSIGN | R/W | 0h | Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode. Reset type: SYSRSn |
| 15-0 | LIMITLO | R/W | 0h | ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB2RESULT register. Reset type: SYSRSn |
ADCPPB3CONFIG is shown in Figure 18-143 and described in Table 18-121.
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ADC PPB3 Config Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ABSEN | CBCEN | TWOSCOMPEN | CONFIG | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-2h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0h | Reserved |
| 6 | ABSEN | R/W | 0h | ADC Post Processing Block 3 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB3. This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT) 0 ADCPPB3RESULT = ADCRESULTx - ADCPPB3OFFREF 1 ADCPPB3RESULT = abs(ADCRESULTx - ADCPPB3OFFREF) Reset type: SYSRSn |
| 5 | CBCEN | R/W | 0h | ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn |
| 4 | TWOSCOMPEN | R/W | 0h | ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB3RESULT register. 0 ADCPPB3RESULT = ADCRESULTx - ADCPPB3OFFREF 1 ADCPPB3RESULT = ADCPPB3OFFREF - ADCRESULTx Reset type: SYSRSn |
| 3-0 | CONFIG | R/W | 2h | ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated with post processing block 3 0010 SOC2/EOC2/RESULT2 is associated with post processing block 3 0011 SOC3/EOC3/RESULT3 is associated with post processing block 3 0100 SOC4/EOC4/RESULT4 is associated with post processing block 3 0101 SOC5/EOC5/RESULT5 is associated with post processing block 3 0110 SOC6/EOC6/RESULT6 is associated with post processing block 3 0111 SOC7/EOC7/RESULT7 is associated with post processing block 3 1000 SOC8/EOC8/RESULT8 is associated with post processing block 3 1001 SOC9/EOC9/RESULT9 is associated with post processing block 3 1010 SOC10/EOC10/RESULT10 is associated with post processing block 3 1011 SOC11/EOC11/RESULT11 is associated with post processing block 3 1100 SOC12/EOC12/RESULT12 is associated with post processing block 3 1101 SOC13/EOC13/RESULT13 is associated with post processing block 3 1110 SOC14/EOC14/RESULT14 is associated with post processing block 3 1111 SOC15/EOC15/RESULT15 is associated with post processing block 3 Reset type: SYSRSn |
ADCPPB3STAMP is shown in Figure 18-144 and described in Table 18-122.
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ADC PPB3 Sample Delay Time Stamp Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DLYSTAMP | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DLYSTAMP | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11-0 | DLYSTAMP | R | 0h | ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample. Reset type: SYSRSn |
ADCPPB3OFFCAL is shown in Figure 18-145 and described in Table 18-123.
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ADC PPB3 Offset Calibration Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | OFFCAL | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFCAL | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | OFFCAL | R/W | 0h | ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register. 000h No change. The ADC output is stored directly into ADCRESULT. 001h ADC output - 1 is stored into ADCRESULT. 002h ADC output - 2 is stored into ADCRESULT. ... 200h ADC output + 512 is stored into ADCRESULT. ... 3FFh ADC output + 1 is stored into ADCRESULT. NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register. Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied. Reset type: SYSRSn |
ADCPPB3OFFREF is shown in Figure 18-146 and described in Table 18-124.
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ADC PPB3 Offset Reference Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OFFREF | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFREF | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | OFFREF | R/W | 0h | ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB3RESULT register. This subtraction is not saturated. 0000h No change. The ADCRESULT value is passed on. 0001h ADCRESULT - 1 is passed on. 0002h ADCRESULT - 2 is passed on. ... 8000h ADCRESULT - 32,768 is passed on. ... FFFFh ADCRESULT - 65,535 is passed on. NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode. Reset type: SYSRSn |
ADCPPB3TRIPHI is shown in Figure 18-147 and described in Table 18-125.
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ADC PPB3 Trip High Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LIMITHI | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | LIMITHI | R/W | 0h | ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will be ignored in 12 bit mode Reset type: SYSRSn |
ADCPPB3TRIPLO is shown in Figure 18-148 and described in Table 18-126.
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ADC PPB3 Trip Low/Trigger Time Stamp Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| REQSTAMP | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| REQSTAMP | LIMITLO2EN | RESERVED | LSIGN | ||||
| R-0h | R/W-0h | R-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| LIMITLO | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LIMITLO | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | REQSTAMP | R | 0h | ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field. Reset type: SYSRSn |
| 19 | LIMITLO2EN | R/W | 0h | Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB3TRIPLO register. Not compatible with comparison with ADCPPB3PSUM or ADCPPB3SUM 1 = Low limit set by ADCPPB3TRIPLO2 register Reset type: SYSRSn |
| 18-17 | RESERVED | R | 0h | Reserved |
| 16 | LSIGN | R/W | 0h | Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode. Reset type: SYSRSn |
| 15-0 | LIMITLO | R/W | 0h | ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB3RESULT register. Reset type: SYSRSn |
ADCPPB4CONFIG is shown in Figure 18-149 and described in Table 18-127.
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ADC PPB4 Config Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ABSEN | CBCEN | TWOSCOMPEN | CONFIG | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-3h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0h | Reserved |
| 6 | ABSEN | R/W | 0h | ADC Post Processing Block 4 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB4. This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT) 0 ADCPPB4RESULT = ADCRESULTx - ADCPPB4OFFREF 1 ADCPPB4RESULT = abs(ADCRESULTx - ADCPPB4OFFREF) Reset type: SYSRSn |
| 5 | CBCEN | R/W | 0h | ADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present. Reset type: SYSRSn |
| 4 | TWOSCOMPEN | R/W | 0h | ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB4RESULT register. 0 ADCPPB4RESULT = ADCRESULTx - ADCPPB4OFFREF 1 ADCPPB4RESULT = ADCPPB4OFFREF - ADCRESULTx Reset type: SYSRSn |
| 3-0 | CONFIG | R/W | 3h | ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated with post processing block 4 0010 SOC2/EOC2/RESULT2 is associated with post processing block 4 0011 SOC3/EOC3/RESULT3 is associated with post processing block 4 0100 SOC4/EOC4/RESULT4 is associated with post processing block 4 0101 SOC5/EOC5/RESULT5 is associated with post processing block 4 0110 SOC6/EOC6/RESULT6 is associated with post processing block 4 0111 SOC7/EOC7/RESULT7 is associated with post processing block 4 1000 SOC8/EOC8/RESULT8 is associated with post processing block 4 1001 SOC9/EOC9/RESULT9 is associated with post processing block 4 1010 SOC10/EOC10/RESULT10 is associated with post processing block 4 1011 SOC11/EOC11/RESULT11 is associated with post processing block 4 1100 SOC12/EOC12/RESULT12 is associated with post processing block 4 1101 SOC13/EOC13/RESULT13 is associated with post processing block 4 1110 SOC14/EOC14/RESULT14 is associated with post processing block 4 1111 SOC15/EOC15/RESULT15 is associated with post processing block 4 Reset type: SYSRSn |
ADCPPB4STAMP is shown in Figure 18-150 and described in Table 18-128.
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ADC PPB4 Sample Delay Time Stamp Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DLYSTAMP | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DLYSTAMP | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11-0 | DLYSTAMP | R | 0h | ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample. Reset type: SYSRSn |
ADCPPB4OFFCAL is shown in Figure 18-151 and described in Table 18-129.
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ADC PPB4 Offset Calibration Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | OFFCAL | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFCAL | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | OFFCAL | R/W | 0h | ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register. 000h No change. The ADC output is stored directly into ADCRESULT. 001h ADC output - 1 is stored into ADCRESULT. 002h ADC output - 2 is stored into ADCRESULT. ... 200h ADC output + 512 is stored into ADCRESULT. ... 3FFh ADC output + 1 is stored into ADCRESULT. NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register. Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied. Reset type: SYSRSn |
ADCPPB4OFFREF is shown in Figure 18-152 and described in Table 18-130.
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ADC PPB4 Offset Reference Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OFFREF | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFREF | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | OFFREF | R/W | 0h | ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB4RESULT register. This subtraction is not saturated. 0000h No change. The ADCRESULT value is passed on. 0001h ADCRESULT - 1 is passed on. 0002h ADCRESULT - 2 is passed on. ... 8000h ADCRESULT - 32,768 is passed on. ... FFFFh ADCRESULT - 65,535 is passed on. NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode. Reset type: SYSRSn |
ADCPPB4TRIPHI is shown in Figure 18-153 and described in Table 18-131.
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ADC PPB4 Trip High Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LIMITHI | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | LIMITHI | R/W | 0h | ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will be ignored in 12 bit mode Reset type: SYSRSn |
ADCPPB4TRIPLO is shown in Figure 18-154 and described in Table 18-132.
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ADC PPB4 Trip Low/Trigger Time Stamp Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| REQSTAMP | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| REQSTAMP | LIMITLO2EN | RESERVED | LSIGN | ||||
| R-0h | R/W-0h | R-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| LIMITLO | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LIMITLO | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | REQSTAMP | R | 0h | ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field. Reset type: SYSRSn |
| 19 | LIMITLO2EN | R/W | 0h | Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB4TRIPLO register. Not compatible with comparison with ADCPPB4PSUM or ADCPPB4SUM 1 = Low limit set by ADCPPB4TRIPLO2 register Reset type: SYSRSn |
| 18-17 | RESERVED | R | 0h | Reserved |
| 16 | LSIGN | R/W | 0h | Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode. Reset type: SYSRSn |
| 15-0 | LIMITLO | R/W | 0h | ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB4RESULT register. Reset type: SYSRSn |
ADCSAFECHECKRESEN is shown in Figure 18-155 and described in Table 18-133.
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ADC Safe Check Result Enable Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| SOC15CHKEN | SOC14CHKEN | SOC13CHKEN | SOC12CHKEN | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SOC11CHKEN | SOC10CHKEN | SOC9CHKEN | SOC8CHKEN | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SOC7CHKEN | SOC6CHKEN | SOC5CHKEN | SOC4CHKEN | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SOC3CHKEN | SOC2CHKEN | SOC1CHKEN | SOC0CHKEN | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | SOC15CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT15 passed to safety checker 10 PPB Result associated with SOC15 passed to safety checker 11 PPB Sum associated with SOC15 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 29-28 | SOC14CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT14 passed to safety checker 10 PPB Result associated with SOC14 passed to safety checker 11 PPB Sum associated with SOC14 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 27-26 | SOC13CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT13 passed to safety checker 10 PPB Result associated with SOC13 passed to safety checker 11 PPB Sum associated with SOC13 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 25-24 | SOC12CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT12 passed to safety checker 10 PPB Result associated with SOC12 passed to safety checker 11 PPB Sum associated with SOC12 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 23-22 | SOC11CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT11 passed to safety checker 10 PPB Result associated with SOC11 passed to safety checker 11 PPB Sum associated with SOC11 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 21-20 | SOC10CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT10 passed to safety checker 10 PPB Result associated with SOC10 passed to safety checker 11 PPB Sum associated with SOC10 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 19-18 | SOC9CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT9 passed to safety checker 10 PPB Result associated with SOC9 passed to safety checker 11 PPB Sum associated with SOC9 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 17-16 | SOC8CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT8 passed to safety checker 10 PPB Result associated with SOC8 passed to safety checker 11 PPB Sum associated with SOC8 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 15-14 | SOC7CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT7 passed to safety checker 10 PPB Result associated with SOC7 passed to safety checker 11 PPB Sum associated with SOC7 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 13-12 | SOC6CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT6 passed to safety checker 10 PPB Result associated with SOC6 passed to safety checker 11 PPB Sum associated with SOC6 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 11-10 | SOC5CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT5 passed to safety checker 10 PPB Result associated with SOC5 passed to safety checker 11 PPB Sum associated with SOC5 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 9-8 | SOC4CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT4 passed to safety checker 10 PPB Result associated with SOC4 passed to safety checker 11 PPB Sum associated with SOC4 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 7-6 | SOC3CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT3 passed to safety checker 10 PPB Result associated with SOC3 passed to safety checker 11 PPB Sum associated with SOC3 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 5-4 | SOC2CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT2 passed to safety checker 10 PPB Result associated with SOC2 passed to safety checker 11 PPB Sum associated with SOC2 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 3-2 | SOC1CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT1 passed to safety checker 10 PPB Result associated with SOC1 passed to safety checker 11 PPB Sum associated with SOC1 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
| 1-0 | SOC0CHKEN | R/W | 0h | Determine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker 01 ADCRESULT0 passed to safety checker 10 PPB Result associated with SOC0 passed to safety checker 11 PPB Sum associated with SOC0 passed to safety chekcer Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker Reset type: SYSRSn |
ADCINTCYCLE is shown in Figure 18-156 and described in Table 18-134.
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ADC Early Interrupt Generation Cycle
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DELAY | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DELAY | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | DELAY | R/W | 0h | ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles, for the interrupt to be generated. Reset type: SYSRSn |
ADCINLTRIM1 is shown in Figure 18-157 and described in Table 18-135.
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ADC Linearity Trim 1 Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INLTRIM31TO0 | |||||||||||||||||||||||||||||||
| R/W-Xh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | INLTRIM31TO0 | R/W | Xh | ADC Linearity Trim Bits 31-0. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn |
ADCINLTRIM2 is shown in Figure 18-158 and described in Table 18-136.
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ADC Linearity Trim 2 Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INLTRIM63TO32 | |||||||||||||||||||||||||||||||
| R/W-Xh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | INLTRIM63TO32 | R/W | Xh | ADC Linearity Trim Bits 63-32. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn |
ADCINLTRIM3 is shown in Figure 18-159 and described in Table 18-137.
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ADC Linearity Trim 3 Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INLTRIM95TO64 | |||||||||||||||||||||||||||||||
| R/W-Xh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | INLTRIM95TO64 | R/W | Xh | ADC Linearity Trim Bits 95-64. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn |
ADCINLTRIM4 is shown in Figure 18-160 and described in Table 18-138.
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ADC Linearity Trim 4 Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INLTRIM127TO96 | |||||||||||||||||||||||||||||||
| R/W-Xh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | INLTRIM127TO96 | R/W | Xh | ADC Linearity Trim Bits 127-96. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn |
ADCINLTRIM5 is shown in Figure 18-161 and described in Table 18-139.
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ADC Linearity Trim 5 Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INLTRIM159TO128 | |||||||||||||||||||||||||||||||
| R/W-Xh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | INLTRIM159TO128 | R/W | Xh | ADC Linearity Trim Bits 159-128. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn |
ADCINLTRIM6 is shown in Figure 18-162 and described in Table 18-140.
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ADC Linearity Trim 6 Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INLTRIM191TO160 | |||||||||||||||||||||||||||||||
| R/W-Xh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | INLTRIM191TO160 | R/W | Xh | ADC Linearity Trim Bits 191-160. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications. Reset type: XRSn |
ADCREV2 is shown in Figure 18-163 and described in Table 18-141.
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ADC Wrapper Revision Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| WRAPPERREV | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WRAPPERTYPE | |||||||
| R-4h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | WRAPPERREV | R | 0h | ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h. Reset type: SYSRSn |
| 7-0 | WRAPPERTYPE | R | 4h | ADC Wrapper Type. Always set to 4 for this ADC. Reset type: SYSRSn |
REP1CTL is shown in Figure 18-164 and described in Table 18-142.
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ADC Trigger Repeater 1 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SWSYNC | RESERVED | SYNCINSEL | |||||
| R-0/W1S-0h | R-0h | R/W-0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | TRIGGER | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TRIGGEROVF | PHASEOVF | RESERVED | RESERVED | MODULEBUSY | RESERVED | ACTIVEMODE | MODE |
| R/W1C-0h | R/W1C-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23 | SWSYNC | R-0/W1S | 0h | Trigger repeater 1 software force sync. On a sync. event, all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared. Reset type: SYSRSn |
| 22-21 | RESERVED | R | 0h | Reserved |
| 20-16 | SYNCINSEL | R/W | 0h | Trigger repeater 1 sync. input select. On a sync. event, all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared. 0h = Disable Syncin to Repeater 1 1h = EPWM1SYNCOUT 2h = EPWM2SYNCOUT 3h = EPWM3SYNCOUT 4h = EPWM4SYNCOUT 5h = EPWM5SYNCOUT 6h = EPWM6SYNCOUT 7h = EPWM7SYNCOUT 8h = EPWM8SYNCOUT 9h = EPWM9SYNCOUT Ah = EPWM10SYNCOUT Bh = EPWM11SYNCOUT Ch = EPWM12SYNCOUT Dh = EPWM13SYNCOUT Eh = EPWM14SYNCOUT Fh = EPWM15SYNCOUT 10h = EPWM16SYNCOUT 11h = EPWM17SYNCOUT 12h = EPWM18SYNCOUT 13h = ECAP1SYNCOUT 14h = ECAP2SYNCOUT 15h = ECAP3SYNCOUT 16h = ECAP4SYNCOUT 17h = ECAP5SYNCOUT 18h = ECAP6SYNCOUT 19h = ECAP7SYNCOUT 1Ah = INPUTXBAROUT5 1Bh = INPUTXBAROUT6 1Ch = EtherCATSYNC0 1Dh = EtherCATSYNC1 1Eh - 1Fh = RSVD Reset type: SYSRSn |
| 15 | RESERVED | R | 0h | Reserved |
| 14-8 | TRIGGER | R/W | 0h | ADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - CPU1 Timer 0, TINT0n 02h REPTRIG2 - CPU1 Timer 1, TINT1n 03h REPTRIG3 - CPU1 Timer 2, TINT2n 04h REPTRIG4 - GPIO, Input X-Bar INPUT5 05h REPTRIG5 - ePWM1, ADCSOCA 06h REPTRIG6 - ePWM1, ADCSOCB 07h REPTRIG7 - ePWM2, ADCSOCA 08h REPTRIG8 - ePWM2, ADCSOCB 09h REPTRIG9 - ePWM3, ADCSOCA 0Ah REPTRIG10 - ePWM3, ADCSOCB 0Bh REPTRIG11 - ePWM4, ADCSOCA 0Ch REPTRIG12 - ePWM4, ADCSOCB 0Dh REPTRIG13 - ePWM5, ADCSOCA 0Eh REPTRIG14 - ePWM5, ADCSOCB 0Fh REPTRIG15 - ePWM6, ADCSOCA 10h REPTRIG16 - ePWM6, ADCSOCB 11h REPTRIG17 - ePWM7, ADCSOCA 12h REPTRIG18 - ePWM7, ADCSOCB 13h REPTRIG19 - ePWM8, ADCSOCA 14h REPTRIG20 - ePWM8, ADCSOCB 15h REPTRIG21 - ePWM9, ADCSOCA 16h REPTRIG22 - ePWM9, ADCSOCB 17h REPTRIG23 - ePWM10, ADCSOCA 18h REPTRIG24 - ePWM10, ADCSOCB 19h REPTRIG25 - ePWM11, ADCSOCA 1Ah REPTRIG26 - ePWM11, ADCSOCB 1Bh REPTRIG27 - ePWM12, ADCSOCA 1Ch REPTRIG28 - ePWM12, ADCSOCB 1Dh REPTRIG29 - CPU2 Timer 0, TINT0n 1Eh REPTRIG30 - CPU2 Timer 1, TINT1n 1Fh REPTRIG31 - CPU2 Timer 2, TINT2n 20h - 4Fh - Reserved 50h REPTRIG80 eCAP1 51h REPTRIG81 eCAP2 52h REPTRIG82 eCAP3 53h REPTRIG83 eCAP4 54h REPTRIG84 eCAP5 55h REPTRIG85 eCAP6 56h REPTRIG86 eCAP7 57h REPTRIG87 eCAP8 58h REPTRIG88 - ePWM13, ADCSOCA 59h REPTRIG89 - ePWM13, ADCSOCB 5Ah REPTRIG90 - ePWM14, ADCSOCA 5Bh REPTRIG91 - ePWM14, ADCSOCB 5Ch REPTRIG92 - ePWM15, ADCSOCA 5Dh REPTRIG93 - ePWM15, ADCSOCB 5Eh REPTRIG94 - ePWM16, ADCSOCA 5Fh REPTRIG95 - ePWM16, ADCSOCB 60h REPTRIG96 - ePWM17, ADCSOCA 61h REPTRIG97 - ePWM17, ADCSOCB 62h REPTRIG98 - ePWM18, ADCSOCA 63h REPTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 7 | TRIGGEROVF | R/W1C | 0h | ADC Trigger Repeater 1 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers (NCOUNT was not 0 or SOCs associated with Repeater 1 were still pending). Writing a 1 will clear this flag. Note: This flag won't be set in undersampling mode or when NSEL = 0 if a trigger arrives before the previous SOCs have completed, the trigger will be passed and the overflow flags of the SOCs that were still pending will be set. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn |
| 6 | PHASEOVF | R/W1C | 0h | ADC Trigger Repeater 1 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger (PHASECOUNT was not 0). Writing a 1 will clear this flag. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn |
| 5 | RESERVED | R | 0h | Reserved |
| 4 | RESERVED | R | 0h | Reserved |
| 3 | MODULEBUSY | R | 0h | ADC Trigger Repeater 1 Module Busy indicator. In oversampling mode: 0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 1 still has repeated triggers remaining (NCOUNT > 0) or associated SOCs are still pending (SOCBUSY is 1) If a new oversampled trigger is received while the module is still busy, the TRIGGEROVF bit will be set and the trigger will be ignored. Reset type: SYSRSn |
| 2 | RESERVED | R | 0h | Reserved |
| 1 | ACTIVEMODE | R | 0h | When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't cause any changes in functionality until the module becomes idle and then a new trigger is received. 0 = module is oversampling 1 = module is undersampling Reset type: SYSRSn |
| 0 | MODE | R/W | 0h | ADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode. In oversampling mode, when the trigger selected by REP1CTL.TRIGSEL is received, the repeater will repeat the trigger REP1N.NSEL + 1 times. In undersampling mode, when the trigger selected by REP1CTL.TRIGSEL is received the first time, the repeater will pass the trigger through. The next REP1N.NSEL triggers will be ignored. 0 = oversampling 1 = undersampling Reset type: SYSRSn |
REP1N is shown in Figure 18-165 and described in Table 18-143.
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ADC Trigger Repeater 1 N Select Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NCOUNT | RESERVED | NSEL | ||||||||||||||||||||||||||||
| R-0h | R-0h | R-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-23 | RESERVED | R | 0h | Reserved |
| 22-16 | NCOUNT | R | 0h | ADC trigger repeater 1 trigger count. In oversampling mode, indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 (the repeater is still busy generating the repeated triggers) then the trigger will be ignored and REP1CTL.TRIGOVF will be set to 1. In undersampling mode, indicates the number of triggers remaining to be supressed. Reset type: SYSRSn |
| 15-7 | RESERVED | R | 0h | Reserved |
| 6-0 | NSEL | R/W | 0h | ADC Trigger Repeater 1 selection of number of triggers. In oversampling mode, selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL, NSEL + 1 triggers will be generated. 0 = 1 trigger is generated (pass-through) 1 = 2 triggers are generated 2 = 3 triggers are generated ... 127 = 128 triggers are generated In undersampling mode, selects the number triggers to be supressed. 1 out NSEL + 1 triggers received corresponding to REP1CTL.TRIGSEL will be passed through (the first trigger will be passed through and the subsequent NSEL triggers will be supressed). 0 = all triggers are passed 1 = 1 out of 2 triggers are passed 2 = 1 out of 3 triggers are passed ... 127 = 1 out of 128 triggers are passed Reset type: SYSRSn |
REP1PHASE is shown in Figure 18-166 and described in Table 18-144.
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ADC Trigger Repeater 1 Phase Select Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHASECOUNT | PHASE | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | PHASECOUNT | R | 0h | ADC trigger repeater 1 phase delay status. When the trigger selected by REP1CTL.TRIGSEL is received, this register will start counting down from PHASECOUNT until the counter reaches 0, at which point the trigger will be passed on to the repeater re-trigger logic. If the trigger selected by REP1CTL.TRIGSEL is recieved when PHASECOUNT is not 0 (the phase delay logic is busy from the previous trigger) then the new trigger will be ignored and REP1CTL.PHASEOVF will be set to 1. Reset type: SYSRSn |
| 15-0 | PHASE | R/W | 0h | ADC trigger repeater 1 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 = trigger is delayed by 2 SYSCLKs ... 65535 = trigger is delayed by 65535 SYSCLKs Reset type: SYSRSn |
REP1SPREAD is shown in Figure 18-167 and described in Table 18-145.
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ADC Trigger Repeater 1 Spread Select Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPREADCOUNT | SPREAD | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | SPREADCOUNT | R | 0h | ADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode, this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not occur until SPREADCOUNT is 0 (minimum time is complete) and REP1CTL.BUSY = 0 (SOCs associated with trigger repeater 1 are no longer pending). Reset type: SYSRSn |
| 15-0 | SPREAD | R/W | 0h | ADC trigger repeater 1 spread delay configuration. In oversampling mode, defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with repeater 1 to sample and convert, then the repeater will generate triggers as fast as the ADC can convert the associated conversions. If SPREAD is greater than the time needed for all SOCs associated with repeater 1 to sample and convert, then repeated triggers to the ADC will be SPREAD SYSCLK cycles apart. 0 = oversampled repeated triggers occur as fast as the ADC can sample and convert associated SOCs 1 = time between repeated triggers is at least 1 SYSCLKs 2 = time between repeated triggers is at least 2 SYSCLKs ... 65535 = time between repeated triggers is at least 65535 SYSCLKs Reset type: SYSRSn |
REP1FRC is shown in Figure 18-168 and described in Table 18-146.
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ADC Trigger Repeater 1 Software Force Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SWFRC | ||||||
| R-0h | R-0/W1S-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0h | Reserved |
| 0 | SWFRC | R-0/W1S | 0h | Write 1 to force a trigger to repeat block 1 input regardless of the value of TRIGGER. Always reads 0. Reset type: SYSRSn |
REP2CTL is shown in Figure 18-169 and described in Table 18-147.
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ADC Trigger Repeater 2 Control Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SWSYNC | RESERVED | SYNCINSEL | |||||
| R-0/W1S-0h | R-0h | R/W-0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | TRIGGER | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TRIGGEROVF | PHASEOVF | RESERVED | RESERVED | MODULEBUSY | RESERVED | ACTIVEMODE | MODE |
| R/W1C-0h | R/W1C-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23 | SWSYNC | R-0/W1S | 0h | Trigger repeater 2 software force sync. On a sync. event, all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared. Reset type: SYSRSn |
| 22-21 | RESERVED | R | 0h | Reserved |
| 20-16 | SYNCINSEL | R/W | 0h | Trigger repeater 2 sync. input select. On a sync. event, all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared. 0h = Disable Syncin to Repeater 2 1h = EPWM1SYNCOUT 2h = EPWM2SYNCOUT 3h = EPWM3SYNCOUT 4h = EPWM4SYNCOUT 5h = EPWM5SYNCOUT 6h = EPWM6SYNCOUT 7h = EPWM7SYNCOUT 8h = EPWM8SYNCOUT 9h = EPWM9SYNCOUT Ah = EPWM10SYNCOUT Bh = EPWM11SYNCOUT Ch = EPWM12SYNCOUT Dh = EPWM13SYNCOUT Eh = EPWM14SYNCOUT Fh = EPWM15SYNCOUT 10h = EPWM16SYNCOUT 11h = EPWM17SYNCOUT 12h = EPWM18SYNCOUT 13h = ECAP1SYNCOUT 14h = ECAP2SYNCOUT 15h = ECAP3SYNCOUT 16h = ECAP4SYNCOUT 17h = ECAP5SYNCOUT 18h = ECAP6SYNCOUT 19h = ECAP7SYNCOUT 1Ah = INPUTXBAROUT5 1Bh = INPUTXBAROUT6 1Ch = EtherCATSYNC0 1Dh = EtherCATSYNC1 1Eh - 1Fh = RSVD Reset type: SYSRSn |
| 15 | RESERVED | R | 0h | Reserved |
| 14-8 | TRIGGER | R/W | 0h | ADC Trigger Repeater 2 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - CPU1 Timer 0, TINT0n 02h REPTRIG2 - CPU1 Timer 1, TINT1n 03h REPTRIG3 - CPU1 Timer 2, TINT2n 04h REPTRIG4 - GPIO, Input X-Bar INPUT5 05h REPTRIG5 - ePWM1, ADCSOCA 06h REPTRIG6 - ePWM1, ADCSOCB 07h REPTRIG7 - ePWM2, ADCSOCA 08h REPTRIG8 - ePWM2, ADCSOCB 09h REPTRIG9 - ePWM3, ADCSOCA 0Ah REPTRIG10 - ePWM3, ADCSOCB 0Bh REPTRIG11 - ePWM4, ADCSOCA 0Ch REPTRIG12 - ePWM4, ADCSOCB 0Dh REPTRIG13 - ePWM5, ADCSOCA 0Eh REPTRIG14 - ePWM5, ADCSOCB 0Fh REPTRIG15 - ePWM6, ADCSOCA 10h REPTRIG16 - ePWM6, ADCSOCB 11h REPTRIG17 - ePWM7, ADCSOCA 12h REPTRIG18 - ePWM7, ADCSOCB 13h REPTRIG19 - ePWM8, ADCSOCA 14h REPTRIG20 - ePWM8, ADCSOCB 15h REPTRIG21 - ePWM9, ADCSOCA 16h REPTRIG22 - ePWM9, ADCSOCB 17h REPTRIG23 - ePWM10, ADCSOCA 18h REPTRIG24 - ePWM10, ADCSOCB 19h REPTRIG25 - ePWM11, ADCSOCA 1Ah REPTRIG26 - ePWM11, ADCSOCB 1Bh REPTRIG27 - ePWM12, ADCSOCA 1Ch REPTRIG28 - ePWM12, ADCSOCB 1Dh REPTRIG29 - CPU2 Timer 0, TINT0n 1Eh REPTRIG30 - CPU2 Timer 1, TINT1n 1Fh REPTRIG31 - CPU2 Timer 2, TINT2n 20h - 4Fh - Reserved 50h REPTRIG80 eCAP1 51h REPTRIG81 eCAP2 52h REPTRIG82 eCAP3 53h REPTRIG83 eCAP4 54h REPTRIG84 eCAP5 55h REPTRIG85 eCAP6 56h REPTRIG86 eCAP7 57h REPTRIG87 eCAP8 58h REPTRIG88 - ePWM13, ADCSOCA 59h REPTRIG89 - ePWM13, ADCSOCB 5Ah REPTRIG90 - ePWM14, ADCSOCA 5Bh REPTRIG91 - ePWM14, ADCSOCB 5Ch REPTRIG92 - ePWM15, ADCSOCA 5Dh REPTRIG93 - ePWM15, ADCSOCB 5Eh REPTRIG94 - ePWM16, ADCSOCA 5Fh REPTRIG95 - ePWM16, ADCSOCB 60h REPTRIG96 - ePWM17, ADCSOCA 61h REPTRIG97 - ePWM17, ADCSOCB 62h REPTRIG98 - ePWM18, ADCSOCA 63h REPTRIG99 - ePWM18, ADCSOCB 64h - 7Fh - Reserved Reset type: SYSRSn |
| 7 | TRIGGEROVF | R/W1C | 0h | ADC Trigger Repeater 2 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers (NCOUNT was not 0 or SOCs associated with Repeater 2 were still pending). Writing a 1 will clear this flag. Note: This flag won't be set in undersampling mode or when NSEL = 0 if a trigger arrives before the previous SOCs have completed, the trigger will be passed and the overflow flags of the SOCs that were still pending will be set. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn |
| 6 | PHASEOVF | R/W1C | 0h | ADC Trigger Repeater 2 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger (PHASECOUNT was not 0). Writing a 1 will clear this flag. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set Reset type: SYSRSn |
| 5 | RESERVED | R | 0h | Reserved |
| 4 | RESERVED | R | 0h | Reserved |
| 3 | MODULEBUSY | R | 0h | ADC Trigger Repeater 2 Module Busy indicator. In oversampling mode: 0 = Repeater 2 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 2 still has repeated triggers remaining (NCOUNT > 0) or associated SOCs are still pending (SOCBUSY is 1) If a new oversampled trigger is received while the module is still busy, the TRIGGEROVF bit will be set and the trigger will be ignored. Reset type: SYSRSn |
| 2 | RESERVED | R | 0h | Reserved |
| 1 | ACTIVEMODE | R | 0h | When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't cause any changes in functionality until the module becomes idle and then a new trigger is received. 0 = module is oversampling 1 = module is undersampling Reset type: SYSRSn |
| 0 | MODE | R/W | 0h | ADC trigger repeater 2 mode selection. Select either oversampling or undersampling mode. In oversampling mode, when the trigger selected by REP2CTL.TRIGSEL is received, the repeater will repeat the trigger REP2N.NSEL + 1 times. In undersampling mode, when the trigger selected by REP2CTL.TRIGSEL is received the first time, the repeater will pass the trigger through. The next REP2N.NSEL triggers will be ignored. 0 = oversampling 1 = undersampling Reset type: SYSRSn |
REP2N is shown in Figure 18-170 and described in Table 18-148.
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ADC Trigger Repeater 2 N Select Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NCOUNT | RESERVED | NSEL | ||||||||||||||||||||||||||||
| R-0h | R-0h | R-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-23 | RESERVED | R | 0h | Reserved |
| 22-16 | NCOUNT | R | 0h | ADC trigger repeater 2 trigger count. In oversampling mode, indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP2CTL.TRIGSEL while NCOUNT is not 0 (the repeater is still busy generating the repeated triggers) then the trigger will be ignored and REP2CTL.TRIGOVF will be set to 1. In undersampling mode, indicates the number of triggers remaining to be supressed. Reset type: SYSRSn |
| 15-7 | RESERVED | R | 0h | Reserved |
| 6-0 | NSEL | R/W | 0h | ADC Trigger Repeater 2 selection of number of triggers. In oversampling mode, selects the number of repeated triggers. For each trigger received corresponding to REP2CTL.TRIGSEL, NSEL + 1 triggers will be generated. 0 = 1 trigger is generated (pass-through) 1 = 2 triggers are generated 2 = 3 triggers are generated ... 127 = 128 triggers are generated In undersampling mode, selects the number triggers to be supressed. 1 out NSEL + 1 triggers received corresponding to REP2CTL.TRIGSEL will be passed through (the first trigger will be passed through and the subsequent NSEL triggers will be supressed). 0 = all triggers are passed 1 = 1 out of 2 triggers are passed 2 = 1 out of 3 triggers are passed ... 127 = 1 out of 128 triggers are passed Reset type: SYSRSn |
REP2PHASE is shown in Figure 18-171 and described in Table 18-149.
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ADC Trigger Repeater 2 Phase Select Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHASECOUNT | PHASE | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | PHASECOUNT | R | 0h | ADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received, this register will start counting down from PHASECOUNT until the counter reaches 0, at which point the trigger will be passed on to the repeater re-trigger logic. If the trigger selected by REP2CTL.TRIGSEL is recieved when PHASECOUNT is not 0 (the phase delay logic is busy from the previous trigger) then the new trigger will be ignored and REP2CTL.PHASEOVF will be set to 1. Reset type: SYSRSn |
| 15-0 | PHASE | R/W | 0h | ADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 = trigger is delayed by 2 SYSCLKs ... 65535 = trigger is delayed by 65535 SYSCLKs Reset type: SYSRSn |
REP2SPREAD is shown in Figure 18-172 and described in Table 18-150.
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ADC Trigger Repeater 2 Spread Select Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPREADCOUNT | SPREAD | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | SPREADCOUNT | R | 0h | ADC trigger repeater 2 spread status. When a trigger is sent to the ADC in oversampling mode, this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not occur until SPREADCOUNT is 0 (minimum time is complete) and REP2CTL.BUSY = 0 (SOCs associated with trigger repeater 2 are no longer pending). Reset type: SYSRSn |
| 15-0 | SPREAD | R/W | 0h | ADC trigger repeater 2 spread delay configuration. In oversampling mode, defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with repeater 2 to sample and convert, then the repeater will generate triggers as fast as the ADC can convert the associated conversions. If SPREAD is greater than the time needed for all SOCs associated with repeater 2 to sample and convert, then repeated triggers to the ADC will be SPREAD SYSCLK cycles apart. 0 = oversampled repeated triggers occur as fast as the ADC can sample and convert associated SOCs 1 = time between repeated triggers is at least 1 SYSCLKs 2 = time between repeated triggers is at least 2 SYSCLKs ... 65535 = time between repeated triggers is at least 65535 SYSCLKs Reset type: SYSRSn |
REP2FRC is shown in Figure 18-173 and described in Table 18-151.
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ADC Trigger Repeater 2 Software Force Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SWFRC | ||||||
| R-0h | R-0/W1S-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0h | Reserved |
| 0 | SWFRC | R-0/W1S | 0h | Write 1 to force a trigger to repeat block 2 input regardless of the value of TRIGGER. Always reads 0. Reset type: SYSRSn |
ADCPPB1LIMIT is shown in Figure 18-174 and described in Table 18-152.
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ADC PPB1Conversion Count Limit Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | LIMIT | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LIMIT | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | LIMIT | R/W | 0h | Post Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode. Reset type: SYSRSn |
ADCPPBP1PCOUNT is shown in Figure 18-175 and described in Table 18-153.
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ADC PPB1 Partial Conversion Count Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PCOUNT | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PCOUNT | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PCOUNT | R | 0h | Post Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn |
ADCPPB1CONFIG2 is shown in Figure 18-176 and described in Table 18-154.
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ADC PPB1 Sum Shift Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| COMPSEL | RESERVED | OSINTSEL | SWSYNC | RESERVED | SYNCINSEL | ||
| R/W-0h | R-0h | R/W-0h | R-0/W1S-0h | R-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SYNCINSEL | SHIFT | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | COMPSEL | R/W | 0h | Post Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT, ADCPPB1PSUM, or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB1RESULT is used for compare logic 01 = ADCPPB1PSUM is used for compare logic 10 = ADCPPB1SUM is used for compare logic 11 = Reserved Note: when ADCPPB1PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB1LIMIT equals ADCPPB1COUNT) the ADCPPB1PSUM register will be cleared and the final sum will be loaded into ADCPPB1SUM. For this sample, the final sum, ADCPPB1SUM will be used for the compariosn instead of ADCPPB1PSUM. Reset type: SYSRSn |
| 13 | RESERVED | R | 0h | Reserved |
| 12 | OSINTSEL | R/W | 0h | Post Processing Block 1 Interrupt Source Select. OSINT1 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT1 in addition to a PCOUNT = LIMIT event. 0 = OSINT1 will be generated from PCOUNT = LIMIT only 1 = OSTIN1 will be generated form PCOUNT = LIMIT or a sync. event. Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored. Reset type: SYSRSn |
| 11 | SWSYNC | R-0/W1S | 0h | PPB 1 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn |
| 10-9 | RESERVED | R | 0h | Reserved |
| 8-4 | SYNCINSEL | R/W | 0h | PPB 1 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. 0h = Disable Syncin to PPB 1 1h = EPWM1SYNCOUT 2h = EPWM2SYNCOUT 3h = EPWM3SYNCOUT 4h = EPWM4SYNCOUT 5h = EPWM5SYNCOUT 6h = EPWM6SYNCOUT 7h = EPWM7SYNCOUT 8h = EPWM8SYNCOUT 9h = EPWM9SYNCOUT Ah = EPWM10SYNCOUT Bh = EPWM11SYNCOUT Ch = EPWM12SYNCOUT Dh = EPWM13SYNCOUT Eh = EPWM14SYNCOUT Fh = EPWM15SYNCOUT 10h = EPWM16SYNCOUT 11h = EPWM17SYNCOUT 12h = EPWM18SYNCOUT 13h = ECAP1SYNCOUT 14h = ECAP2SYNCOUT 15h = ECAP3SYNCOUT 16h = ECAP4SYNCOUT 17h = ECAP5SYNCOUT 18h = ECAP6SYNCOUT 19h = ECAP7SYNCOUT 1Ah = INPUTXBAROUT5 1Bh = INPUTXBAROUT6 1Ch = EtherCATSYNC0 1Dh = EtherCATSYNC1 1Eh - 1Fh = RSVD Reset type: SYSRSn |
| 3-0 | SHIFT | R/W | 0h | Post Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 10 : SUM = PSUM >> 10 11 - 15 : Reserved Reset type: SYSRSn |
ADCPPB1PSUM is shown in Figure 18-177 and described in Table 18-155.
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ADC PPB1 Partial Sum Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PSUM | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 23. Reset type: SYSRSn |
| 23-0 | PSUM | R | 0h | Post Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn |
ADCPPB1PMAX is shown in Figure 18-178 and described in Table 18-156.
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ADC PPB1 Partial Max Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PMAX | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn |
| 16-0 | PMAX | R | 0h | Post Processing Block 1 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is larger. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn |
ADCPPB1PMAXI is shown in Figure 18-179 and described in Table 18-157.
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ADC PPB1 Partial Max Index Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PMAXI | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PMAXI | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PMAXI | R | 0h | Post Processing Block 1 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn |
ADCPPB1PMIN is shown in Figure 18-180 and described in Table 18-158.
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ADC PPB1 Partial MIN Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PMIN | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn |
| 16-0 | PMIN | R | 0h | Post Processing Block 1 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is smaller. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn |
ADCPPB1PMINI is shown in Figure 18-181 and described in Table 18-159.
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ADC PPB1 Partial Min Index Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PMINI | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PMINI | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PMINI | R | 0h | Post Processing Block 1 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information). Reset type: SYSRSn |
ADCPPB1TRIPLO2 is shown in Figure 18-182 and described in Table 18-160.
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ADC PPB1 Extended Trip Low Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LIMITLO | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | LIMITLO | R/W | 0h | ADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO2[23:17] will be ignored in 16 bit mode - TRIPLO2[23:13] will be ignored in 12 bit mode Reset type: SYSRSn |
ADCPPB2LIMIT is shown in Figure 18-183 and described in Table 18-161.
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ADC PPB2Conversion Count Limit Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | LIMIT | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LIMIT | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | LIMIT | R/W | 0h | Post Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode. Reset type: SYSRSn |
ADCPPBP2PCOUNT is shown in Figure 18-184 and described in Table 18-162.
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ADC PPB2 Partial Conversion Count Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PCOUNT | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PCOUNT | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PCOUNT | R | 0h | Post Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn |
ADCPPB2CONFIG2 is shown in Figure 18-185 and described in Table 18-163.
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ADC PPB2 Sum Shift Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| COMPSEL | RESERVED | OSINTSEL | SWSYNC | RESERVED | SYNCINSEL | ||
| R/W-0h | R-0h | R/W-0h | R-0/W1S-0h | R-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SYNCINSEL | SHIFT | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | COMPSEL | R/W | 0h | Post Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT, ADCPPB2PSUM, or ADCPPB2SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB2RESULT is used for compare logic 01 = ADCPPB2PSUM is used for compare logic 10 = ADCPPB2SUM is used for compare logic 11 = Reserved Note: when ADCPPB2PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB2LIMIT equals ADCPPB2COUNT) the ADCPPB2PSUM register will be cleared and the final sum will be loaded into ADCPPB2SUM. For this sample, the final sum, ADCPPB2SUM will be used for the compariosn instead of ADCPPB2PSUM. Reset type: SYSRSn |
| 13 | RESERVED | R | 0h | Reserved |
| 12 | OSINTSEL | R/W | 0h | Post Processing Block 2 Interrupt Source Select. OSINT2 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT2 in addition to a PCOUNT = LIMIT event. 0 = OSINT2 will be generated from PCOUNT = LIMIT only 1 = OSTIN2 will be generated form PCOUNT = LIMIT or a sync. event. Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored. Reset type: SYSRSn |
| 11 | SWSYNC | R-0/W1S | 0h | PPB 2 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn |
| 10-9 | RESERVED | R | 0h | Reserved |
| 8-4 | SYNCINSEL | R/W | 0h | PPB 2 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. 0h = Disable Syncin to PPB 2 1h = EPWM1SYNCOUT 2h = EPWM2SYNCOUT 3h = EPWM3SYNCOUT 4h = EPWM4SYNCOUT 5h = EPWM5SYNCOUT 6h = EPWM6SYNCOUT 7h = EPWM7SYNCOUT 8h = EPWM8SYNCOUT 9h = EPWM9SYNCOUT Ah = EPWM10SYNCOUT Bh = EPWM11SYNCOUT Ch = EPWM12SYNCOUT Dh = EPWM13SYNCOUT Eh = EPWM14SYNCOUT Fh = EPWM15SYNCOUT 10h = EPWM16SYNCOUT 11h = EPWM17SYNCOUT 12h = EPWM18SYNCOUT 13h = ECAP1SYNCOUT 14h = ECAP2SYNCOUT 15h = ECAP3SYNCOUT 16h = ECAP4SYNCOUT 17h = ECAP5SYNCOUT 18h = ECAP6SYNCOUT 19h = ECAP7SYNCOUT 1Ah = INPUTXBAROUT5 1Bh = INPUTXBAROUT6 1Ch = EtherCATSYNC0 1Dh = EtherCATSYNC1 1Eh - 1Fh = RSVD Reset type: SYSRSn |
| 3-0 | SHIFT | R/W | 0h | Post Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 10 : SUM = PSUM >> 10 11 - 15 : Reserved Reset type: SYSRSn |
ADCPPB2PSUM is shown in Figure 18-186 and described in Table 18-164.
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ADC PPB2 Partial Sum Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PSUM | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 23. Reset type: SYSRSn |
| 23-0 | PSUM | R | 0h | Post Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn |
ADCPPB2PMAX is shown in Figure 18-187 and described in Table 18-165.
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ADC PPB2 Partial Max Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PMAX | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn |
| 16-0 | PMAX | R | 0h | Post Processing Block 2 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is larger. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn |
ADCPPB2PMAXI is shown in Figure 18-188 and described in Table 18-166.
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ADC PPB2 Partial Max Index Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PMAXI | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PMAXI | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PMAXI | R | 0h | Post Processing Block 2 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn |
ADCPPB2PMIN is shown in Figure 18-189 and described in Table 18-167.
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ADC PPB2 Partial MIN Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PMIN | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn |
| 16-0 | PMIN | R | 0h | Post Processing Block 2 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is smaller. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn |
ADCPPB2PMINI is shown in Figure 18-190 and described in Table 18-168.
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ADC PPB2 Partial Min Index Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PMINI | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PMINI | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PMINI | R | 0h | Post Processing Block 2 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information). Reset type: SYSRSn |
ADCPPB2TRIPLO2 is shown in Figure 18-191 and described in Table 18-169.
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ADC PPB2 Extended Trip Low Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LIMITLO | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | LIMITLO | R/W | 0h | ADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO2[23:17] will be ignored in 16 bit mode - TRIPLO2[23:13] will be ignored in 12 bit mode Reset type: SYSRSn |
ADCPPB3LIMIT is shown in Figure 18-192 and described in Table 18-170.
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ADC PPB3Conversion Count Limit Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | LIMIT | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LIMIT | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | LIMIT | R/W | 0h | Post Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode. Reset type: SYSRSn |
ADCPPBP3PCOUNT is shown in Figure 18-193 and described in Table 18-171.
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ADC PPB3 Partial Conversion Count Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PCOUNT | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PCOUNT | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PCOUNT | R | 0h | Post Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn |
ADCPPB3CONFIG2 is shown in Figure 18-194 and described in Table 18-172.
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ADC PPB3 Sum Shift Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| COMPSEL | RESERVED | OSINTSEL | SWSYNC | RESERVED | SYNCINSEL | ||
| R/W-0h | R-0h | R/W-0h | R-0/W1S-0h | R-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SYNCINSEL | SHIFT | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | COMPSEL | R/W | 0h | Post Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT, ADCPPB3PSUM, or ADCPPB3SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB3RESULT is used for compare logic 01 = ADCPPB3PSUM is used for compare logic 10 = ADCPPB3SUM is used for compare logic 11 = Reserved Note: when ADCPPB3PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB3LIMIT equals ADCPPB3COUNT) the ADCPPB3PSUM register will be cleared and the final sum will be loaded into ADCPPB3SUM. For this sample, the final sum, ADCPPB3SUM will be used for the compariosn instead of ADCPPB3PSUM. Reset type: SYSRSn |
| 13 | RESERVED | R | 0h | Reserved |
| 12 | OSINTSEL | R/W | 0h | Post Processing Block 3 Interrupt Source Select. OSINT3 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT3 in addition to a PCOUNT = LIMIT event. 0 = OSINT3 will be generated from PCOUNT = LIMIT only 1 = OSTIN3 will be generated form PCOUNT = LIMIT or a sync. event. Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored. Reset type: SYSRSn |
| 11 | SWSYNC | R-0/W1S | 0h | PPB 3 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn |
| 10-9 | RESERVED | R | 0h | Reserved |
| 8-4 | SYNCINSEL | R/W | 0h | PPB 3 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. 0h = Disable Syncin to PPB 3 1h = EPWM1SYNCOUT 2h = EPWM2SYNCOUT 3h = EPWM3SYNCOUT 4h = EPWM4SYNCOUT 5h = EPWM5SYNCOUT 6h = EPWM6SYNCOUT 7h = EPWM7SYNCOUT 8h = EPWM8SYNCOUT 9h = EPWM9SYNCOUT Ah = EPWM10SYNCOUT Bh = EPWM11SYNCOUT Ch = EPWM12SYNCOUT Dh = EPWM13SYNCOUT Eh = EPWM14SYNCOUT Fh = EPWM15SYNCOUT 10h = EPWM16SYNCOUT 11h = EPWM17SYNCOUT 12h = EPWM18SYNCOUT 13h = ECAP1SYNCOUT 14h = ECAP2SYNCOUT 15h = ECAP3SYNCOUT 16h = ECAP4SYNCOUT 17h = ECAP5SYNCOUT 18h = ECAP6SYNCOUT 19h = ECAP7SYNCOUT 1Ah = INPUTXBAROUT5 1Bh = INPUTXBAROUT6 1Ch = EtherCATSYNC0 1Dh = EtherCATSYNC1 1Eh - 1Fh = RSVD Reset type: SYSRSn |
| 3-0 | SHIFT | R/W | 0h | Post Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 10 : SUM = PSUM >> 10 11 - 15 : Reserved Reset type: SYSRSn |
ADCPPB3PSUM is shown in Figure 18-195 and described in Table 18-173.
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ADC PPB3 Partial Sum Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PSUM | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 23. Reset type: SYSRSn |
| 23-0 | PSUM | R | 0h | Post Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn |
ADCPPB3PMAX is shown in Figure 18-196 and described in Table 18-174.
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ADC PPB3 Partial Max Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PMAX | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn |
| 16-0 | PMAX | R | 0h | Post Processing Block 3 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is larger. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn |
ADCPPB3PMAXI is shown in Figure 18-197 and described in Table 18-175.
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ADC PPB3 Partial Max Index Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PMAXI | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PMAXI | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PMAXI | R | 0h | Post Processing Block 3 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn |
ADCPPB3PMIN is shown in Figure 18-198 and described in Table 18-176.
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ADC PPB3 Partial MIN Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PMIN | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn |
| 16-0 | PMIN | R | 0h | Post Processing Block 3 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is smaller. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn |
ADCPPB3PMINI is shown in Figure 18-199 and described in Table 18-177.
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ADC PPB3 Partial Min Index Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PMINI | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PMINI | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PMINI | R | 0h | Post Processing Block 3 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information). Reset type: SYSRSn |
ADCPPB3TRIPLO2 is shown in Figure 18-200 and described in Table 18-178.
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ADC PPB3 Extended Trip Low Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LIMITLO | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | LIMITLO | R/W | 0h | ADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO2[23:17] will be ignored in 16 bit mode - TRIPLO2[23:13] will be ignored in 12 bit mode Reset type: SYSRSn |
ADCPPB4LIMIT is shown in Figure 18-201 and described in Table 18-179.
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ADC PPB4Conversion Count Limit Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | LIMIT | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LIMIT | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | LIMIT | R/W | 0h | Post Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode. Reset type: SYSRSn |
ADCPPBP4PCOUNT is shown in Figure 18-202 and described in Table 18-180.
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ADC PPB4 Partial Conversion Count Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PCOUNT | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PCOUNT | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PCOUNT | R | 0h | Post Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn |
ADCPPB4CONFIG2 is shown in Figure 18-203 and described in Table 18-181.
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ADC PPB4 Sum Shift Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| COMPSEL | RESERVED | OSINTSEL | SWSYNC | RESERVED | SYNCINSEL | ||
| R/W-0h | R-0h | R/W-0h | R-0/W1S-0h | R-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SYNCINSEL | SHIFT | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | COMPSEL | R/W | 0h | Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT, ADCPPB4PSUM, or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB4RESULT is used for compare logic 01 = ADCPPB4PSUM is used for compare logic 10 = ADCPPB4SUM is used for compare logic 11 = Reserved Note: when ADCPPB4PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB4LIMIT equals ADCPPB4COUNT) the ADCPPB4PSUM register will be cleared and the final sum will be loaded into ADCPPB4SUM. For this sample, the final sum, ADCPPB4SUM will be used for the compariosn instead of ADCPPB4PSUM. Reset type: SYSRSn |
| 13 | RESERVED | R | 0h | Reserved |
| 12 | OSINTSEL | R/W | 0h | Post Processing Block 4 Interrupt Source Select. OSINT4 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to a PCOUNT = LIMIT event. 0 = OSINT4 will be generated from PCOUNT = LIMIT only 1 = OSTIN4 will be generated form PCOUNT = LIMIT or a sync. event. Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored. Reset type: SYSRSn |
| 11 | SWSYNC | R-0/W1S | 0h | PPB 4 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur. Reset type: SYSRSn |
| 10-9 | RESERVED | R | 0h | Reserved |
| 8-4 | SYNCINSEL | R/W | 0h | PPB 4 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset. 0h = Disable Syncin to PPB 4 1h = EPWM1SYNCOUT 2h = EPWM2SYNCOUT 3h = EPWM3SYNCOUT 4h = EPWM4SYNCOUT 5h = EPWM5SYNCOUT 6h = EPWM6SYNCOUT 7h = EPWM7SYNCOUT 8h = EPWM8SYNCOUT 9h = EPWM9SYNCOUT Ah = EPWM10SYNCOUT Bh = EPWM11SYNCOUT Ch = EPWM12SYNCOUT Dh = EPWM13SYNCOUT Eh = EPWM14SYNCOUT Fh = EPWM15SYNCOUT 10h = EPWM16SYNCOUT 11h = EPWM17SYNCOUT 12h = EPWM18SYNCOUT 13h = ECAP1SYNCOUT 14h = ECAP2SYNCOUT 15h = ECAP3SYNCOUT 16h = ECAP4SYNCOUT 17h = ECAP5SYNCOUT 18h = ECAP6SYNCOUT 19h = ECAP7SYNCOUT 1Ah = INPUTXBAROUT5 1Bh = INPUTXBAROUT6 1Ch = EtherCATSYNC0 1Dh = EtherCATSYNC1 1Eh - 1Fh = RSVD Reset type: SYSRSn |
| 3-0 | SHIFT | R/W | 0h | Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM >> 1 2 : SUM = PSUM >> 2 ... 10 : SUM = PSUM >> 10 11 - 15 : Reserved Reset type: SYSRSn |
ADCPPB4PSUM is shown in Figure 18-204 and described in Table 18-182.
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ADC PPB4 Partial Sum Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PSUM | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 23. Reset type: SYSRSn |
| 23-0 | PSUM | R | 0h | Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information). Reset type: SYSRSn |
ADCPPB4PMAX is shown in Figure 18-205 and described in Table 18-183.
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ADC PPB4 Partial Max Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PMAX | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn |
| 16-0 | PMAX | R | 0h | Post Processing Block 4 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is larger. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn |
ADCPPB4PMAXI is shown in Figure 18-206 and described in Table 18-184.
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ADC PPB4 Partial Max Index Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PMAXI | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PMAXI | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PMAXI | R | 0h | Post Processing Block 4 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn |
ADCPPB4PMIN is shown in Figure 18-207 and described in Table 18-185.
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ADC PPB4 Partial MIN Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIGN | PMIN | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 16. Reset type: SYSRSn |
| 16-0 | PMIN | R | 0h | Post Processing Block 4 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is smaller. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn |
ADCPPB4PMINI is shown in Figure 18-208 and described in Table 18-186.
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ADC PPB4 Partial Min Index Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PMINI | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PMINI | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-0 | PMINI | R | 0h | Post Processing Block 4 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information). Reset type: SYSRSn |
ADCPPB4TRIPLO2 is shown in Figure 18-209 and described in Table 18-187.
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ADC PPB4 Extended Trip Low Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LIMITLO | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | LIMITLO | R/W | 0h | ADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register, the upper bits will be ignored: - TRIPLO2[23:17] will be ignored in 16 bit mode - TRIPLO2[23:13] will be ignored in 12 bit mode Reset type: SYSRSn |