SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
Table 32-4 lists the memory-mapped registers for the USB_REGS registers. All register offset addresses not listed in Table 32-4 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | USBFADDR | USB Device Functional Address | Go | |
1h | USBPOWER | USB Power | Go | |
2h | USBTXIS | USB Transmit Interrupt Status | Go | |
4h | USBRXIS | USB Receive Interrupt Status | Go | |
6h | USBTXIE | USB Transmit Interrupt Enable | Go | |
8h | USBRXIE | USB Receive Interrupt Enable | Go | |
Ah | USBIS | USB General Interrupt Status | Go | |
Bh | USBIE | USB Interrupt Enable | Go | |
Ch | USBFRAME | USB Frame Value | Go | |
Eh | USBEPIDX | USB Endpoint Index | Go | |
Fh | USBTEST | USB Test Mode | Go | |
20h | USBFIFO0 | USB FIFO Endpoint 0 | Go | |
24h | USBFIFO1 | USB FIFO Endpoint 1 | Go | |
28h | USBFIFO2 | USB FIFO Endpoint 2 | Go | |
2Ch | USBFIFO3 | USB FIFO Endpoint 3 | Go | |
60h | USBDEVCTL | USB Device Control | Go | |
62h | USBTXFIFOSZ | USB Transmit Dynamic FIFO Sizing | Go | |
63h | USBRXFIFOSZ | USB Receive Dynamic FIFO Sizing | Go | |
64h | USBTXFIFOADD | USB Transmit FIFO Start Address | Go | |
66h | USBRXFIFOADD | USB Receive FIFO Start Address | Go | |
7Ah | USBCONTIM | USB Connect Timing | Go | |
7Dh | USBFSEOF | USB Full-Speed Last Transaction to End of Frame Timing | Go | |
7Eh | USBLSEOF | USB Low-Speed Last Transaction to End of Frame Timing | Go | |
80h | USBTXFUNCADDR0 | USB Transmit Functional Address Endpoint 0 | Go | |
82h | USBTXHUBADDR0 | USB Transmit Hub Address Endpoint 0 | Go | |
83h | USBTXHUBPORT0 | USB Transmit Hub Port Endpoint 0 | Go | |
88h | USBTXFUNCADDR1 | USB Transmit Functional Address Endpoint 1 | Go | |
8Ah | USBTXHUBADDR1 | USB Transmit Hub Address Endpoint 1 | Go | |
8Bh | USBTXHUBPORT1 | USB Transmit Hub Port Endpoint 1 | Go | |
8Ch | USBRXFUNCADDR1 | USB Receive Functional Address Endpoint 1 | Go | |
8Eh | USBRXHUBADDR1 | USB Receive Hub Address Endpoint 1 | Go | |
8Fh | USBRXHUBPORT1 | USB Receive Hub Port Endpoint 1 | Go | |
90h | USBTXFUNCADDR2 | USB Transmit Functional Address Endpoint 2 | Go | |
92h | USBTXHUBADDR2 | USB Transmit Hub Address Endpoint 2 | Go | |
93h | USBTXHUBPORT2 | USB Transmit Hub Port Endpoint 2 | Go | |
94h | USBRXFUNCADDR2 | USB Receive Functional Address Endpoint 2 | Go | |
96h | USBRXHUBADDR2 | USB Receive Hub Address Endpoint 2 | Go | |
97h | USBRXHUBPORT2 | USB Receive Hub Port Endpoint 2 | Go | |
98h | USBTXFUNCADDR3 | USB Transmit Functional Address Endpoint 3 | Go | |
9Ah | USBTXHUBADDR3 | USB Transmit Hub Address Endpoint 3 | Go | |
9Bh | USBTXHUBPORT3 | USB Transmit Hub Port Endpoint 3 | Go | |
9Ch | USBRXFUNCADDR3 | USB Receive Functional Address Endpoint 3 | Go | |
9Eh | USBRXHUBADDR3 | USB Receive Hub Address Endpoint 3 | Go | |
9Fh | USBRXHUBPORT3 | USB Receive Hub Port Endpoint 3 | Go | |
102h | USBCSRL0 | USB Control and Status Endpoint 0 Low | Go | |
103h | USBCSRH0 | USB Control and Status Endpoint 0 High | Go | |
108h | USBCOUNT0 | USB Receive Byte Count Endpoint 0 | Go | |
10Ah | USBTYPE0 | USB Type Endpoint 0 | Go | |
10Bh | USBNAKLMT | USB NAK Limit | Go | |
110h | USBTXMAXP1 | USB Maximum Transmit Data Endpoint 1 | Go | |
112h | USBTXCSRL1 | USB Transmit Control and Status Endpoint 1 Low | Go | |
113h | USBTXCSRH1 | USB Transmit Control and Status Endpoint 1 High | Go | |
114h | USBRXMAXP1 | USB Maximum Receive Data Endpoint 1 | Go | |
116h | USBRXCSRL1 | USB Receive Control and Status Endpoint 1 Low | Go | |
117h | USBRXCSRH1 | USB Receive Control and Status Endpoint 1 High | Go | |
118h | USBRXCOUNT1 | USB Receive Byte Count Endpoint 1 | Go | |
11Ah | USBTXTYPE1 | USB Host Transmit Configure Type Endpoint 1 | Go | |
11Bh | USBTXINTERVAL1 | USB Host Transmit Interval Endpoint 1 | Go | |
11Ch | USBRXTYPE1 | USB Host Configure Receive Type Endpoint 1 | Go | |
11Dh | USBRXINTERVAL1 | USB Host Receive Polling Interval Endpoint 1 | Go | |
120h | USBTXMAXP2 | USB Maximum Transmit Data Endpoint 2 | Go | |
122h | USBTXCSRL2 | USB Transmit Control and Status Endpoint 2 Low | Go | |
123h | USBTXCSRH2 | USB Transmit Control and Status Endpoint 2 High | Go | |
124h | USBRXMAXP2 | USB Maximum Receive Data Endpoint 2 | Go | |
126h | USBRXCSRL2 | USB Receive Control and Status Endpoint 2 Low | Go | |
127h | USBRXCSRH2 | USB Receive Control and Status Endpoint 2 High | Go | |
128h | USBRXCOUNT2 | USB Receive Byte Count Endpoint 2 | Go | |
12Ah | USBTXTYPE2 | USB Host Transmit Configure Type Endpoint 2 | Go | |
12Bh | USBTXINTERVAL2 | USB Host Transmit Interval Endpoint 2 | Go | |
12Ch | USBRXTYPE2 | USB Host Configure Receive Type Endpoint 2 | Go | |
12Dh | USBRXINTERVAL2 | USB Host Receive Polling Interval Endpoint 2 | Go | |
130h | USBTXMAXP3 | USB Maximum Transmit Data Endpoint 3 | Go | |
132h | USBTXCSRL3 | USB Transmit Control and Status Endpoint 3 Low | Go | |
133h | USBTXCSRH3 | USB Transmit Control and Status Endpoint 3 High | Go | |
134h | USBRXMAXP3 | USB Maximum Receive Data Endpoint 3 | Go | |
136h | USBRXCSRL3 | USB Receive Control and Status Endpoint 3 Low | Go | |
137h | USBRXCSRH3 | USB Receive Control and Status Endpoint 3 High | Go | |
138h | USBRXCOUNT3 | USB Receive Byte Count Endpoint 3 | Go | |
13Ah | USBTXTYPE3 | USB Host Transmit Configure Type Endpoint 3 | Go | |
13Bh | USBTXINTERVAL3 | USB Host Transmit Interval Endpoint 3 | Go | |
13Ch | USBRXTYPE3 | USB Host Configure Receive Type Endpoint 3 | Go | |
13Dh | USBRXINTERVAL3 | USB Host Receive Polling Interval Endpoint 3 | Go | |
304h | USBRQPKTCOUNT1 | USB Request Packet Count in Block Transfer Endpoint 1 | Go | |
308h | USBRQPKTCOUNT2 | USB Request Packet Count in Block Transfer Endpoint 2 | Go | |
30Ch | USBRQPKTCOUNT3 | USB Request Packet Count in Block Transfer Endpoint 3 | Go | |
340h | USBRXDPKTBUFDIS | USB Receive Double Packet Buffer Disable | Go | |
342h | USBTXDPKTBUFDIS | USB Transmit Double Packet Buffer Disable | Go | |
400h | USBEPC | USB External Power Control | Go | |
404h | USBEPCRIS | USB External Power Control Raw Interrupt Status | Go | |
408h | USBEPCIM | USB External Power Control Interrupt Mask | Go | |
40Ch | USBEPCISC | USB External Power Control Interrupt Status and Clear | Go | |
410h | USBDRRIS | USB Device RESUME Raw Interrupt Status | Go | |
414h | USBDRIM | USB Device RESUME Interrupt Mask | Go | |
418h | USBDRISC | USB Device RESUME Interrupt Status and Clear | Go | |
41Ch | USBGPCS | USB General-Purpose Control and Status | Go | |
430h | USBVDC | USB VBUS Droop Control | Go | |
434h | USBVDCRIS | USB VBUS Droop Control Raw Interrupt Status | Go | |
438h | USBVDCIM | USB VBUS Droop Control Interrupt Mask | Go | |
43Ch | USBVDCISC | USB VBUS Droop Control Interrupt Status and Clear | Go | |
444h | USBIDVRIS | USB ID Valid Detect Raw Interrupt Status | Go | |
448h | USBIDVIM | USB ID Valid Detect Interrupt Mask | Go | |
44Ch | USBIDVISC | USB ID Valid Detect Interrupt Status and Clear | Go | |
450h | USBDMASEL | USB DMA Select | Go | |
480h | USB_GLB_INT_EN | USB Global Interrupt Enable Register Note: This Register is applicable only when USB is mapped to CPU1 | Go | |
484h | USB_GLB_INT_FLG | USB Global Interrupt Flag Register Note: This Register is applicable only when USB is mapped to CPU1 | Go | |
488h | USB_GLB_INT_FLG_CLR | USB Global Interrupt Flag Clear Register Note: This Register is applicable only when USB is mapped to CPU1 | Go | |
500h | USBDMARIS | USB uDMA Raw Interrupt Status register. Note: This Register is applicable only when USB is mapped to CM | Go | |
504h | USBDMAIM | USB uDMA Interrupt Mask Register Note: This Register is applicable only when USB is mapped to CM | Go | |
508h | USBDMAISC | USB uDMA Interrupt Status and Clear Register Note: This Register is applicable only when USB is mapped to CM | Go |
Complex bit access types are encoded to fit into small table cells. Table 32-5 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
USBFADDR is shown in Figure 32-3 and described in Table 32-6.
Return to the Summary Table.
USB Device Functional Address
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FUNCADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | FUNCADDR | R/W | 0h | Function Address of Device as received through SET_ADDRESS Reset type: SYSRSn |
USBPOWER is shown in Figure 32-4 and described in Table 32-7.
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USB Power
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ISOUP | SOFT_CONN | RESERVED | RESET | RESUME | SUSPEND | PWRDNPHY | |
R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ISOUP | R/W | 0h | Isochronous Update Reset type: SYSRSn 0h (R/W) = Host Mode - Reserved Device Mode - No effect 1h (R/W) = Host Mode - Reserved Device Mode - The USB controller waits for an SOF token from the time the TXRDY bit is set in the USBTXCSRLn register before sending the packet. If an IN token is received before an SOF token, then a zerolength data packet is sent. |
6 | SOFT_CONN | R/W | 0h | Soft Connect/Disconnect Reset type: SYSRSn 0h (R/W) = Host Mode - Reserved Device Mode - The USB D+/D- lines are tri-stated. 1h (R/W) = Host Mode - Reserved Device Mode - The USB D+/D- lines are enabled. |
5-4 | RESERVED | R | 0h | Reserved |
3 | RESET | R/W | 0h | Enable Reset Signaling Reset type: SYSRSn 0h (R/W) = Ends RESET signaling on the bus. 1h (R/W) = Enables RESET signaling on the bus. |
2 | RESUME | R/W | 0h | Enable Resume Signaling. The bit should be cleared by software 20 ms after being set. Reset type: SYSRSn 0h (R/W) = Ends RESUME signaling on the bus. 1h (R/W) = Enables RESUME signaling when the Device is in SUSPEND mode. |
1 | SUSPEND | R/W | 0h | Enable Suspend Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Enables SUSPEND mode. |
0 | PWRDNPHY | R/W | 0h | Power Down PHY Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Powers down the internal USB PHY. |
USBTXIS is shown in Figure 32-5 and described in Table 32-8.
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USB Transmit Interrupt Status
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EP3 | EP2 | EP1 | EP0 | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | EP3 | R | 0h | Transmit Endpoint 3 Interrupt Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The Endpoint 3 transmit interrupt is asserted. |
2 | EP2 | R | 0h | Transmit Endpoint 2 Interrupt Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The Endpoint 2 transmit interrupt is asserted. |
1 | EP1 | R | 0h | Transmit Endpoint 1 Interrupt Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The Endpoint 1 transmit interrupt is asserted. |
0 | EP0 | R | 0h | Transmit Endpoint 0 Interrupt Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The Endpoint 0 transmit and receive interrupt is asserted. |
USBRXIS is shown in Figure 32-6 and described in Table 32-9.
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USB Receive Interrupt Status
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EP3 | EP2 | EP1 | RESERVED | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | EP3 | R | 0h | Recieve Endpoint 3 Interrupt Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The Endpoint 3 transmit interrupt is asserted. |
2 | EP2 | R | 0h | Recieve Endpoint 2 Interrupt Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The Endpoint 2 transmit interrupt is asserted. |
1 | EP1 | R | 0h | Recieve Endpoint 1 Interrupt Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The Endpoint 1 transmit interrupt is asserted. |
0 | RESERVED | R | 0h | Reserved |
USBTXIE is shown in Figure 32-7 and described in Table 32-10.
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USB Transmit Interrupt Enable
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EP3 | EP2 | EP1 | EP0 | |||
R-0h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | EP3 | R/W | 1h | Transmit Endpoint 3 Interrupt Enable Reset type: SYSRSn 0h (R/W) = The EP3 transmit interrupt is suppressed and not sent to the interrupt controller. 1h (R/W) = An interrupt is sent to the interrupt controller when the EP3 bit in the USBTXIS register is set. |
2 | EP2 | R/W | 1h | Transmit Endpoint 2 Interrupt Enable Reset type: SYSRSn 0h (R/W) = The EP2 transmit interrupt is suppressed and not sent to the interrupt controller. 1h (R/W) = An interrupt is sent to the interrupt controller when the EP2 bit in the USBTXIS register is set. |
1 | EP1 | R/W | 1h | Transmit Endpoint 1 Interrupt Enable Reset type: SYSRSn 0h (R/W) = The EP1 transmit interrupt is suppressed and not sent to the interrupt controller. 1h (R/W) = An interrupt is sent to the interrupt controller when the EP1 bit in the USBTXIS register is set. |
0 | EP0 | R/W | 1h | Transmit Endpoint 0 Interrupt Enable Reset type: SYSRSn 0h (R/W) = The EP0 transmit and receive interrupt is suppressed and not sent to the interupt controller. 1h (R/W) = An interrupt is sent to the interrupt controller when the EP0 bit in the USBTXIS register is set. |
USBRXIE is shown in Figure 32-8 and described in Table 32-11.
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USB Receive Interrupt Enable
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EP3 | EP2 | EP1 | RESERVED | |||
R-0h | R/W-1h | R/W-1h | R/W-1h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | EP3 | R/W | 1h | Recieve Endpoint 3 Interrupt Enable Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The Endpoint 3 transmit interrupt is asserted. |
2 | EP2 | R/W | 1h | Recieve Endpoint 2 Interrupt Enable Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The Endpoint 2 transmit interrupt is asserted. |
1 | EP1 | R/W | 1h | Recieve Endpoint 1 Interrupt Enable Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The Endpoint 1 transmit interrupt is asserted. |
0 | RESERVED | R | 0h | Reserved |
USBIS is shown in Figure 32-9 and described in Table 32-12.
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USB General Interrupt Status
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DISCON | RESERVED | SOF | RESET | RESUME | SUSPEND | |
R-0h | R/W-1h | R-0h | R/W-1h | R/W-1h | R/W-1h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | DISCON | R/W | 1h | Session Disconnect Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = The device has been disconnected from the host. |
4 | RESERVED | R | 0h | Reserved |
3 | SOF | R/W | 1h | Start of frame Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = A new frame has started. |
2 | RESET | R/W | 1h | RESET Signaling Detected Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = RESET signaling has been detected on the bus. |
1 | RESUME | R/W | 1h | RESUME Signaling Detected. Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = RESUME signaling has been detected on the bus while the USB controller is in SUSPEND mode. |
0 | SUSPEND | R | 0h | SUSPEND Signaling Detected Reset type: SYSRSn 0h (R/W) = No interrupt 1h (R/W) = SUSPEND signaling has been detected on the bus. |
USBIE is shown in Figure 32-10 and described in Table 32-13.
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USB Interrupt Enable
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DISCON | RESERVED | SOF | RESET | RESUME | SUSPEND | |
R-0h | R/W-1h | R-0h | R/W-1h | R/W-1h | R/W-1h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | DISCON | R/W | 1h | Session Disconnect Reset type: SYSRSn 0h (R/W) = The DISCON interrupt is suppressed and not sent to the interrupt controller. 1h (R/W) = An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set. |
4 | RESERVED | R | 0h | Reserved |
3 | SOF | R/W | 1h | Start of frame Reset type: SYSRSn 0h (R/W) = The SOF interrupt is suppressed and not sent to the interrupt controller. 1h (R/W) = An interrupt is sent to the interrupt controller when the SOF bit in the USBIS register is set. |
2 | RESET | R/W | 1h | RESET Signaling Detected Reset type: SYSRSn 0h (R/W) = The RESET interrupt is suppressed and not sent to the interrupt controller. 1h (R/W) = An interrupt is sent to the interrupt controller when the RESET bit in the USBIS register is set. |
1 | RESUME | R/W | 1h | RESUME Signaling Detected. Reset type: SYSRSn 0h (R/W) = The RESUME interrupt is suppressed and not sent to the interrupt controller. 1h (R/W) = An interrupt is sent to the interrupt controller when the RESUME bit in the USBIS register is set. |
0 | SUSPEND | R | 0h | SUSPEND Signaling Detected Reset type: SYSRSn 0h (R/W) = The SUSPEND interrupt is suppressed and not sent to the interrupt controller. 1h (R/W) = An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set. |
USBFRAME is shown in Figure 32-11 and described in Table 32-14.
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USB Frame Value
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FRAME | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRAME | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10-0 | FRAME | R | 0h | Frame Number Reset type: SYSRSn |
USBEPIDX is shown in Figure 32-12 and described in Table 32-15.
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USB Endpoint Index
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EPIDX | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R | 0h | Reserved |
3-0 | EPIDX | R/W | 0h | Endpoint Index. This bit field configures which endpoint is accessed when reading or writing to one of the USB controller's indexed registers. A value of 0x0 corresponds to Endpoint 0 and a value of 0xF corresponds to Endpoint 15. Reset type: SYSRSn |
USBTEST is shown in Figure 32-13 and described in Table 32-16.
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USB Test Mode
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FORCEH | FIFOACC | FORCEFS | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FORCEH | R/W | 0h | Force Host Mode. While in this mode, status of the bus connection may be read using the DEV bit of the USBDEVCTL register. The operating speed is determined from the FORCEFS bit. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Forces the USB controller to enter Host mode when the SESSION bit is set, regardless ofwhether the USB controller is connected to any peripheral. The state of the USB0DP and USB0DM signals is ignored. The USB controller then remains in Host mode until the SESSION bit is cleared, even if a Device is disconnected. If the FORCEH bit remains set, the USB controller re-enters Host mode the next time the SESSION bit is set. |
6 | FIFOACC | R/W | 0h | FIFO Access Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO. |
5 | FORCEFS | R/W | 0h | Force Full Speed Upon Reset Reset type: SYSRSn 0h (R/W) = The USB controller operates at Low Speed. 1h (R/W) = Forces the USB controller into Full-Speed mode upon receiving a USB RESET. |
4-0 | RESERVED | R | 0h | Reserved |
USBFIFO0 is shown in Figure 32-14 and described in Table 32-17.
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USB FIFO Endpoint 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | EPDATA | R/W | 0h | Endpoint Data. Writing to this register loads the data into the Transmit FIFO and reading unloads data from the Receive FIFO. Reset type: SYSRSn |
USBFIFO1 is shown in Figure 32-15 and described in Table 32-18.
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USB FIFO Endpoint 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | EPDATA | R/W | 0h | Endpoint Data. Writing to this register loads the data into the Transmit FIFO and reading unloads data from the Receive FIFO. Reset type: SYSRSn |
USBFIFO2 is shown in Figure 32-16 and described in Table 32-19.
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USB FIFO Endpoint 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | EPDATA | R/W | 0h | Endpoint Data. Writing to this register loads the data into the Transmit FIFO and reading unloads data from the Receive FIFO. Reset type: SYSRSn |
USBFIFO3 is shown in Figure 32-17 and described in Table 32-20.
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USB FIFO Endpoint 3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | EPDATA | R/W | 0h | Endpoint Data. Writing to this register loads the data into the Transmit FIFO and reading unloads data from the Receive FIFO. Reset type: SYSRSn |
USBDEVCTL is shown in Figure 32-18 and described in Table 32-21.
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USB Device Control
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEV | FSDEV | LSDEV | VBUS | HOST | HOSTREQ | SESSION | |
R-0h | R/W-1h | R-0h | R/W-1h | R/W-1h | R/W-1h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0h | Reserved |
7 | DEV | R | 0h | Device Mode Reset type: SYSRSn 0h (R/W) = The USB controller is operating on the OTG A side of the cable. 1h (R/W) = The USB controller is operating on the OTG B side of the cable. Only valid while a session is in progress. |
6 | FSDEV | R/W | 1h | Full Speed Device Detected Reset type: SYSRSn 0h (R/W) = A full-speed Device has not been detected on the port. 1h (R/W) = A full-speed Device has been detected on the port. |
5 | LSDEV | R | 0h | Low Speed Device Detected Reset type: SYSRSn 0h (R/W) = A low-speed Device has not been detected on the port. 1h (R/W) = A low-speed Device has been detected on the port. |
4-3 | VBUS | R/W | 1h | Vbus Level Reset type: SYSRSn 0h (R/W) = Above AValid, below VBusValid. VBUS is detected as above 1.5 V and below 4.75 V. 1h (R/W) = Above VBusValid. VBUS is detected as above 4.75 V. |
2 | HOST | R/W | 1h | Host Mode Reset type: SYSRSn 0h (R/W) = The USB controller is acting as a Device. 1h (R/W) = The USB controller is acting as a Host. Only valid while a session is in progress. |
1 | HOSTREQ | R/W | 1h | When set, the USB controller will initiate the Host Negotiation when Suspend mode is entered. It is cleared when Host Negotiation is completed. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Initiates the Host Negotiation when SUSPENDmode is entered. |
0 | SESSION | R | 0h | Session Start/End Reset type: SYSRSn 0h (R/W) = When operating as a Host: When cleared by software, this bit ends a session. When operating as a Device: The USB controller has ended a session. When the USB controller is in SUSPEND mode, this bit may be cleared by software to perform a software disconnect. 1h (R/W) = When operating as a Host: When set by software, this bit starts a session. When operating as a Device: The USB controller has started a session. When set by software, the Session Request Protocol is initiated. Clearing this bit when the USB controller is not suspended results in undefined behavior. |
USBTXFIFOSZ is shown in Figure 32-19 and described in Table 32-22.
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USB Transmit Dynamic FIFO Sizing
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DPB | SIZE | |||||
R-0h | R/W-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0h | Reserved |
4 | DPB | R/W | 0h | Double Packet Buffer Support Reset type: SYSRSn 0h (R/W) = Single packet buffering is supported. 1h (R/W) = Double packet buffering is enabled. |
3-0 | SIZE | R | 0h | Max Packet Size Reset type: SYSRSn 0h (R/W) = 8.0 1h (R/W) = 16.0 2h (R/W) = 32.0 3h (R/W) = 64.0 4h (R/W) = 128.0 5h (R/W) = 256.0 6h (R/W) = 512.0 7h (R/W) = 1024.0 8h (R/W) = 2048.0 9h (R/W) = Reserved Ah (R/W) = Reserved Bh (R/W) = Reserved Ch (R/W) = Reserved Dh (R/W) = Reserved Eh (R/W) = Reserved Fh (R/W) = Reserved |
USBRXFIFOSZ is shown in Figure 32-20 and described in Table 32-23.
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USB Receive Dynamic FIFO Sizing
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DPB | SIZE | |||||
R-0h | R/W-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0h | Reserved |
4 | DPB | R/W | 0h | Double Packet Buffer Support Reset type: SYSRSn 0h (R/W) = Single packet buffering is supported. 1h (R/W) = Double packet buffering is enabled. |
3-0 | SIZE | R | 0h | Maximum packet size to be allowed. If DPB = 0, the FIFO also is this size if DPB = 1, the FIFO is twice this size. Packet size in bytes: Reset type: SYSRSn 0h (R/W) = 8.0 1h (R/W) = 16.0 2h (R/W) = 32.0 3h (R/W) = 64.0 4h (R/W) = 128.0 5h (R/W) = 256.0 6h (R/W) = 512.0 7h (R/W) = 1024.0 8h (R/W) = 2048.0 9h (R/W) = Reserved Ah (R/W) = Reserved Bh (R/W) = Reserved Ch (R/W) = Reserved Dh (R/W) = Reserved Eh (R/W) = Reserved Fh (R/W) = Reserved |
USBTXFIFOADD is shown in Figure 32-21 and described in Table 32-24.
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USB Transmit FIFO Start Address
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | RESERVED | R | 0h | Reserved |
8-0 | ADDR | R/W | 0h | Endpoint Data Reset type: SYSRSn 0h (R/W) = 0.0 1h (R/W) = 8.0 2h (R/W) = 16.0 3h (R/W) = 24.0 4h (R/W) = 32.0 5h (R/W) = 40.0 6h (R/W) = 48.0 7h (R/W) = 56.0 8h (R/W) = 64.0 9h (R/W) = 72.0 Ah (R/W) = 80.0 Bh (R/W) = 88.0 Ch (R/W) = 96.0 Dh (R/W) = 104.0 Eh (R/W) = 112.0 Fh (R/W) = 120.0 10h (R/W) = 128.0 11h (R/W) = 136.0 12h (R/W) = 144.0 13h (R/W) = 152.0 14h (R/W) = 160.0 15h (R/W) = 168.0 16h (R/W) = 176.0 17h (R/W) = 184.0 18h (R/W) = 192.0 19h (R/W) = 200.0 1Ah (R/W) = 208.0 1Bh (R/W) = 216.0 1Ch (R/W) = 224.0 1Dh (R/W) = 232.0 1Eh (R/W) = 240.0 1Fh (R/W) = 248.0 20h (R/W) = 256.0 21h (R/W) = 264.0 22h (R/W) = 272.0 23h (R/W) = 280.0 24h (R/W) = 288.0 25h (R/W) = 296.0 26h (R/W) = 304.0 27h (R/W) = 312.0 28h (R/W) = 320.0 29h (R/W) = 328.0 2Ah (R/W) = 336.0 2Bh (R/W) = 344.0 2Ch (R/W) = 352.0 2Dh (R/W) = 360.0 2Eh (R/W) = 368.0 2Fh (R/W) = 376.0 30h (R/W) = 384.0 31h (R/W) = 392.0 32h (R/W) = 400.0 33h (R/W) = 408.0 34h (R/W) = 416.0 35h (R/W) = 424.0 36h (R/W) = 432.0 37h (R/W) = 440.0 38h (R/W) = 448.0 39h (R/W) = 456.0 3Ah (R/W) = 464.0 3Bh (R/W) = 472.0 3Ch (R/W) = 480.0 3Dh (R/W) = 488.0 3Eh (R/W) = 496.0 3Fh (R/W) = 504.0 40h (R/W) = 512.0 41h (R/W) = 520.0 42h (R/W) = 528.0 43h (R/W) = 536.0 44h (R/W) = 544.0 45h (R/W) = 552.0 46h (R/W) = 560.0 47h (R/W) = 568.0 48h (R/W) = 576.0 49h (R/W) = 584.0 4Ah (R/W) = 592.0 4Bh (R/W) = 600.0 4Ch (R/W) = 608.0 4Dh (R/W) = 616.0 4Eh (R/W) = 624.0 4Fh (R/W) = 632.0 50h (R/W) = 640.0 51h (R/W) = 648.0 52h (R/W) = 656.0 53h (R/W) = 664.0 54h (R/W) = 672.0 55h (R/W) = 680.0 56h (R/W) = 688.0 57h (R/W) = 696.0 58h (R/W) = 704.0 59h (R/W) = 712.0 5Ah (R/W) = 720.0 5Bh (R/W) = 728.0 5Ch (R/W) = 736.0 5Dh (R/W) = 744.0 5Eh (R/W) = 752.0 5Fh (R/W) = 760.0 60h (R/W) = 768.0 61h (R/W) = 776.0 62h (R/W) = 784.0 63h (R/W) = 792.0 64h (R/W) = 800.0 65h (R/W) = 808.0 66h (R/W) = 816.0 67h (R/W) = 824.0 68h (R/W) = 832.0 69h (R/W) = 840.0 6Ah (R/W) = 848.0 6Bh (R/W) = 856.0 6Ch (R/W) = 864.0 6Dh (R/W) = 872.0 6Eh (R/W) = 880.0 6Fh (R/W) = 888.0 70h (R/W) = 896.0 71h (R/W) = 904.0 72h (R/W) = 912.0 73h (R/W) = 920.0 74h (R/W) = 928.0 75h (R/W) = 936.0 76h (R/W) = 944.0 77h (R/W) = 952.0 78h (R/W) = 960.0 79h (R/W) = 968.0 7Ah (R/W) = 976.0 7Bh (R/W) = 984.0 7Ch (R/W) = 992.0 7Dh (R/W) = 1000.0 7Eh (R/W) = 1008.0 7Fh (R/W) = 1016.0 80h (R/W) = 1024.0 81h (R/W) = 1032.0 82h (R/W) = 1040.0 83h (R/W) = 1048.0 84h (R/W) = 1056.0 85h (R/W) = 1064.0 86h (R/W) = 1072.0 87h (R/W) = 1080.0 88h (R/W) = 1088.0 89h (R/W) = 1096.0 8Ah (R/W) = 1104.0 8Bh (R/W) = 1112.0 8Ch (R/W) = 1120.0 8Dh (R/W) = 1128.0 8Eh (R/W) = 1136.0 8Fh (R/W) = 1144.0 90h (R/W) = 1152.0 91h (R/W) = 1160.0 92h (R/W) = 1168.0 93h (R/W) = 1176.0 94h (R/W) = 1184.0 95h (R/W) = 1192.0 96h (R/W) = 1200.0 97h (R/W) = 1208.0 98h (R/W) = 1216.0 99h (R/W) = 1224.0 9Ah (R/W) = 1232.0 9Bh (R/W) = 1240.0 9Ch (R/W) = 1248.0 9Dh (R/W) = 1256.0 9Eh (R/W) = 1264.0 9Fh (R/W) = 1272.0 A0h (R/W) = 1280.0 A1h (R/W) = 1288.0 A2h (R/W) = 1296.0 A3h (R/W) = 1304.0 A4h (R/W) = 1312.0 A5h (R/W) = 1320.0 A6h (R/W) = 1328.0 A7h (R/W) = 1336.0 A8h (R/W) = 1344.0 A9h (R/W) = 1352.0 AAh (R/W) = 1360.0 ABh (R/W) = 1368.0 ACh (R/W) = 1376.0 ADh (R/W) = 1384.0 AEh (R/W) = 1392.0 AFh (R/W) = 1400.0 B0h (R/W) = 1408.0 B1h (R/W) = 1416.0 B2h (R/W) = 1424.0 B3h (R/W) = 1432.0 B4h (R/W) = 1440.0 B5h (R/W) = 1448.0 B6h (R/W) = 1456.0 B7h (R/W) = 1464.0 B8h (R/W) = 1472.0 B9h (R/W) = 1480.0 BAh (R/W) = 1488.0 BBh (R/W) = 1496.0 BCh (R/W) = 1504.0 BDh (R/W) = 1512.0 BEh (R/W) = 1520.0 BFh (R/W) = 1528.0 C0h (R/W) = 1536.0 C1h (R/W) = 1544.0 C2h (R/W) = 1552.0 C3h (R/W) = 1560.0 C4h (R/W) = 1568.0 C5h (R/W) = 1576.0 C6h (R/W) = 1584.0 C7h (R/W) = 1592.0 C8h (R/W) = 1600.0 C9h (R/W) = 1608.0 CAh (R/W) = 1616.0 CBh (R/W) = 1624.0 CCh (R/W) = 1632.0 CDh (R/W) = 1640.0 CEh (R/W) = 1648.0 CFh (R/W) = 1656.0 D0h (R/W) = 1664.0 D1h (R/W) = 1672.0 D2h (R/W) = 1680.0 D3h (R/W) = 1688.0 D4h (R/W) = 1696.0 D5h (R/W) = 1704.0 D6h (R/W) = 1712.0 D7h (R/W) = 1720.0 D8h (R/W) = 1728.0 D9h (R/W) = 1736.0 DAh (R/W) = 1744.0 DBh (R/W) = 1752.0 DCh (R/W) = 1760.0 DDh (R/W) = 1768.0 DEh (R/W) = 1776.0 DFh (R/W) = 1784.0 E0h (R/W) = 1792.0 E1h (R/W) = 1800.0 E2h (R/W) = 1808.0 E3h (R/W) = 1816.0 E4h (R/W) = 1824.0 E5h (R/W) = 1832.0 E6h (R/W) = 1840.0 E7h (R/W) = 1848.0 E8h (R/W) = 1856.0 E9h (R/W) = 1864.0 EAh (R/W) = 1872.0 EBh (R/W) = 1880.0 ECh (R/W) = 1888.0 EDh (R/W) = 1896.0 EEh (R/W) = 1904.0 EFh (R/W) = 1912.0 F0h (R/W) = 1920.0 F1h (R/W) = 1928.0 F2h (R/W) = 1936.0 F3h (R/W) = 1944.0 F4h (R/W) = 1952.0 F5h (R/W) = 1960.0 F6h (R/W) = 1968.0 F7h (R/W) = 1976.0 F8h (R/W) = 1984.0 F9h (R/W) = 1992.0 FAh (R/W) = 2000.0 FBh (R/W) = 2008.0 FCh (R/W) = 2016.0 FDh (R/W) = 2024.0 FEh (R/W) = 2032.0 FFh (R/W) = 2040.0 100h (R/W) = 2048.0 101h (R/W) = 2056.0 102h (R/W) = 2064.0 103h (R/W) = 2072.0 104h (R/W) = 2080.0 105h (R/W) = 2088.0 106h (R/W) = 2096.0 107h (R/W) = 2104.0 108h (R/W) = 2112.0 109h (R/W) = 2120.0 10Ah (R/W) = 2128.0 10Bh (R/W) = 2136.0 10Ch (R/W) = 2144.0 10Dh (R/W) = 2152.0 10Eh (R/W) = 2160.0 10Fh (R/W) = 2168.0 110h (R/W) = 2176.0 111h (R/W) = 2184.0 112h (R/W) = 2192.0 113h (R/W) = 2200.0 114h (R/W) = 2208.0 115h (R/W) = 2216.0 116h (R/W) = 2224.0 117h (R/W) = 2232.0 118h (R/W) = 2240.0 119h (R/W) = 2248.0 11Ah (R/W) = 2256.0 11Bh (R/W) = 2264.0 11Ch (R/W) = 2272.0 11Dh (R/W) = 2280.0 11Eh (R/W) = 2288.0 11Fh (R/W) = 2296.0 120h (R/W) = 2304.0 121h (R/W) = 2312.0 122h (R/W) = 2320.0 123h (R/W) = 2328.0 124h (R/W) = 2336.0 125h (R/W) = 2344.0 126h (R/W) = 2352.0 127h (R/W) = 2360.0 128h (R/W) = 2368.0 129h (R/W) = 2376.0 12Ah (R/W) = 2384.0 12Bh (R/W) = 2392.0 12Ch (R/W) = 2400.0 12Dh (R/W) = 2408.0 12Eh (R/W) = 2416.0 12Fh (R/W) = 2424.0 130h (R/W) = 2432.0 131h (R/W) = 2440.0 132h (R/W) = 2448.0 133h (R/W) = 2456.0 134h (R/W) = 2464.0 135h (R/W) = 2472.0 136h (R/W) = 2480.0 137h (R/W) = 2488.0 138h (R/W) = 2496.0 139h (R/W) = 2504.0 13Ah (R/W) = 2512.0 13Bh (R/W) = 2520.0 13Ch (R/W) = 2528.0 13Dh (R/W) = 2536.0 13Eh (R/W) = 2544.0 13Fh (R/W) = 2552.0 140h (R/W) = 2560.0 141h (R/W) = 2568.0 142h (R/W) = 2576.0 143h (R/W) = 2584.0 144h (R/W) = 2592.0 145h (R/W) = 2600.0 146h (R/W) = 2608.0 147h (R/W) = 2616.0 148h (R/W) = 2624.0 149h (R/W) = 2632.0 14Ah (R/W) = 2640.0 14Bh (R/W) = 2648.0 14Ch (R/W) = 2656.0 14Dh (R/W) = 2664.0 14Eh (R/W) = 2672.0 14Fh (R/W) = 2680.0 150h (R/W) = 2688.0 151h (R/W) = 2696.0 152h (R/W) = 2704.0 153h (R/W) = 2712.0 154h (R/W) = 2720.0 155h (R/W) = 2728.0 156h (R/W) = 2736.0 157h (R/W) = 2744.0 158h (R/W) = 2752.0 159h (R/W) = 2760.0 15Ah (R/W) = 2768.0 15Bh (R/W) = 2776.0 15Ch (R/W) = 2784.0 15Dh (R/W) = 2792.0 15Eh (R/W) = 2800.0 15Fh (R/W) = 2808.0 160h (R/W) = 2816.0 161h (R/W) = 2824.0 162h (R/W) = 2832.0 163h (R/W) = 2840.0 164h (R/W) = 2848.0 165h (R/W) = 2856.0 166h (R/W) = 2864.0 167h (R/W) = 2872.0 168h (R/W) = 2880.0 169h (R/W) = 2888.0 16Ah (R/W) = 2896.0 16Bh (R/W) = 2904.0 16Ch (R/W) = 2912.0 16Dh (R/W) = 2920.0 16Eh (R/W) = 2928.0 16Fh (R/W) = 2936.0 170h (R/W) = 2944.0 171h (R/W) = 2952.0 172h (R/W) = 2960.0 173h (R/W) = 2968.0 174h (R/W) = 2976.0 175h (R/W) = 2984.0 176h (R/W) = 2992.0 177h (R/W) = 3000.0 178h (R/W) = 3008.0 179h (R/W) = 3016.0 17Ah (R/W) = 3024.0 17Bh (R/W) = 3032.0 17Ch (R/W) = 3040.0 17Dh (R/W) = 3048.0 17Eh (R/W) = 3056.0 17Fh (R/W) = 3064.0 180h (R/W) = 3072.0 181h (R/W) = 3080.0 182h (R/W) = 3088.0 183h (R/W) = 3096.0 184h (R/W) = 3104.0 185h (R/W) = 3112.0 186h (R/W) = 3120.0 187h (R/W) = 3128.0 188h (R/W) = 3136.0 189h (R/W) = 3144.0 18Ah (R/W) = 3152.0 18Bh (R/W) = 3160.0 18Ch (R/W) = 3168.0 18Dh (R/W) = 3176.0 18Eh (R/W) = 3184.0 18Fh (R/W) = 3192.0 190h (R/W) = 3200.0 191h (R/W) = 3208.0 192h (R/W) = 3216.0 193h (R/W) = 3224.0 194h (R/W) = 3232.0 195h (R/W) = 3240.0 196h (R/W) = 3248.0 197h (R/W) = 3256.0 198h (R/W) = 3264.0 199h (R/W) = 3272.0 19Ah (R/W) = 3280.0 19Bh (R/W) = 3288.0 19Ch (R/W) = 3296.0 19Dh (R/W) = 3304.0 19Eh (R/W) = 3312.0 19Fh (R/W) = 3320.0 1A0h (R/W) = 3328.0 1A1h (R/W) = 3336.0 1A2h (R/W) = 3344.0 1A3h (R/W) = 3352.0 1A4h (R/W) = 3360.0 1A5h (R/W) = 3368.0 1A6h (R/W) = 3376.0 1A7h (R/W) = 3384.0 1A8h (R/W) = 3392.0 1A9h (R/W) = 3400.0 1AAh (R/W) = 3408.0 1ABh (R/W) = 3416.0 1ACh (R/W) = 3424.0 1ADh (R/W) = 3432.0 1AEh (R/W) = 3440.0 1AFh (R/W) = 3448.0 1B0h (R/W) = 3456.0 1B1h (R/W) = 3464.0 1B2h (R/W) = 3472.0 1B3h (R/W) = 3480.0 1B4h (R/W) = 3488.0 1B5h (R/W) = 3496.0 1B6h (R/W) = 3504.0 1B7h (R/W) = 3512.0 1B8h (R/W) = 3520.0 1B9h (R/W) = 3528.0 1BAh (R/W) = 3536.0 1BBh (R/W) = 3544.0 1BCh (R/W) = 3552.0 1BDh (R/W) = 3560.0 1BEh (R/W) = 3568.0 1BFh (R/W) = 3576.0 1C0h (R/W) = 3584.0 1C1h (R/W) = 3592.0 1C2h (R/W) = 3600.0 1C3h (R/W) = 3608.0 1C4h (R/W) = 3616.0 1C5h (R/W) = 3624.0 1C6h (R/W) = 3632.0 1C7h (R/W) = 3640.0 1C8h (R/W) = 3648.0 1C9h (R/W) = 3656.0 1CAh (R/W) = 3664.0 1CBh (R/W) = 3672.0 1CCh (R/W) = 3680.0 1CDh (R/W) = 3688.0 1CEh (R/W) = 3696.0 1CFh (R/W) = 3704.0 1D0h (R/W) = 3712.0 1D1h (R/W) = 3720.0 1D2h (R/W) = 3728.0 1D3h (R/W) = 3736.0 1D4h (R/W) = 3744.0 1D5h (R/W) = 3752.0 1D6h (R/W) = 3760.0 1D7h (R/W) = 3768.0 1D8h (R/W) = 3776.0 1D9h (R/W) = 3784.0 1DAh (R/W) = 3792.0 1DBh (R/W) = 3800.0 1DCh (R/W) = 3808.0 1DDh (R/W) = 3816.0 1DEh (R/W) = 3824.0 1DFh (R/W) = 3832.0 1E0h (R/W) = 3840.0 1E1h (R/W) = 3848.0 1E2h (R/W) = 3856.0 1E3h (R/W) = 3864.0 1E4h (R/W) = 3872.0 1E5h (R/W) = 3880.0 1E6h (R/W) = 3888.0 1E7h (R/W) = 3896.0 1E8h (R/W) = 3904.0 1E9h (R/W) = 3912.0 1EAh (R/W) = 3920.0 1EBh (R/W) = 3928.0 1ECh (R/W) = 3936.0 1EDh (R/W) = 3944.0 1EEh (R/W) = 3952.0 1EFh (R/W) = 3960.0 1F0h (R/W) = 3968.0 1F1h (R/W) = 3976.0 1F2h (R/W) = 3984.0 1F3h (R/W) = 3992.0 1F4h (R/W) = 4000.0 1F5h (R/W) = 4008.0 1F6h (R/W) = 4016.0 1F7h (R/W) = 4024.0 1F8h (R/W) = 4032.0 1F9h (R/W) = 4040.0 1FAh (R/W) = 4048.0 1FBh (R/W) = 4056.0 1FCh (R/W) = 4064.0 1FDh (R/W) = 4072.0 1FEh (R/W) = 4080.0 1FFh (R/W) = 4088.0 |
USBRXFIFOADD is shown in Figure 32-22 and described in Table 32-25.
Return to the Summary Table.
USB Receive FIFO Start Address
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | RESERVED | R | 0h | Reserved |
8-0 | ADDR | R/W | 0h | Endpoint Data Reset type: SYSRSn 0h (R/W) = 0.0 1h (R/W) = 8.0 2h (R/W) = 16.0 3h (R/W) = 24.0 4h (R/W) = 32.0 5h (R/W) = 40.0 6h (R/W) = 48.0 7h (R/W) = 56.0 8h (R/W) = 64.0 9h (R/W) = 72.0 Ah (R/W) = 80.0 Bh (R/W) = 88.0 Ch (R/W) = 96.0 Dh (R/W) = 104.0 Eh (R/W) = 112.0 Fh (R/W) = 120.0 10h (R/W) = 128.0 11h (R/W) = 136.0 12h (R/W) = 144.0 13h (R/W) = 152.0 14h (R/W) = 160.0 15h (R/W) = 168.0 16h (R/W) = 176.0 17h (R/W) = 184.0 18h (R/W) = 192.0 19h (R/W) = 200.0 1Ah (R/W) = 208.0 1Bh (R/W) = 216.0 1Ch (R/W) = 224.0 1Dh (R/W) = 232.0 1Eh (R/W) = 240.0 1Fh (R/W) = 248.0 20h (R/W) = 256.0 21h (R/W) = 264.0 22h (R/W) = 272.0 23h (R/W) = 280.0 24h (R/W) = 288.0 25h (R/W) = 296.0 26h (R/W) = 304.0 27h (R/W) = 312.0 28h (R/W) = 320.0 29h (R/W) = 328.0 2Ah (R/W) = 336.0 2Bh (R/W) = 344.0 2Ch (R/W) = 352.0 2Dh (R/W) = 360.0 2Eh (R/W) = 368.0 2Fh (R/W) = 376.0 30h (R/W) = 384.0 31h (R/W) = 392.0 32h (R/W) = 400.0 33h (R/W) = 408.0 34h (R/W) = 416.0 35h (R/W) = 424.0 36h (R/W) = 432.0 37h (R/W) = 440.0 38h (R/W) = 448.0 39h (R/W) = 456.0 3Ah (R/W) = 464.0 3Bh (R/W) = 472.0 3Ch (R/W) = 480.0 3Dh (R/W) = 488.0 3Eh (R/W) = 496.0 3Fh (R/W) = 504.0 40h (R/W) = 512.0 41h (R/W) = 520.0 42h (R/W) = 528.0 43h (R/W) = 536.0 44h (R/W) = 544.0 45h (R/W) = 552.0 46h (R/W) = 560.0 47h (R/W) = 568.0 48h (R/W) = 576.0 49h (R/W) = 584.0 4Ah (R/W) = 592.0 4Bh (R/W) = 600.0 4Ch (R/W) = 608.0 4Dh (R/W) = 616.0 4Eh (R/W) = 624.0 4Fh (R/W) = 632.0 50h (R/W) = 640.0 51h (R/W) = 648.0 52h (R/W) = 656.0 53h (R/W) = 664.0 54h (R/W) = 672.0 55h (R/W) = 680.0 56h (R/W) = 688.0 57h (R/W) = 696.0 58h (R/W) = 704.0 59h (R/W) = 712.0 5Ah (R/W) = 720.0 5Bh (R/W) = 728.0 5Ch (R/W) = 736.0 5Dh (R/W) = 744.0 5Eh (R/W) = 752.0 5Fh (R/W) = 760.0 60h (R/W) = 768.0 61h (R/W) = 776.0 62h (R/W) = 784.0 63h (R/W) = 792.0 64h (R/W) = 800.0 65h (R/W) = 808.0 66h (R/W) = 816.0 67h (R/W) = 824.0 68h (R/W) = 832.0 69h (R/W) = 840.0 6Ah (R/W) = 848.0 6Bh (R/W) = 856.0 6Ch (R/W) = 864.0 6Dh (R/W) = 872.0 6Eh (R/W) = 880.0 6Fh (R/W) = 888.0 70h (R/W) = 896.0 71h (R/W) = 904.0 72h (R/W) = 912.0 73h (R/W) = 920.0 74h (R/W) = 928.0 75h (R/W) = 936.0 76h (R/W) = 944.0 77h (R/W) = 952.0 78h (R/W) = 960.0 79h (R/W) = 968.0 7Ah (R/W) = 976.0 7Bh (R/W) = 984.0 7Ch (R/W) = 992.0 7Dh (R/W) = 1000.0 7Eh (R/W) = 1008.0 7Fh (R/W) = 1016.0 80h (R/W) = 1024.0 81h (R/W) = 1032.0 82h (R/W) = 1040.0 83h (R/W) = 1048.0 84h (R/W) = 1056.0 85h (R/W) = 1064.0 86h (R/W) = 1072.0 87h (R/W) = 1080.0 88h (R/W) = 1088.0 89h (R/W) = 1096.0 8Ah (R/W) = 1104.0 8Bh (R/W) = 1112.0 8Ch (R/W) = 1120.0 8Dh (R/W) = 1128.0 8Eh (R/W) = 1136.0 8Fh (R/W) = 1144.0 90h (R/W) = 1152.0 91h (R/W) = 1160.0 92h (R/W) = 1168.0 93h (R/W) = 1176.0 94h (R/W) = 1184.0 95h (R/W) = 1192.0 96h (R/W) = 1200.0 97h (R/W) = 1208.0 98h (R/W) = 1216.0 99h (R/W) = 1224.0 9Ah (R/W) = 1232.0 9Bh (R/W) = 1240.0 9Ch (R/W) = 1248.0 9Dh (R/W) = 1256.0 9Eh (R/W) = 1264.0 9Fh (R/W) = 1272.0 A0h (R/W) = 1280.0 A1h (R/W) = 1288.0 A2h (R/W) = 1296.0 A3h (R/W) = 1304.0 A4h (R/W) = 1312.0 A5h (R/W) = 1320.0 A6h (R/W) = 1328.0 A7h (R/W) = 1336.0 A8h (R/W) = 1344.0 A9h (R/W) = 1352.0 AAh (R/W) = 1360.0 ABh (R/W) = 1368.0 ACh (R/W) = 1376.0 ADh (R/W) = 1384.0 AEh (R/W) = 1392.0 AFh (R/W) = 1400.0 B0h (R/W) = 1408.0 B1h (R/W) = 1416.0 B2h (R/W) = 1424.0 B3h (R/W) = 1432.0 B4h (R/W) = 1440.0 B5h (R/W) = 1448.0 B6h (R/W) = 1456.0 B7h (R/W) = 1464.0 B8h (R/W) = 1472.0 B9h (R/W) = 1480.0 BAh (R/W) = 1488.0 BBh (R/W) = 1496.0 BCh (R/W) = 1504.0 BDh (R/W) = 1512.0 BEh (R/W) = 1520.0 BFh (R/W) = 1528.0 C0h (R/W) = 1536.0 C1h (R/W) = 1544.0 C2h (R/W) = 1552.0 C3h (R/W) = 1560.0 C4h (R/W) = 1568.0 C5h (R/W) = 1576.0 C6h (R/W) = 1584.0 C7h (R/W) = 1592.0 C8h (R/W) = 1600.0 C9h (R/W) = 1608.0 CAh (R/W) = 1616.0 CBh (R/W) = 1624.0 CCh (R/W) = 1632.0 CDh (R/W) = 1640.0 CEh (R/W) = 1648.0 CFh (R/W) = 1656.0 D0h (R/W) = 1664.0 D1h (R/W) = 1672.0 D2h (R/W) = 1680.0 D3h (R/W) = 1688.0 D4h (R/W) = 1696.0 D5h (R/W) = 1704.0 D6h (R/W) = 1712.0 D7h (R/W) = 1720.0 D8h (R/W) = 1728.0 D9h (R/W) = 1736.0 DAh (R/W) = 1744.0 DBh (R/W) = 1752.0 DCh (R/W) = 1760.0 DDh (R/W) = 1768.0 DEh (R/W) = 1776.0 DFh (R/W) = 1784.0 E0h (R/W) = 1792.0 E1h (R/W) = 1800.0 E2h (R/W) = 1808.0 E3h (R/W) = 1816.0 E4h (R/W) = 1824.0 E5h (R/W) = 1832.0 E6h (R/W) = 1840.0 E7h (R/W) = 1848.0 E8h (R/W) = 1856.0 E9h (R/W) = 1864.0 EAh (R/W) = 1872.0 EBh (R/W) = 1880.0 ECh (R/W) = 1888.0 EDh (R/W) = 1896.0 EEh (R/W) = 1904.0 EFh (R/W) = 1912.0 F0h (R/W) = 1920.0 F1h (R/W) = 1928.0 F2h (R/W) = 1936.0 F3h (R/W) = 1944.0 F4h (R/W) = 1952.0 F5h (R/W) = 1960.0 F6h (R/W) = 1968.0 F7h (R/W) = 1976.0 F8h (R/W) = 1984.0 F9h (R/W) = 1992.0 FAh (R/W) = 2000.0 FBh (R/W) = 2008.0 FCh (R/W) = 2016.0 FDh (R/W) = 2024.0 FEh (R/W) = 2032.0 FFh (R/W) = 2040.0 100h (R/W) = 2048.0 101h (R/W) = 2056.0 102h (R/W) = 2064.0 103h (R/W) = 2072.0 104h (R/W) = 2080.0 105h (R/W) = 2088.0 106h (R/W) = 2096.0 107h (R/W) = 2104.0 108h (R/W) = 2112.0 109h (R/W) = 2120.0 10Ah (R/W) = 2128.0 10Bh (R/W) = 2136.0 10Ch (R/W) = 2144.0 10Dh (R/W) = 2152.0 10Eh (R/W) = 2160.0 10Fh (R/W) = 2168.0 110h (R/W) = 2176.0 111h (R/W) = 2184.0 112h (R/W) = 2192.0 113h (R/W) = 2200.0 114h (R/W) = 2208.0 115h (R/W) = 2216.0 116h (R/W) = 2224.0 117h (R/W) = 2232.0 118h (R/W) = 2240.0 119h (R/W) = 2248.0 11Ah (R/W) = 2256.0 11Bh (R/W) = 2264.0 11Ch (R/W) = 2272.0 11Dh (R/W) = 2280.0 11Eh (R/W) = 2288.0 11Fh (R/W) = 2296.0 120h (R/W) = 2304.0 121h (R/W) = 2312.0 122h (R/W) = 2320.0 123h (R/W) = 2328.0 124h (R/W) = 2336.0 125h (R/W) = 2344.0 126h (R/W) = 2352.0 127h (R/W) = 2360.0 128h (R/W) = 2368.0 129h (R/W) = 2376.0 12Ah (R/W) = 2384.0 12Bh (R/W) = 2392.0 12Ch (R/W) = 2400.0 12Dh (R/W) = 2408.0 12Eh (R/W) = 2416.0 12Fh (R/W) = 2424.0 130h (R/W) = 2432.0 131h (R/W) = 2440.0 132h (R/W) = 2448.0 133h (R/W) = 2456.0 134h (R/W) = 2464.0 135h (R/W) = 2472.0 136h (R/W) = 2480.0 137h (R/W) = 2488.0 138h (R/W) = 2496.0 139h (R/W) = 2504.0 13Ah (R/W) = 2512.0 13Bh (R/W) = 2520.0 13Ch (R/W) = 2528.0 13Dh (R/W) = 2536.0 13Eh (R/W) = 2544.0 13Fh (R/W) = 2552.0 140h (R/W) = 2560.0 141h (R/W) = 2568.0 142h (R/W) = 2576.0 143h (R/W) = 2584.0 144h (R/W) = 2592.0 145h (R/W) = 2600.0 146h (R/W) = 2608.0 147h (R/W) = 2616.0 148h (R/W) = 2624.0 149h (R/W) = 2632.0 14Ah (R/W) = 2640.0 14Bh (R/W) = 2648.0 14Ch (R/W) = 2656.0 14Dh (R/W) = 2664.0 14Eh (R/W) = 2672.0 14Fh (R/W) = 2680.0 150h (R/W) = 2688.0 151h (R/W) = 2696.0 152h (R/W) = 2704.0 153h (R/W) = 2712.0 154h (R/W) = 2720.0 155h (R/W) = 2728.0 156h (R/W) = 2736.0 157h (R/W) = 2744.0 158h (R/W) = 2752.0 159h (R/W) = 2760.0 15Ah (R/W) = 2768.0 15Bh (R/W) = 2776.0 15Ch (R/W) = 2784.0 15Dh (R/W) = 2792.0 15Eh (R/W) = 2800.0 15Fh (R/W) = 2808.0 160h (R/W) = 2816.0 161h (R/W) = 2824.0 162h (R/W) = 2832.0 163h (R/W) = 2840.0 164h (R/W) = 2848.0 165h (R/W) = 2856.0 166h (R/W) = 2864.0 167h (R/W) = 2872.0 168h (R/W) = 2880.0 169h (R/W) = 2888.0 16Ah (R/W) = 2896.0 16Bh (R/W) = 2904.0 16Ch (R/W) = 2912.0 16Dh (R/W) = 2920.0 16Eh (R/W) = 2928.0 16Fh (R/W) = 2936.0 170h (R/W) = 2944.0 171h (R/W) = 2952.0 172h (R/W) = 2960.0 173h (R/W) = 2968.0 174h (R/W) = 2976.0 175h (R/W) = 2984.0 176h (R/W) = 2992.0 177h (R/W) = 3000.0 178h (R/W) = 3008.0 179h (R/W) = 3016.0 17Ah (R/W) = 3024.0 17Bh (R/W) = 3032.0 17Ch (R/W) = 3040.0 17Dh (R/W) = 3048.0 17Eh (R/W) = 3056.0 17Fh (R/W) = 3064.0 180h (R/W) = 3072.0 181h (R/W) = 3080.0 182h (R/W) = 3088.0 183h (R/W) = 3096.0 184h (R/W) = 3104.0 185h (R/W) = 3112.0 186h (R/W) = 3120.0 187h (R/W) = 3128.0 188h (R/W) = 3136.0 189h (R/W) = 3144.0 18Ah (R/W) = 3152.0 18Bh (R/W) = 3160.0 18Ch (R/W) = 3168.0 18Dh (R/W) = 3176.0 18Eh (R/W) = 3184.0 18Fh (R/W) = 3192.0 190h (R/W) = 3200.0 191h (R/W) = 3208.0 192h (R/W) = 3216.0 193h (R/W) = 3224.0 194h (R/W) = 3232.0 195h (R/W) = 3240.0 196h (R/W) = 3248.0 197h (R/W) = 3256.0 198h (R/W) = 3264.0 199h (R/W) = 3272.0 19Ah (R/W) = 3280.0 19Bh (R/W) = 3288.0 19Ch (R/W) = 3296.0 19Dh (R/W) = 3304.0 19Eh (R/W) = 3312.0 19Fh (R/W) = 3320.0 1A0h (R/W) = 3328.0 1A1h (R/W) = 3336.0 1A2h (R/W) = 3344.0 1A3h (R/W) = 3352.0 1A4h (R/W) = 3360.0 1A5h (R/W) = 3368.0 1A6h (R/W) = 3376.0 1A7h (R/W) = 3384.0 1A8h (R/W) = 3392.0 1A9h (R/W) = 3400.0 1AAh (R/W) = 3408.0 1ABh (R/W) = 3416.0 1ACh (R/W) = 3424.0 1ADh (R/W) = 3432.0 1AEh (R/W) = 3440.0 1AFh (R/W) = 3448.0 1B0h (R/W) = 3456.0 1B1h (R/W) = 3464.0 1B2h (R/W) = 3472.0 1B3h (R/W) = 3480.0 1B4h (R/W) = 3488.0 1B5h (R/W) = 3496.0 1B6h (R/W) = 3504.0 1B7h (R/W) = 3512.0 1B8h (R/W) = 3520.0 1B9h (R/W) = 3528.0 1BAh (R/W) = 3536.0 1BBh (R/W) = 3544.0 1BCh (R/W) = 3552.0 1BDh (R/W) = 3560.0 1BEh (R/W) = 3568.0 1BFh (R/W) = 3576.0 1C0h (R/W) = 3584.0 1C1h (R/W) = 3592.0 1C2h (R/W) = 3600.0 1C3h (R/W) = 3608.0 1C4h (R/W) = 3616.0 1C5h (R/W) = 3624.0 1C6h (R/W) = 3632.0 1C7h (R/W) = 3640.0 1C8h (R/W) = 3648.0 1C9h (R/W) = 3656.0 1CAh (R/W) = 3664.0 1CBh (R/W) = 3672.0 1CCh (R/W) = 3680.0 1CDh (R/W) = 3688.0 1CEh (R/W) = 3696.0 1CFh (R/W) = 3704.0 1D0h (R/W) = 3712.0 1D1h (R/W) = 3720.0 1D2h (R/W) = 3728.0 1D3h (R/W) = 3736.0 1D4h (R/W) = 3744.0 1D5h (R/W) = 3752.0 1D6h (R/W) = 3760.0 1D7h (R/W) = 3768.0 1D8h (R/W) = 3776.0 1D9h (R/W) = 3784.0 1DAh (R/W) = 3792.0 1DBh (R/W) = 3800.0 1DCh (R/W) = 3808.0 1DDh (R/W) = 3816.0 1DEh (R/W) = 3824.0 1DFh (R/W) = 3832.0 1E0h (R/W) = 3840.0 1E1h (R/W) = 3848.0 1E2h (R/W) = 3856.0 1E3h (R/W) = 3864.0 1E4h (R/W) = 3872.0 1E5h (R/W) = 3880.0 1E6h (R/W) = 3888.0 1E7h (R/W) = 3896.0 1E8h (R/W) = 3904.0 1E9h (R/W) = 3912.0 1EAh (R/W) = 3920.0 1EBh (R/W) = 3928.0 1ECh (R/W) = 3936.0 1EDh (R/W) = 3944.0 1EEh (R/W) = 3952.0 1EFh (R/W) = 3960.0 1F0h (R/W) = 3968.0 1F1h (R/W) = 3976.0 1F2h (R/W) = 3984.0 1F3h (R/W) = 3992.0 1F4h (R/W) = 4000.0 1F5h (R/W) = 4008.0 1F6h (R/W) = 4016.0 1F7h (R/W) = 4024.0 1F8h (R/W) = 4032.0 1F9h (R/W) = 4040.0 1FAh (R/W) = 4048.0 1FBh (R/W) = 4056.0 1FCh (R/W) = 4064.0 1FDh (R/W) = 4072.0 1FEh (R/W) = 4080.0 1FFh (R/W) = 4088.0 200h (R/W) = 4095.0 |
USBCONTIM is shown in Figure 32-23 and described in Table 32-26.
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USB Connect Timing
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WTCON | WTID | ||||||
R/W-1h | R/W-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | WTCON | R/W | 1h | The wait ID field configures the delay required from the enable of the ID detection to when the ID value is valid, in units of 4.369 ms. The default corresponds to 52.43 ms. Reset type: SYSRSn |
3-0 | WTID | R/W | 1h | The connect wait field configures the wait required to allow for the user's connect/disconnect filter, in units of 533.3 ns. The default corresponds to 2.667 us. Reset type: SYSRSn |
USBFSEOF is shown in Figure 32-24 and described in Table 32-27.
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USB Full-Speed Last Transaction to End of Frame Timing
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FSEOFG | |||||||
R/W-77h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | FSEOFG | R/W | 77h | The full-speed end-of-frame gap field is used during full-speed transactions to configure the gap between the last transaction and the End-of-Frame (EOF), in units of 533.3 ns. The default corresponds to 63.46 us. Reset type: SYSRSn |
USBLSEOF is shown in Figure 32-25 and described in Table 32-28.
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USB Low-Speed Last Transaction to End of Frame Timing
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LSEOFG | |||||||
R/W-72h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LSEOFG | R/W | 72h | The low-speed end-of-frame gap field is used during low-speed transactions to set the gap between the last transaction and the End-of-Frame (EOF), in units of 1.067 us. The default corresponds to 121.6 us. Reset type: SYSRSn |
USBTXFUNCADDR0 is shown in Figure 32-26 and described in Table 32-29.
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USB Transmit Functional Address Endpoint 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBTXHUBADDR0 is shown in Figure 32-27 and described in Table 32-30.
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USB Transmit Hub Address Endpoint 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBTXHUBPORT0 is shown in Figure 32-28 and described in Table 32-31.
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USB Transmit Hub Port Endpoint 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Hub Port specifies the USB hub port number. Reset type: SYSRSn |
USBTXFUNCADDR1 is shown in Figure 32-29 and described in Table 32-32.
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USB Transmit Functional Address Endpoint 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBTXHUBADDR1 is shown in Figure 32-30 and described in Table 32-33.
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USB Transmit Hub Address Endpoint 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBTXHUBPORT1 is shown in Figure 32-31 and described in Table 32-34.
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USB Transmit Hub Port Endpoint 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Hub Port specifies the USB hub port number. Reset type: SYSRSn |
USBRXFUNCADDR1 is shown in Figure 32-32 and described in Table 32-35.
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USB Receive Functional Address Endpoint 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBRXHUBADDR1 is shown in Figure 32-33 and described in Table 32-36.
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USB Receive Hub Address Endpoint 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MULTTRAN | ADDR | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MULTTRAN | R/W | 0h | Hub has Multiple Translators Reset type: SYSRSn 0h (R/W) = Clear to indicate that the hub has a single transaction translator. 1h (R/W) = Set to indicate that the hub has multiple transaction translators. |
6-0 | ADDR | R/W | 0h | Hub Address Reset type: SYSRSn |
USBRXHUBPORT1 is shown in Figure 32-34 and described in Table 32-37.
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USB Receive Hub Port Endpoint 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Hub Address Reset type: SYSRSn |
USBTXFUNCADDR2 is shown in Figure 32-35 and described in Table 32-38.
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USB Transmit Functional Address Endpoint 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBTXHUBADDR2 is shown in Figure 32-36 and described in Table 32-39.
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USB Transmit Hub Address Endpoint 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBTXHUBPORT2 is shown in Figure 32-37 and described in Table 32-40.
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USB Transmit Hub Port Endpoint 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Hub Port specifies the USB hub port number. Reset type: SYSRSn |
USBRXFUNCADDR2 is shown in Figure 32-38 and described in Table 32-41.
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USB Receive Functional Address Endpoint 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBRXHUBADDR2 is shown in Figure 32-39 and described in Table 32-42.
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USB Receive Hub Address Endpoint 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MULTTRAN | ADDR | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MULTTRAN | R/W | 0h | Hub has Multiple Translators Reset type: SYSRSn 0h (R/W) = Clear to indicate that the hub has a single transaction translator. 1h (R/W) = Set to indicate that the hub has multiple transaction translators. |
6-0 | ADDR | R/W | 0h | Hub Address Reset type: SYSRSn |
USBRXHUBPORT2 is shown in Figure 32-40 and described in Table 32-43.
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USB Receive Hub Port Endpoint 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Hub Address Reset type: SYSRSn |
USBTXFUNCADDR3 is shown in Figure 32-41 and described in Table 32-44.
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USB Transmit Functional Address Endpoint 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBTXHUBADDR3 is shown in Figure 32-42 and described in Table 32-45.
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USB Transmit Hub Address Endpoint 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBTXHUBPORT3 is shown in Figure 32-43 and described in Table 32-46.
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USB Transmit Hub Port Endpoint 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Hub Port specifies the USB hub port number. Reset type: SYSRSn |
USBRXFUNCADDR3 is shown in Figure 32-44 and described in Table 32-47.
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USB Receive Functional Address Endpoint 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Device Address specifies the USB bus address for the target Device. Reset type: SYSRSn |
USBRXHUBADDR3 is shown in Figure 32-45 and described in Table 32-48.
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USB Receive Hub Address Endpoint 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MULTTRAN | ADDR | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MULTTRAN | R/W | 0h | Hub has Multiple Translators Reset type: SYSRSn 0h (R/W) = Clear to indicate that the hub has a single transaction translator. 1h (R/W) = Set to indicate that the hub has multiple transaction translators. |
6-0 | ADDR | R/W | 0h | Hub Address Reset type: SYSRSn |
USBRXHUBPORT3 is shown in Figure 32-46 and described in Table 32-49.
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USB Receive Hub Port Endpoint 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | ADDR | R/W | 0h | Hub Address Reset type: SYSRSn |
USBCSRL0 is shown in Figure 32-47 and described in Table 32-50.
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USB Control and Status Endpoint 0 Low
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENDC_NAKTO | RXRDYC_STATUS | STALL_RQPKT | SETEND_ERROR | DATAEND_SETUP | STALLED | TXRDY | RXRDY |
W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SETENDC_NAKTO | W1C | 0h | NAK Timeout. Software must clear this bit to allow the endpoint to continue. Reset type: SYSRSn 0h (R/W) = No timeout 1h (R/W) = Indicates that endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the USBNAKLMT register |
6 | RXRDYC_STATUS | R/W | 0h | Status Packet. Setting this bit ensures that the DT bit is set in the USBCSRH0 register so that a DATA1 packet is used for the STATUS stage transaction. Reset type: SYSRSn 0h (R/W) = No transaction 1h (R/W) = The Endpoint 1 transmit interrupt is asserted. |
5 | STALL_RQPKT | R/W | 0h | Request Packet. This bit is cleared when the RXRDY bit is set. Reset type: SYSRSn 0h (R/W) = No request 1h (R/W) = Initiates a STATUS stage transaction. This bit must be set at the same time as the TXRDY or REQPKT bit is set. This bit is automatically cleared when the STATUS stage is over. |
4 | SETEND_ERROR | R/W | 0h | Error. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Three attempts have been made to perform a transaction with no response from the peripheral. The EP0 bit in the USBTXIS register is also set in this situation. |
3 | DATAEND_SETUP | R/W | 0h | Setup Packet. Setting this bit always clears the DT bit in the USBCSRH0 register to send a DATA0 packet. Reset type: SYSRSn 0h (R/W) = Sends an OUT token. 1h (R/W) = Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set. |
2 | STALLED | R/W | 0h | Endpoint Stalled. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No handshake has been received. 1h (R/W) = A STALL handshake has been received |
1 | TXRDY | R/W | 0h | Transmit Packet Ready. If both the TXRDY and SETUP bits are set, a setup packet is sent. If just TXRDY is set, an OUT packet is sent. Reset type: SYSRSn 0h (R/W) = No transmit packet is ready. 1h (R/W) = Software sets this bit after loading a data packet into the TX FIFO. The EP0 bit in the USBTXIS register is also set in this situation. |
0 | RXRDY | R/W | 0h | Receive Packet Ready. Software must clear this bit after he packet has been read from the FIFO to acknowledge that the data has been read from the FIFO. Reset type: SYSRSn 0h (R/W) = No receive packet has been received. 1h (R/W) = Indicates that a data packet has been received in the RX FIFO. The EP0 bit in the USBTXIS register is also set in this situation. |
USBCSRH0 is shown in Figure 32-48 and described in Table 32-51.
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USB Control and Status Endpoint 0 High
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DTWE | DT | FLUSH | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R | 0h | Reserved |
2 | DTWE | R/W | 0h | Data Toggle Write Enable. This bit is automatically cleared once the new value is written. Reset type: SYSRSn 0h (R/W) = The DT bit cannot be written. 1h (R/W) = Enables the current state of the endpoint 0 data toggle to be written (see DT bit). |
1 | DT | R/W | 0h | Data Toggle. When read, this bit indicates the current state of the endpoint 0 data toggle. If DTWE is set, this bit may be written with the required setting of the data toggle. If DTWE is Low, this bit cannot be written. Care should be taken when writing to this bit as it should only be changed to RESET USB endpoint 0. Reset type: SYSRSn |
0 | FLUSH | R/W | 0h | Flush FIFO. This bit is automatically cleared after the flush is performed. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and the TXRDY/RXRDY bit is cleared. Note: This bit should only be set when TXRDY/RXRDY is set. At other times, it may cause data to be corrupted.. |
USBCOUNT0 is shown in Figure 32-49 and described in Table 32-52.
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USB Receive Byte Count Endpoint 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-0 | COUNT | R/W | 0h | FIFO Count. COUNT is a read-only value that indicates the number of received data bytes in the endpoint 0 FIFO. Reset type: SYSRSn |
USBTYPE0 is shown in Figure 32-50 and described in Table 32-53.
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USB Type Endpoint 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPEED | RESERVED | ||||||
R/W-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SPEED | R/W | 0h | Operating Speed specifies the operating speed of the target Device. If selected, the target is assumed to have the same connection speed as the USB controller. Reset type: SYSRSn 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Full 3h (R/W) = Low |
5-0 | RESERVED | R | 0h | Reserved |
USBNAKLMT is shown in Figure 32-51 and described in Table 32-54.
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USB NAK Limit
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NAKLMT | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0h | Reserved |
4-0 | NAKLMT | R/W | 0h | EP0 NAK Limit specifies the number of frames after receiving a stream of NAK responses. Reset type: SYSRSn |
USBTXMAXP1 is shown in Figure 32-52 and described in Table 32-55.
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USB Maximum Transmit Data Endpoint 1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAXLOAD | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXLOAD | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10-0 | MAXLOAD | R/W | 0h | Maximum Payload specifies the maximum payload in bytes per transaction. Reset type: SYSRSn |
USBTXCSRL1 is shown in Figure 32-53 and described in Table 32-56.
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USB Transmit Control and Status Endpoint 1 Low
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAKTO | CLRDT | STALLED | STALL_SETUP | FLUSH | UNDRN_ERROR1 | FIFONE | TXRDY |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | NAKTO | R/W | 0h | NAK Timeout. Software must clear this bit to allow the endpoint to continue. Reset type: SYSRSn 0h (R/W) = No timeout 1h (R/W) = Bulk endpoints only: Indicates that the transmit endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBTXINTERVAL[n] register. |
6 | CLRDT | R/W | 0h | Clear DataToggle Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Writing a 1 to this bit clears the DT bit in the USBTXCSRH[n] register. |
5 | STALLED | R/W | 0h | Endpoint Stalled. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = A STALL handshake has not been received 1h (R/W) = Indicates that a STALL handshake has been received. When this bit is set, any DMA request that is in progress is stopped, the FIFO is completely flushed, and the TXRDY bit is cleared. |
4 | STALL_SETUP | R/W | 0h | Setup Packet. Reset type: SYSRSn 0h (R/W) = No SETUP token is sent. 1h (R/W) = Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set. Note: Setting this bit also clears the DT bit in the USBTXCSRH[n] register. |
3 | FLUSH | R/W | 0h | Flush FIFO. This bit can be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation. Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be corrupted. |
2 | UNDRN_ERROR1 | R/W | 0h | Error. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Three attempts have been made to send a packet and no handshake packet has been received. The TXRDY bit is cleared, the EPn bit in the USBTXIS register is set, and the FIFO is completely flushed inthis situation. Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode. |
1 | FIFONE | R/W | 0h | FIFO Not Empty Reset type: SYSRSn 0h (R/W) = The FIFO is empty 1h (R/W) = At least one packet is in the transmit FIFO. |
0 | TXRDY | R/W | 0h | Transmit Packet Ready. This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO. Reset type: SYSRSn 0h (R/W) = No transmit packet is ready. 1h (R/W) = Software sets this bit after loading a data packet into the TX FIFO. |
USBTXCSRH1 is shown in Figure 32-54 and described in Table 32-57.
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USB Transmit Control and Status Endpoint 1 High
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOSET | ISO | MODE | DMAEN | FDT | DMAMOD | DTWE | DT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AUTOSET | R/W | 0h | Auto Set Reset type: SYSRSn 0h (R/W) = The TXRDY bit must be set manually. 1h (R/W) = Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in USBTXMAXP[n]) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then the TXRDY bit must be set manually. |
6 | ISO | R/W | 0h | Isochronous Transfers Reset type: SYSRSn 0h (R/W) = Enables the transmit endpoint for bulk or interrupt transfers. 1h (R/W) = Enables the transmit endpoint for isochronous transfers. |
5 | MODE | R/W | 0h | Mode Note: This bit only has an effect when the same endpoint FIFO is used for both transmit and receive transactions. Reset type: SYSRSn 0h (R/W) = Enables the endpoint direction as RX. 1h (R/W) = Enables the endpoint direction as TX. |
4 | DMAEN | R/W | 0h | DMA Request Enable Note: Three TX and three /RX endpoints can be connected to the DMA module. If this bit is set for a particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly Reset type: SYSRSn 0h (R/W) = Disables the DMA request for the transmit endpoint. 1h (R/W) = Enables the DMA request for the transmit endpoint. |
3 | FDT | R/W | 0h | Force Data Toggle Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints. Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be corrupted. |
2 | DMAMOD | R/W | 0h | DMA Request Mode Reset type: SYSRSn 0h (R/W) = An interrupt is generated after every DMA packet transfer. 1h (R/W) = An interrupt is generated only after the entire DMA transfer is complete. Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode. |
1 | DTWE | R/W | 0h | Data Toggle Write Enable. This bit is automatically cleared once the new value is written. Reset type: SYSRSn 0h (R/W) = The DT bit cannot be written. 1h (R/W) = Enables the current state of the transmit endpoint data to be written (see DT bit). |
0 | DT | R/W | 0h | Data Toggle. When read, this bit indicates the current state of the transmit endpoint data toggle. If DTWE is High, this bit can be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the transmit endpoint. Reset type: SYSRSn |
USBRXMAXP1 is shown in Figure 32-55 and described in Table 32-58.
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USB Maximum Receive Data Endpoint 1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAXLOAD | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXLOAD | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10-0 | MAXLOAD | R/W | 0h | Maximum Payload specifies the maximum payload in bytes per transaction. Reset type: SYSRSn |
USBRXCSRL1 is shown in Figure 32-56 and described in Table 32-59.
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USB Receive Control and Status Endpoint 1 Low
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRDT | STALLED | STALLREQPKT | FLUSH | DATAERRNAKTO | OVERERROR1 | FULL | RXRDY |
W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLRDT | W1C | 0h | Clear Data Toggle. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Writing a 1 to this bit clears the DT bit in the USBRXCSRH[n] register. |
6 | STALLED | R/W | 0h | Endpoint Stalled. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No handshake has been received. 1h (R/W) = A STALL handshake has been received. The EPn bit in the USBRXIS register is also set. |
5 | STALLREQPKT | R/W | 0h | Request Packet. This bit is cleared when the RXRDY bit is set. Reset type: SYSRSn 0h (R/W) = No request 1h (R/W) = Requests an IN transaction. |
4 | FLUSH | R/W | 0h | Flush FIFO. If the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Note:This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be corrupted. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Flushes the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared |
3 | DATAERRNAKTO | R/W | 0h | Data Error / NAK Timeout Reset type: SYSRSn 0h (R/W) = Normal operation 1h (R/W) = Isochronous endpoints only: I ndicates that RXRDY is set and the data packet has a CRC or bit-stuff error. This bit is cleared when RXRDY is cleared. Bulk endpoints only: Indicates that the receive endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBRXINTERVAL[n] register. Software must clear this bit to allow the endpoint to continue. |
2 | OVERERROR1 | R/W | 0h | Error. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Three attempts have been made to receive a packet and no data packet has been received. The Epn bit in the USBRXIS register is set in this situation. |
1 | FULL | R/W | 0h | FIFO Full Reset type: SYSRSn 0h (R/W) = The receive FIFO is not full. 1h (R/W) = No more packets can be loaded into the receive FIFO. |
0 | RXRDY | R/W | 0h | Receive Packet Ready. If the AUTOCLR bit in the USBRXCSRH[n] register is set, then the this bit is automatically cleared when a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO Reset type: SYSRSn 0h (R/W) = No data packet has been received. 1h (R/W) = Indicates that a data packet has been received. The EPn bit in the USBTXIS register is also set in this situation |
USBRXCSRH1 is shown in Figure 32-57 and described in Table 32-60.
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USB Receive Control and Status Endpoint 1 High
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOCL | ISOAUTORQ | DMAEN | DISNYETPIDERR | DMAMOD | DTWE | DT | RESERVED |
W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AUTOCL | W1C | 0h | Auto Clear Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using DMA to unload the receive FIFO as data is read from the receive FIFO in 4-byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXP[n] register, |
6 | ISOAUTORQ | R/W | 0h | Auto Request Note: This bit is automatically cleared when a short packet is received. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared |
5 | DMAEN | R/W | 0h | DMA Request Enable Note: Three TX and three RX endpoints can be connected to the DMA module. If this bit is set for a particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly Reset type: SYSRSn 0h (R/W) = Disables the DMA request for the receive endpoint. 1h (R/W) = Enables the DMA request for the receive endpoint. |
4 | DISNYETPIDERR | R/W | 0h | PID Error. This bit is ignored in bulk or interrupt transactions. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Indicates a PID error in the received packet of an isochronous transaction. |
3 | DMAMOD | R/W | 0h | DMAMOD Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. Reset type: SYSRSn 0h (R/W) = An interrupt is generated after every DMA packet transfer. 1h (R/W) = An interrupt is generated only after the entire DMA transfer is complete. |
2 | DTWE | R/W | 0h | Data Toggle Write Enable. This bit is automatically cleared once the new value is written. Reset type: SYSRSn 0h (R/W) = The DT bit cannot be written. 1h (R/W) = Enables the current state of the receive endpoint data to be written (see DT bit). |
1 | DT | R/W | 0h | Data Toggle. When read, this bit indicates the current state of the receive data toggle. If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the receive endpoint. Reset type: SYSRSn |
0 | RESERVED | R/W | 0h | Reserved |
USBRXCOUNT1 is shown in Figure 32-58 and described in Table 32-61.
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USB Receive Byte Count Endpoint 1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COUNT | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12-0 | COUNT | R | 0h | Receive Packet Count indicates the number of bytes in the receive packet. Reset type: SYSRSn |
USBTXTYPE1 is shown in Figure 32-59 and described in Table 32-62.
Return to the Summary Table.
USB Host Transmit Configure Type Endpoint 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPEED | PROTO | TEP | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SPEED | R/W | 0h | Operating Speed. This bit field specifies the operating speed of the target Device: Reset type: SYSRSn 0h (R/W) = Default. The target is assumed to be using the same connection speed as the USB controller. 1h (R/W) = Reserved 2h (R/W) = Full 3h (R/W) = Low |
5-4 | PROTO | R/W | 0h | Protocol. Software must configure this bit field to select the required protocol for the transmit endpoint: Reset type: SYSRSn 0h (R/W) = Control 1h (R/W) = isochronous 2h (R/W) = Bulk 3h (R/W) = Interrupt |
3-0 | TEP | R/W | 0h | Target Endpoint Number. Software must configure this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB controller during Device enumeration. Reset type: SYSRSn |
USBTXINTERVAL1 is shown in Figure 32-60 and described in Table 32-63.
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USB Host Transmit Interval Endpoint 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXPOLLNAKLMT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TXPOLLNAKLMT | R/W | 0h | TX Polling / NAK Limit The polling interval for interrupt/isochronous transfers the NAK limit for bulk transfers. Reset type: SYSRSn |
USBRXTYPE1 is shown in Figure 32-61 and described in Table 32-64.
Return to the Summary Table.
USB Host Configure Receive Type Endpoint 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPEED | PROTO | TEP | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SPEED | R/W | 0h | Operating Speed. This bit field specifies the operating speed of the target Device: Reset type: SYSRSn 0h (R/W) = Default. The target is assumed to be using the same connection speed as the USB controller. 1h (R/W) = Reserved 2h (R/W) = Full 3h (R/W) = Low |
5-4 | PROTO | R/W | 0h | Protocol. Software must configure this bit field to select the required protocol for the transmit endpoint: Reset type: SYSRSn 0h (R/W) = Control 1h (R/W) = isochronous 2h (R/W) = Bulk 3h (R/W) = Interrupt |
3-0 | TEP | R/W | 0h | Target Endpoint Number. Software must configure this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB controller during Device enumeration. Reset type: SYSRSn |
USBRXINTERVAL1 is shown in Figure 32-62 and described in Table 32-65.
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USB Host Receive Polling Interval Endpoint 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXPOLLNAKLMT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | RXPOLLNAKLMT | R/W | 0h | RX Polling / NAK Limit The polling interval for interrupt/isochronous transfers the NAK limit for bulk transfers. Reset type: SYSRSn |
USBTXMAXP2 is shown in Figure 32-63 and described in Table 32-66.
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USB Maximum Transmit Data Endpoint 2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAXLOAD | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXLOAD | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10-0 | MAXLOAD | R/W | 0h | Maximum Payload specifies the maximum payload in bytes per transaction. Reset type: SYSRSn |
USBTXCSRL2 is shown in Figure 32-64 and described in Table 32-67.
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USB Transmit Control and Status Endpoint 2 Low
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAKTO | CLRDT | STALLED | STALL_SETUP | FLUSH | UNDRNERROR2 | FIFONE | TXRDY |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | NAKTO | R/W | 0h | NAK Timeout. Software must clear this bit to allow the endpoint to continue. Reset type: SYSRSn 0h (R/W) = No timeout 1h (R/W) = Bulk endpoints only: Indicates that the transmit endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBTXINTERVAL[n] register. |
6 | CLRDT | R/W | 0h | Clear DataToggle Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Writing a 1 to this bit clears the DT bit in the USBTXCSRH[n] register. |
5 | STALLED | R/W | 0h | Endpoint Stalled. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = A STALL handshake has not been received 1h (R/W) = Indicates that a STALL handshake has been received. When this bit is set, any DMA request that is in progress is stopped, the FIFO is completely flushed, and the TXRDY bit is cleared. |
4 | STALL_SETUP | R/W | 0h | Setup Packet. Reset type: SYSRSn 0h (R/W) = No SETUP token is sent. 1h (R/W) = Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set. Note: Setting this bit also clears the DT bit in the USBTXCSRH[n] register. |
3 | FLUSH | R/W | 0h | Flush FIFO. This bit can be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation. Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be corrupted. |
2 | UNDRNERROR2 | R/W | 0h | Error. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Three attempts have been made to send a packet and no handshake packet has been received. The TXRDY bit is cleared, the EPn bit in the USBTXIS register is set, and the FIFO is completely flushed inthis situation. Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode. |
1 | FIFONE | R/W | 0h | FIFO Not Empty Reset type: SYSRSn 0h (R/W) = The FIFO is empty 1h (R/W) = At least one packet is in the transmit FIFO. |
0 | TXRDY | R/W | 0h | Transmit Packet Ready. This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO. Reset type: SYSRSn 0h (R/W) = No transmit packet is ready. 1h (R/W) = Software sets this bit after loading a data packet into the TX FIFO. |
USBTXCSRH2 is shown in Figure 32-65 and described in Table 32-68.
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USB Transmit Control and Status Endpoint 2 High
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOSET | ISO | MODE | DMAEN | FDT | DMAMOD | DTWE | DT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AUTOSET | R/W | 0h | Auto Set Reset type: SYSRSn 0h (R/W) = The TXRDY bit must be set manually. 1h (R/W) = Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in USBTXMAXP[n]) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then the TXRDY bit must be set manually. |
6 | ISO | R/W | 0h | Isochronous Transfers Reset type: SYSRSn 0h (R/W) = Enables the transmit endpoint for bulk or interrupt transfers. 1h (R/W) = Enables the transmit endpoint for isochronous transfers. |
5 | MODE | R/W | 0h | Mode Note: This bit only has an effect when the same endpoint FIFO is used for both transmit and receive transactions. Reset type: SYSRSn 0h (R/W) = Enables the endpoint direction as RX. 1h (R/W) = Enables the endpoint direction as TX. |
4 | DMAEN | R/W | 0h | DMA Request Enable Note: Three TX and three /RX endpoints can be connected to the DMA module. If this bit is set for a particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly Reset type: SYSRSn 0h (R/W) = Disables the DMA request for the transmit endpoint. 1h (R/W) = Enables the DMA request for the transmit endpoint. |
3 | FDT | R/W | 0h | Force Data Toggle Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints. Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be corrupted. |
2 | DMAMOD | R/W | 0h | DMA Request Mode Reset type: SYSRSn 0h (R/W) = An interrupt is generated after every DMA packet transfer. 1h (R/W) = An interrupt is generated only after the entire DMA transfer is complete. Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode. |
1 | DTWE | R/W | 0h | Data Toggle Write Enable. This bit is automatically cleared once the new value is written. Reset type: SYSRSn 0h (R/W) = The DT bit cannot be written. 1h (R/W) = Enables the current state of the transmit endpoint data to be written (see DT bit). |
0 | DT | R/W | 0h | Data Toggle. When read, this bit indicates the current state of the transmit endpoint data toggle. If DTWE is High, this bit can be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the transmit endpoint. Reset type: SYSRSn |
USBRXMAXP2 is shown in Figure 32-66 and described in Table 32-69.
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USB Maximum Receive Data Endpoint 2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAXLOAD | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXLOAD | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10-0 | MAXLOAD | R/W | 0h | Maximum Payload specifies the maximum payload in bytes per transaction. Reset type: SYSRSn |
USBRXCSRL2 is shown in Figure 32-67 and described in Table 32-70.
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USB Receive Control and Status Endpoint 2 Low
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRDT | STALLED | STALLREQPKT | FLUSH | DATAERRNAKTO | OVERERROR2 | FULL | RXRDY |
W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLRDT | W1C | 0h | Clear Data Toggle. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Writing a 1 to this bit clears the DT bit in the USBRXCSRH[n] register. |
6 | STALLED | R/W | 0h | Endpoint Stalled. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No handshake has been received. 1h (R/W) = A STALL handshake has been received. The EPn bit in the USBRXIS register is also set. |
5 | STALLREQPKT | R/W | 0h | Request Packet. This bit is cleared when the RXRDY bit is set. Reset type: SYSRSn 0h (R/W) = No request 1h (R/W) = Requests an IN transaction. |
4 | FLUSH | R/W | 0h | Flush FIFO. If the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Note:This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be corrupted. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Flushes the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared |
3 | DATAERRNAKTO | R/W | 0h | Data Error / NAK Timeout Reset type: SYSRSn 0h (R/W) = Normal operation 1h (R/W) = Isochronous endpoints only: I ndicates that RXRDY is set and the data packet has a CRC or bit-stuff error. This bit is cleared when RXRDY is cleared. Bulk endpoints only: Indicates that the receive endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBRXINTERVAL[n] register. Software must clear this bit to allow the endpoint to continue. |
2 | OVERERROR2 | R/W | 0h | Error. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Three attempts have been made to receive a packet and no data packet has been received. The Epn bit in the USBRXIS register is set in this situation. |
1 | FULL | R/W | 0h | FIFO Full Reset type: SYSRSn 0h (R/W) = The receive FIFO is not full. 1h (R/W) = No more packets can be loaded into the receive FIFO. |
0 | RXRDY | R/W | 0h | Receive Packet Ready. If the AUTOCLR bit in the USBRXCSRH[n] register is set, then the this bit is automatically cleared when a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO Reset type: SYSRSn 0h (R/W) = No data packet has been received. 1h (R/W) = Indicates that a data packet has been received. The EPn bit in the USBTXIS register is also set in this situation |
USBRXCSRH2 is shown in Figure 32-68 and described in Table 32-71.
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USB Receive Control and Status Endpoint 2 High
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOCL | ISOAUTORQ | DMAEN | DISNYETPIDERR | DMAMOD | DTWE | DT | RESERVED |
W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AUTOCL | W1C | 0h | Auto Clear Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using DMA to unload the receive FIFO as data is read from the receive FIFO in 4-byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXP[n] register, |
6 | ISOAUTORQ | R/W | 0h | Auto Request Note: This bit is automatically cleared when a short packet is received. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared |
5 | DMAEN | R/W | 0h | DMA Request Enable Note: Three TX and three RX endpoints can be connected to the DMA module. If this bit is set for a particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly Reset type: SYSRSn 0h (R/W) = Disables the DMA request for the receive endpoint. 1h (R/W) = Enables the DMA request for the receive endpoint. |
4 | DISNYETPIDERR | R/W | 0h | PID Error. This bit is ignored in bulk or interrupt transactions. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Indicates a PID error in the received packet of an isochronous transaction. |
3 | DMAMOD | R/W | 0h | DMAMOD Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. Reset type: SYSRSn 0h (R/W) = An interrupt is generated after every DMA packet transfer. 1h (R/W) = An interrupt is generated only after the entire DMA transfer is complete. |
2 | DTWE | R/W | 0h | Data Toggle Write Enable. This bit is automatically cleared once the new value is written. Reset type: SYSRSn 0h (R/W) = The DT bit cannot be written. 1h (R/W) = Enables the current state of the receive endpoint data to be written (see DT bit). |
1 | DT | R/W | 0h | Data Toggle. When read, this bit indicates the current state of the receive data toggle. If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the receive endpoint. Reset type: SYSRSn |
0 | RESERVED | R/W | 0h | Reserved |
USBRXCOUNT2 is shown in Figure 32-69 and described in Table 32-72.
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USB Receive Byte Count Endpoint 2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COUNT | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12-0 | COUNT | R | 0h | Receive Packet Count indicates the number of bytes in the receive packet. Reset type: SYSRSn |
USBTXTYPE2 is shown in Figure 32-70 and described in Table 32-73.
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USB Host Transmit Configure Type Endpoint 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPEED | PROTO | TEP | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SPEED | R/W | 0h | Operating Speed. This bit field specifies the operating speed of the target Device: Reset type: SYSRSn 0h (R/W) = Default. The target is assumed to be using the same connection speed as the USB controller. 1h (R/W) = Reserved 2h (R/W) = Full 3h (R/W) = Low |
5-4 | PROTO | R/W | 0h | Protocol. Software must configure this bit field to select the required protocol for the transmit endpoint: Reset type: SYSRSn 0h (R/W) = Control 1h (R/W) = isochronous 2h (R/W) = Bulk 3h (R/W) = Interrupt |
3-0 | TEP | R/W | 0h | Target Endpoint Number. Software must configure this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB controller during Device enumeration. Reset type: SYSRSn |
USBTXINTERVAL2 is shown in Figure 32-71 and described in Table 32-74.
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USB Host Transmit Interval Endpoint 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXPOLLNAKLMT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TXPOLLNAKLMT | R/W | 0h | TX Polling / NAK Limit The polling interval for interrupt/isochronous transfers the NAK limit for bulk transfers. Reset type: SYSRSn |
USBRXTYPE2 is shown in Figure 32-72 and described in Table 32-75.
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USB Host Configure Receive Type Endpoint 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPEED | PROTO | TEP | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SPEED | R/W | 0h | Operating Speed. This bit field specifies the operating speed of the target Device: Reset type: SYSRSn 0h (R/W) = Default. The target is assumed to be using the same connection speed as the USB controller. 1h (R/W) = Reserved 2h (R/W) = Full 3h (R/W) = Low |
5-4 | PROTO | R/W | 0h | Protocol. Software must configure this bit field to select the required protocol for the transmit endpoint: Reset type: SYSRSn 0h (R/W) = Control 1h (R/W) = isochronous 2h (R/W) = Bulk 3h (R/W) = Interrupt |
3-0 | TEP | R/W | 0h | Target Endpoint Number. Software must configure this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB controller during Device enumeration. Reset type: SYSRSn |
USBRXINTERVAL2 is shown in Figure 32-73 and described in Table 32-76.
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USB Host Receive Polling Interval Endpoint 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXPOLLNAKLMT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | RXPOLLNAKLMT | R/W | 0h | RX Polling / NAK Limit The polling interval for interrupt/isochronous transfers the NAK limit for bulk transfers. Reset type: SYSRSn |
USBTXMAXP3 is shown in Figure 32-74 and described in Table 32-77.
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USB Maximum Transmit Data Endpoint 3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAXLOAD | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXLOAD | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10-0 | MAXLOAD | R/W | 0h | Maximum Payload specifies the maximum payload in bytes per transaction. Reset type: SYSRSn |
USBTXCSRL3 is shown in Figure 32-75 and described in Table 32-78.
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USB Transmit Control and Status Endpoint 3 Low
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAKTO | CLRDT | STALLED | STALL_SETUP | FLUSH | UNDRNERROR3 | FIFONE | TXRDY |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | NAKTO | R/W | 0h | NAK Timeout. Software must clear this bit to allow the endpoint to continue. Reset type: SYSRSn 0h (R/W) = No timeout 1h (R/W) = Bulk endpoints only: Indicates that the transmit endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBTXINTERVAL[n] register. |
6 | CLRDT | R/W | 0h | Clear DataToggle Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Writing a 1 to this bit clears the DT bit in the USBTXCSRH[n] register. |
5 | STALLED | R/W | 0h | Endpoint Stalled. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = A STALL handshake has not been received 1h (R/W) = Indicates that a STALL handshake has been received. When this bit is set, any DMA request that is in progress is stopped, the FIFO is completely flushed, and the TXRDY bit is cleared. |
4 | STALL_SETUP | R/W | 0h | Setup Packet. Reset type: SYSRSn 0h (R/W) = No SETUP token is sent. 1h (R/W) = Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set. Note: Setting this bit also clears the DT bit in the USBTXCSRH[n] register. |
3 | FLUSH | R/W | 0h | Flush FIFO. This bit can be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation. Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be corrupted. |
2 | UNDRNERROR3 | R/W | 0h | Error. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Three attempts have been made to send a packet and no handshake packet has been received. The TXRDY bit is cleared, the EPn bit in the USBTXIS register is set, and the FIFO is completely flushed inthis situation. Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode. |
1 | FIFONE | R/W | 0h | FIFO Not Empty Reset type: SYSRSn 0h (R/W) = The FIFO is empty 1h (R/W) = At least one packet is in the transmit FIFO. |
0 | TXRDY | R/W | 0h | Transmit Packet Ready. This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO. Reset type: SYSRSn 0h (R/W) = No transmit packet is ready. 1h (R/W) = Software sets this bit after loading a data packet into the TX FIFO. |
USBTXCSRH3 is shown in Figure 32-76 and described in Table 32-79.
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USB Transmit Control and Status Endpoint 3 High
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOSET | ISO | MODE | DMAEN | FDT | DMAMOD | DTWE | DT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AUTOSET | R/W | 0h | Auto Set Reset type: SYSRSn 0h (R/W) = The TXRDY bit must be set manually. 1h (R/W) = Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in USBTXMAXP[n]) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then the TXRDY bit must be set manually. |
6 | ISO | R/W | 0h | Isochronous Transfers Reset type: SYSRSn 0h (R/W) = Enables the transmit endpoint for bulk or interrupt transfers. 1h (R/W) = Enables the transmit endpoint for isochronous transfers. |
5 | MODE | R/W | 0h | Mode Note: This bit only has an effect when the same endpoint FIFO is used for both transmit and receive transactions. Reset type: SYSRSn 0h (R/W) = Enables the endpoint direction as RX. 1h (R/W) = Enables the endpoint direction as TX. |
4 | DMAEN | R/W | 0h | DMA Request Enable Note: Three TX and three /RX endpoints can be connected to the DMA module. If this bit is set for a particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly Reset type: SYSRSn 0h (R/W) = Disables the DMA request for the transmit endpoint. 1h (R/W) = Enables the DMA request for the transmit endpoint. |
3 | FDT | R/W | 0h | Force Data Toggle Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints. Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be corrupted. |
2 | DMAMOD | R/W | 0h | DMA Request Mode Reset type: SYSRSn 0h (R/W) = An interrupt is generated after every DMA packet transfer. 1h (R/W) = An interrupt is generated only after the entire DMA transfer is complete. Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode. |
1 | DTWE | R/W | 0h | Data Toggle Write Enable. This bit is automatically cleared once the new value is written. Reset type: SYSRSn 0h (R/W) = The DT bit cannot be written. 1h (R/W) = Enables the current state of the transmit endpoint data to be written (see DT bit). |
0 | DT | R/W | 0h | Data Toggle. When read, this bit indicates the current state of the transmit endpoint data toggle. If DTWE is High, this bit can be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the transmit endpoint. Reset type: SYSRSn |
USBRXMAXP3 is shown in Figure 32-77 and described in Table 32-80.
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USB Maximum Receive Data Endpoint 3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAXLOAD | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXLOAD | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10-0 | MAXLOAD | R/W | 0h | Maximum Payload specifies the maximum payload in bytes per transaction. Reset type: SYSRSn |
USBRXCSRL3 is shown in Figure 32-78 and described in Table 32-81.
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USB Receive Control and Status Endpoint 3 Low
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRDT | STALLED | STALLREQPKT | FLUSH | DATAERRNAKTO | OVERERROR3 | FULL | RXRDY |
W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLRDT | W1C | 0h | Clear Data Toggle. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Writing a 1 to this bit clears the DT bit in the USBRXCSRH[n] register. |
6 | STALLED | R/W | 0h | Endpoint Stalled. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No handshake has been received. 1h (R/W) = A STALL handshake has been received. The EPn bit in the USBRXIS register is also set. |
5 | STALLREQPKT | R/W | 0h | Request Packet. This bit is cleared when the RXRDY bit is set. Reset type: SYSRSn 0h (R/W) = No request 1h (R/W) = Requests an IN transaction. |
4 | FLUSH | R/W | 0h | Flush FIFO. If the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Note:This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be corrupted. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Flushes the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared |
3 | DATAERRNAKTO | R/W | 0h | Data Error / NAK Timeout Reset type: SYSRSn 0h (R/W) = Normal operation 1h (R/W) = Isochronous endpoints only: I ndicates that RXRDY is set and the data packet has a CRC or bit-stuff error. This bit is cleared when RXRDY is cleared. Bulk endpoints only: Indicates that the receive endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBRXINTERVAL[n] register. Software must clear this bit to allow the endpoint to continue. |
2 | OVERERROR3 | R/W | 0h | Error. Software must clear this bit. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Three attempts have been made to receive a packet and no data packet has been received. The Epn bit in the USBRXIS register is set in this situation. |
1 | FULL | R/W | 0h | FIFO Full Reset type: SYSRSn 0h (R/W) = The receive FIFO is not full. 1h (R/W) = No more packets can be loaded into the receive FIFO. |
0 | RXRDY | R/W | 0h | Receive Packet Ready. If the AUTOCLR bit in the USBRXCSRH[n] register is set, then the this bit is automatically cleared when a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO Reset type: SYSRSn 0h (R/W) = No data packet has been received. 1h (R/W) = Indicates that a data packet has been received. The EPn bit in the USBTXIS register is also set in this situation |
USBRXCSRH3 is shown in Figure 32-79 and described in Table 32-82.
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USB Receive Control and Status Endpoint 3 High
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOCL | ISOAUTORQ | DMAEN | DISNYETPIDERR | DMAMOD | DTWE | DT | RESERVED |
W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AUTOCL | W1C | 0h | Auto Clear Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using DMA to unload the receive FIFO as data is read from the receive FIFO in 4-byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXP[n] register, |
6 | ISOAUTORQ | R/W | 0h | Auto Request Note: This bit is automatically cleared when a short packet is received. Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared |
5 | DMAEN | R/W | 0h | DMA Request Enable Note: Three TX and three RX endpoints can be connected to the DMA module. If this bit is set for a particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly Reset type: SYSRSn 0h (R/W) = Disables the DMA request for the receive endpoint. 1h (R/W) = Enables the DMA request for the receive endpoint. |
4 | DISNYETPIDERR | R/W | 0h | PID Error. This bit is ignored in bulk or interrupt transactions. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Indicates a PID error in the received packet of an isochronous transaction. |
3 | DMAMOD | R/W | 0h | DMAMOD Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. Reset type: SYSRSn 0h (R/W) = An interrupt is generated after every DMA packet transfer. 1h (R/W) = An interrupt is generated only after the entire DMA transfer is complete. |
2 | DTWE | R/W | 0h | Data Toggle Write Enable. This bit is automatically cleared once the new value is written. Reset type: SYSRSn 0h (R/W) = The DT bit cannot be written. 1h (R/W) = Enables the current state of the receive endpoint data to be written (see DT bit). |
1 | DT | R/W | 0h | Data Toggle. When read, this bit indicates the current state of the receive data toggle. If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the receive endpoint. Reset type: SYSRSn |
0 | RESERVED | R/W | 0h | Reserved |
USBRXCOUNT3 is shown in Figure 32-80 and described in Table 32-83.
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USB Receive Byte Count Endpoint 3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COUNT | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12-0 | COUNT | R | 0h | Receive Packet Count indicates the number of bytes in the receive packet. Reset type: SYSRSn |
USBTXTYPE3 is shown in Figure 32-81 and described in Table 32-84.
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USB Host Transmit Configure Type Endpoint 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPEED | PROTO | TEP | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SPEED | R/W | 0h | Operating Speed. This bit field specifies the operating speed of the target Device: Reset type: SYSRSn 0h (R/W) = Default. The target is assumed to be using the same connection speed as the USB controller. 1h (R/W) = Reserved 2h (R/W) = Full 3h (R/W) = Low |
5-4 | PROTO | R/W | 0h | Protocol. Software must configure this bit field to select the required protocol for the transmit endpoint: Reset type: SYSRSn 0h (R/W) = Control 1h (R/W) = isochronous 2h (R/W) = Bulk 3h (R/W) = Interrupt |
3-0 | TEP | R/W | 0h | Target Endpoint Number. Software must configure this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB controller during Device enumeration. Reset type: SYSRSn |
USBTXINTERVAL3 is shown in Figure 32-82 and described in Table 32-85.
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USB Host Transmit Interval Endpoint 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXPOLLNAKLMT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TXPOLLNAKLMT | R/W | 0h | TX Polling / NAK Limit The polling interval for interrupt/isochronous transfers the NAK limit for bulk transfers. Reset type: SYSRSn |
USBRXTYPE3 is shown in Figure 32-83 and described in Table 32-86.
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USB Host Configure Receive Type Endpoint 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPEED | PROTO | TEP | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SPEED | R/W | 0h | Operating Speed. This bit field specifies the operating speed of the target Device: Reset type: SYSRSn 0h (R/W) = Default. The target is assumed to be using the same connection speed as the USB controller. 1h (R/W) = Reserved 2h (R/W) = Full 3h (R/W) = Low |
5-4 | PROTO | R/W | 0h | Protocol. Software must configure this bit field to select the required protocol for the transmit endpoint: Reset type: SYSRSn 0h (R/W) = Control 1h (R/W) = isochronous 2h (R/W) = Bulk 3h (R/W) = Interrupt |
3-0 | TEP | R/W | 0h | Target Endpoint Number. Software must configure this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB controller during Device enumeration. Reset type: SYSRSn |
USBRXINTERVAL3 is shown in Figure 32-84 and described in Table 32-87.
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USB Host Receive Polling Interval Endpoint 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXPOLLNAKLMT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | RXPOLLNAKLMT | R/W | 0h | RX Polling / NAK Limit The polling interval for interrupt/isochronous transfers the NAK limit for bulk transfers. Reset type: SYSRSn |
USBRQPKTCOUNT1 is shown in Figure 32-85 and described in Table 32-88.
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USB Request Packet Count in Block Transfer Endpoint 1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COUNT | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12-0 | COUNT | R/W | 0h | Block Transfer Packet Count sets the number of packets of the size defined by the MAXLOAD bit field that are to be transferred in a block transfer. Note: This is only used in Host mode when AUTORQ is set. The bit has no effect in Device mode or when AUTORQ is not set. Reset type: SYSRSn |
USBRQPKTCOUNT2 is shown in Figure 32-86 and described in Table 32-89.
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USB Request Packet Count in Block Transfer Endpoint 2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COUNT | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12-0 | COUNT | R/W | 0h | Block Transfer Packet Count sets the number of packets of the size defined by the MAXLOAD bit field that are to be transferred in a block transfer. Note: This is only used in Host mode when AUTORQ is set. The bit has no effect in Device mode or when AUTORQ is not set. Reset type: SYSRSn |
USBRQPKTCOUNT3 is shown in Figure 32-87 and described in Table 32-90.
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USB Request Packet Count in Block Transfer Endpoint 3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COUNT | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12-0 | COUNT | R/W | 0h | Block Transfer Packet Count sets the number of packets of the size defined by the MAXLOAD bit field that are to be transferred in a block transfer. Note: This is only used in Host mode when AUTORQ is set. The bit has no effect in Device mode or when AUTORQ is not set. Reset type: SYSRSn |
USBRXDPKTBUFDIS is shown in Figure 32-88 and described in Table 32-91.
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USB Receive Double Packet Buffer Disable
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EP3 | EP2 | EP1 | RESERVED | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | EP3 | R | 0h | EP3 RX Double Packet Buffer Disable Reset type: SYSRSn 0h (R/W) = Disables double-packet buffering. 1h (R/W) = Enables double-packet buffering. |
2 | EP2 | R | 0h | EP2 RX Double Packet Buffer Disable Reset type: SYSRSn 0h (R/W) = Disables double-packet buffering. 1h (R/W) = Enables double-packet buffering. |
1 | EP1 | R | 0h | EP1 RX Double Packet Buffer Disable Reset type: SYSRSn 0h (R/W) = Disables double-packet buffering. 1h (R/W) = Enables double-packet buffering. |
0 | RESERVED | R | 0h | Reserved |
USBTXDPKTBUFDIS is shown in Figure 32-89 and described in Table 32-92.
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USB Transmit Double Packet Buffer Disable
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EP3 | EP2 | EP1 | RESERVED | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | EP3 | R | 0h | EP3 TX Double Packet Buffer Disable Reset type: SYSRSn 0h (R/W) = Disables double-packet buffering. 1h (R/W) = Enables double-packet buffering. |
2 | EP2 | R | 0h | EP2 TX Double Packet Buffer Disable Reset type: SYSRSn 0h (R/W) = Disables double-packet buffering. 1h (R/W) = Enables double-packet buffering. |
1 | EP1 | R | 0h | EP1 TX Double Packet Buffer Disable Reset type: SYSRSn 0h (R/W) = Disables double-packet buffering. 1h (R/W) = Enables double-packet buffering. |
0 | RESERVED | R | 0h | Reserved |
USBEPC is shown in Figure 32-90 and described in Table 32-93.
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USB External Power Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PFLTACT | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PFLTAEN | PFLTSEN | PFLTEN | RESERVED | EPENDE | EPEN | |
R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9-8 | PFLTACT | R/W | 0h | Power Fault Action. This bit field specifies how the USB0EPEN signal is changed when detecting a USB power fault Reset type: SYSRSn 0h (R/W) = Unchanged. USB0EPEN is controlled by the combination of the EPEN and EPENDE bits. 1h (R/W) = Tristate. USB0EPEN is undriven (tristate). 2h (R/W) = Low. USB0EPEN is driven Low. 3h (R/W) = High. USB0EPEN is driven High. |
7 | RESERVED | R | 0h | Reserved |
6 | PFLTAEN | R/W | 0h | Power Fault Action Enable. This bit specifies whether a USB power fault triggers any automatic corrective action regarding the driven state of the USB0EPEN signal. Reset type: SYSRSn 0h (R/W) = Disabled. USB0EPEN is controlled by the combination of the EPEN and EPENDE bits. 1h (R/W) = Enabled. The USB0EPEN output is automatically changed to the state specified by the PFLTACT field. |
5 | PFLTSEN | R/W | 0h | Power Fault Sense. This bit specifies the logical sense of the USB0PFLT input signal that indicates an error condition. The complementary state is the inactive state. Reset type: SYSRSn 0h (R/W) = Low Fault. If USB0PFLT is driven Low, the power fault is signaled internally (if enabled by the PFLTEN bit). 1h (R/W) = High Fault. If USB0PFLT is driven High, the power fault is signaled internally (if enabled by the PFLTEN bit). |
4 | PFLTEN | R/W | 0h | Power Fault Input Enable. This bit specifies whether the USB0PFLT input signal is used in internal logic. Reset type: SYSRSn 0h (R/W) = Not Used. The USB0PFLT signal is ignored. 1h (R/W) = Used. The USB0PFLT signal is used internally |
3 | RESERVED | R | 0h | Reserved |
2 | EPENDE | R/W | 0h | EPEN Drive Enable. This bit specifies whether the USB0EPEN signal is driven or undriven (tristate). When driven, the signal value is specified by the EPEN field. When not driven, the EPEN field is ignored and the USB0EPEN signal is placed in a high-impedance state. The USB0EPEN signal is undriven at reset because the sense of the external power supply enable is unknown. By adding the high-impedance state, system designers can bias the power supply enable to the disabled state using a large resistor (100 kOhm) and later configure and drive the output signal to enable the power supply. Reset type: SYSRSn 0h (R/W) = Not Driven. The USB0EPEN signal is high impedance. 1h (R/W) = Driven. The USB0EPEN signal is driven to the logical value specified by the value of the EPEN field. |
1-0 | EPEN | R/W | 0h | External Power Supply Enable Configuration. This bit field specifies and controls the logical value driven on the USB0EPEN signal. Reset type: SYSRSn 0h (R/W) = Power Enable Active Low. The USB0EPEN signal is driven Low if the EPENDE bit is set. 1h (R/W) = Power Enable Active High. The USB0EPEN signal is driven High if the EPENDE bit is set. 2h (R/W) = Power Enable High if VBUS Low. The USB0EPEN signal is driven High when the A device is not recognized. 3h (R/W) = Power Enable High if VBUS High. The USB0EPEN signal is driven High when the A device is recognized. |
USBEPCRIS is shown in Figure 32-91 and described in Table 32-94.
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USB External Power Control Raw Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PF | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | PF | R | 0h | USB Power Fault Interrupt Status. This bit is cleared by writing a 1 to the PF bit in the USBEPCISC register Reset type: SYSRSn 0h (R/W) = A Power Fault status has been detected. 1h (R/W) = An interrupt has not occurred. |
USBEPCIM is shown in Figure 32-92 and described in Table 32-95.
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USB External Power Control Interrupt Mask
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PF | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | PF | R | 0h | USB Power Fault Interrupt Mask. Reset type: SYSRSn 0h (R/W) = The raw interrupt signal from a detected power fault is sent to the interrupt controller. 1h (R/W) = A detected power fault does not affect the interrupt status. |
USBEPCISC is shown in Figure 32-93 and described in Table 32-96.
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USB External Power Control Interrupt Status and Clear
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PF | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | PF | R | 0h | Power Fault Interrupt Status and Clear This bit is cleared by writing a 1. Clearing this bit also clears the PF bit in the USBEPCISC register. Reset type: SYSRSn 0h (R/W) = The PF bits in the USBEPCRIS and USBEPCIM registers are set, providing an interrupt to the interrupt controller 1h (R/W) = No interrupt has occurred or the interrupt is masked. |
USBDRRIS is shown in Figure 32-94 and described in Table 32-97.
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USB Device RESUME Raw Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESUME | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | RESUME | R | 0h | RESUME Interrupt Status This bit is cleared by writing a 1 to the RESUME bit in the USBDRISC register. Reset type: SYSRSn 0h (R/W) = A RESUME status has been detected. 1h (R/W) = An interrupt has not occurred. |
USBDRIM is shown in Figure 32-95 and described in Table 32-98.
Return to the Summary Table.
USB Device RESUME Interrupt Mask
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESUME | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | RESUME | R | 0h | Resume Interrupt Mask Reset type: SYSRSn 0h (R/W) = The raw interrupt signal from a detected RESUME is sent to the interrupt controller. This bit should only be set when a SUSPEND has been detected (the SUSPEND bit in the USBIS register is set). 1h (R/W) = A detected RESUME does not affect the interrupt status. |
USBDRISC is shown in Figure 32-96 and described in Table 32-99.
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USB Device RESUME Interrupt Status and Clear
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESUME | ||||||
R-0h | W1C-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | RESUME | W1C | 0h | RESUME Interrupt Status and Clear. This bit is cleared by writing a 1. Clearing this bit also clears the RESUME bit in the USBDRCRIS register Reset type: SYSRSn 0h (R/W) = The RESUME bits in the USBDRRIS and USBDRCIM registers are set, providing an interrupt to the interrupt controller. 1h (R/W) = No interrupt has occurred or the interrupt is masked. |
USBGPCS is shown in Figure 32-97 and described in Table 32-100.
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USB General-Purpose Control and Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DEVMODOTG | DEVMOD | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-2 | RESERVED | R | 0h | Reserved |
1 | DEVMODOTG | R/W | 0h | Enable Device Mode. This bit enables the DEVMOD bit to control the state of the internal ID signal in G OTG mode. Reset type: SYSRSn 0h (R/W) = The RESUME bits in the USBDRRIS and USBDRCIM registers are set, providing an interrupt to the interrupt controller. 1h (R/W) = No interrupt has occurred or the interrupt is masked. |
0 | DEVMOD | R/W | 0h | Device Mode This bit specifies the state of the internal ID signal in Host mode and in OTG mode when the DEVMODOTG bit is set. In Device mode this bit is ignored (assumed set). Reset type: SYSRSn 0h (R/W) = The RESUME bits in the USBDRRIS and USBDRCIM registers are set, providing an interrupt to the interrupt controller. 1h (R/W) = No interrupt has occurred or the interrupt is masked. |
USBVDC is shown in Figure 32-98 and described in Table 32-101.
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USB VBUS Droop Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VBDEN | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | VBDEN | R/W | 0h | Vbus Droop Enable Reset type: SYSRSn |
USBVDCRIS is shown in Figure 32-99 and described in Table 32-102.
Return to the Summary Table.
USB VBUS Droop Control Raw Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VD | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | VD | R | 0h | Vbus Droop Raw Interrupt Status Reset type: SYSRSn |
USBVDCIM is shown in Figure 32-100 and described in Table 32-103.
Return to the Summary Table.
USB VBUS Droop Control Interrupt Mask
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VD | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | VD | R | 0h | Vbus Droop Interrupt Mask Reset type: SYSRSn |
USBVDCISC is shown in Figure 32-101 and described in Table 32-104.
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USB VBUS Droop Control Interrupt Status and Clear
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VD | ||||||||||||||
R-0h | W1C-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | VD | W1C | 0h | Vbus Droop Interrupt Status and Clear Reset type: SYSRSn |
USBIDVRIS is shown in Figure 32-102 and described in Table 32-105.
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USB ID Valid Detect Raw Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ID | ||||||||||||||
R-0h | W1C-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | ID | W1C | 0h | ID Valid Detect Raw Interrupt Status Reset type: SYSRSn |
USBIDVIM is shown in Figure 32-103 and described in Table 32-106.
Return to the Summary Table.
USB ID Valid Detect Interrupt Mask
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ID | ||||||||||||||
R-0h | W1C-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | ID | W1C | 0h | ID Valid Detect Interrupt mask Reset type: SYSRSn |
USBIDVISC is shown in Figure 32-104 and described in Table 32-107.
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USB ID Valid Detect Interrupt Status and Clear
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ID | ||||||||||||||
R-0h | W1C-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | ID | W1C | 0h | ID Valid Detect Interrupt Status and Clear Reset type: SYSRSn |
USBDMASEL is shown in Figure 32-105 and described in Table 32-108.
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USB DMA Select
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DMACTX | DMACRX | |||||||||||||
R-0h | R/W-0h | R/W-0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMABTX | DMABRX | DMAATX | DMAARX | ||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-20 | DMACTX | R/W | 0h | DMA C TX Select specifies the TX mapping of the third USB endpoint on DMA channel 5 Reset type: SYSRSn 0h (R/W) = Reserved 1h (R/W) = Endpoint 1 TX 2h (R/W) = Endpoint 2 TX 3h (R/W) = Endpoint 3 TX |
19-16 | DMACRX | R/W | 0h | DMA C RX Select specifies the RX and TX mapping of the third USB endpoint on DMA channel 4 Reset type: SYSRSn 0h (R/W) = Reserved 1h (R/W) = Endpoint 1 RX 2h (R/W) = Endpoint 2 RX 3h (R/W) = Endpoint 3 RX |
15-12 | DMABTX | R/W | 0h | DMA B TX Select specifies the TX mapping of the second USB endpoint on DMA channel 3 Reset type: SYSRSn 0h (R/W) = Reserved 1h (R/W) = Endpoint 1 TX 2h (R/W) = Endpoint 2 TX 3h (R/W) = Endpoint 3 TX |
11-8 | DMABRX | R/W | 0h | DMA B RX Select Specifies the RX mapping of the second USB endpoint on DMA channel 2 Reset type: SYSRSn 0h (R/W) = Reserved 1h (R/W) = Endpoint 1 RX 2h (R/W) = Endpoint 2 RX 3h (R/W) = Endpoint 3 RX |
7-4 | DMAATX | R/W | 0h | DMA A TX Select specifies the TX mapping of the first USB endpoint on DMA channel 1 Reset type: SYSRSn 0h (R/W) = Reserved 1h (R/W) = Endpoint 1 TX 2h (R/W) = Endpoint 2 TX 3h (R/W) = Endpoint 3 TX |
3-0 | DMAARX | R/W | 0h | DMA A RX Select specifies the RX mapping of the first USB endpoint on DMA channel 0 Reset type: SYSRSn 0h (R/W) = Reserved 1h (R/W) = Endpoint 1 RX 2h (R/W) = Endpoint 2 RX 3h (R/W) = Endpoint 3 RX |
USB_GLB_INT_EN is shown in Figure 32-106 and described in Table 32-109.
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USB Global Interrupt Enable Register
Note: This Register is applicable only when USB is mapped to CPU1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTEN | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | INTEN | R/W | 0h | 1: Interrupt enabled, USB interrupt is passed on. 0: Interrupt disabled, USB interrupt is blocked. Reset type: SYSRSn |
USB_GLB_INT_FLG is shown in Figure 32-107 and described in Table 32-110.
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USB Global Interrupt Flag Register
Note: This Register is applicable only when USB is mapped to CPU1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTFLG | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | INTFLG | R/W | 0h | 1: Once USB interrupt has been fired, no other interrupt will be fired unless this flag is cleared by writing to USB_GLB_INT_FLG_CLR register. 0: No interrupt has been fired. Reset type: SYSRSn |
USB_GLB_INT_FLG_CLR is shown in Figure 32-108 and described in Table 32-111.
Return to the Summary Table.
USB Global Interrupt Flag Clear Register
Note: This Register is applicable only when USB is mapped to CPU1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTFLG | ||||||
R-0h | R-0/W1S-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | INTFLG | R-0/W1S | 0h | Write of 1 to this field clears the corresponding bit in USB_GLB_INT_FLG register. Write of 0 has no effect. Reset type: SYSRSn |
USBDMARIS is shown in Figure 32-109 and described in Table 32-112.
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USB uDMA Raw Interrupt Status register.
Note: This Register is applicable only when USB is mapped to CM
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USB_DMAC_TX_DONE | USB_DMAC_RX_DONE | USB_DMAB_TX_DONE | USB_DMAB_RX_DONE | USB_DMAA_TX_DONE | USB_DMAA_Rx_DONE | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | USB_DMAC_TX_DONE | R | 0h | 1: USB uDMA transfer complete indication of USB_DMAC_TX trigger 0: No USB uDMA transfer complete indication of USB_DMAC_TXtrigger Reset type: PER.RESET |
4 | USB_DMAC_RX_DONE | R | 0h | 1: USB uDMA transfer complete indication of USB_DMAC_RX trigger 0: No USB uDMA transfer complete indication of USB_DMAC_RXtrigger Reset type: PER.RESET |
3 | USB_DMAB_TX_DONE | R | 0h | 1: USB uDMA transfer complete indication of USB_DMAB_TX trigger 0: No USB uDMA transfer complete indication of USB_DMAB_TXtrigger Reset type: PER.RESET |
2 | USB_DMAB_RX_DONE | R | 0h | 1: USB uDMA transfer complete indication of USB_DMAB_RX trigger 0: No USB uDMA transfer complete indication of USB_DMAB_RXtrigger Reset type: PER.RESET |
1 | USB_DMAA_TX_DONE | R | 0h | 1: USB uDMA transfer complete indication of USB_DMAA_TX trigger 0: No USB uDMA transfer complete indication of USB_DMAA_TXtrigger Reset type: PER.RESET |
0 | USB_DMAA_Rx_DONE | R | 0h | 1: USB uDMA transfer complete indication of USB_DMAA_Rx trigger 0: No USB uDMA transfer complete indication of USB_DMAA_Rxtrigger Reset type: PER.RESET |
USBDMAIM is shown in Figure 32-110 and described in Table 32-113.
Return to the Summary Table.
USB uDMA Interrupt Mask Register
Note: This Register is applicable only when USB is mapped to CM
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USB_DMAC_TX_DONE | USB_DMAC_RX_DONE | USB_DMAB_TX_DONE | USB_DMAB_RX_DONE | USB_DMAA_TX_DONE | USB_DMAA_Rx_DONE | |
R-0h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | USB_DMAC_TX_DONE | R/W | 1h | 0: USB_DMAC_TX_DONE does not trigger a USB interrupt. 1: USB_DMAC_TX_DONE triggers a USB interrupt. Note: The reset value of this bit is 1 to keep compatibility with Concerto USB software model. Reset type: PER.RESET |
4 | USB_DMAC_RX_DONE | R/W | 1h | 0: USB_DMAC_RX_DONE does not trigger a USB interrupt. 1: USB_DMAC_RX_DONE triggers a USB interrupt. Note: The reset value of this bit is 1 to keep compatibility with Concerto USB software model. Reset type: PER.RESET |
3 | USB_DMAB_TX_DONE | R/W | 1h | 0: USB_DMAB_TX_DONE does not trigger a USB interrupt. 1: USB_DMAB_TX_DONE triggers a USB interrupt. Note: The reset value of this bit is 1 to keep compatibility with Concerto USB software model. Reset type: PER.RESET |
2 | USB_DMAB_RX_DONE | R/W | 1h | 0: USB_DMAB_RX_DONE does not trigger a USB interrupt. 1: USB_DMAB_RX_DONE triggers a USB interrupt. Note: The reset value of this bit is 1 to keep compatibility with Concerto USB software model. Reset type: PER.RESET |
1 | USB_DMAA_TX_DONE | R/W | 1h | 0: USB_DMAA_TX_DONE does not trigger a USB interrupt. 1: USB_DMAA_TX_DONE triggers a USB interrupt. Note: The reset value of this bit is 1 to keep compatibility with Concerto USB software model. Reset type: PER.RESET |
0 | USB_DMAA_Rx_DONE | R/W | 1h | 0: USB_DMAA_Rx_DONE does not trigger a USB interrupt. 1: USB_DMAA_Rx_DONE triggers a USB interrupt. Note: The reset value of this bit is 1 to keep compatibility with Concerto USB software model. Reset type: PER.RESET |
USBDMAISC is shown in Figure 32-111 and described in Table 32-114.
Return to the Summary Table.
USB uDMA Interrupt Status and Clear Register
Note: This Register is applicable only when USB is mapped to CM
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USB_DMAC_TX_DONE | USB_DMAC_RX_DONE | USB_DMAB_TX_DONE | USB_DMAB_RX_DONE | USB_DMAA_TX_DONE | USB_DMAA_Rx_DONE | |
R-0h | R/W1S-1h | R/W1S-1h | R/W1S-1h | R/W1S-1h | R/W1S-1h | R/W1S-1h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | USB_DMAC_TX_DONE | R/W1S | 1h | 0: USB_DMAC_TX_DONE has not triggered a USB interrupt. 1: USB_DMAC_TX_DONE triggered a USB interrupt. Note: This bit is cleared by writing a 1. Clearing this bit also clears the DMADONE bit in the USBDMARIS register. Reset type: PER.RESET |
4 | USB_DMAC_RX_DONE | R/W1S | 1h | 0: USB_DMAC_RX_DONE has not triggered a USB interrupt. 1: USB_DMAC_RX_DONE triggered a USB interrupt. Note: This bit is cleared by writing a 1. Clearing this bit also clears the DMADONE bit in the USBDMARIS register. Reset type: PER.RESET |
3 | USB_DMAB_TX_DONE | R/W1S | 1h | 0: USB_DMAB_TX_DONE has not triggered a USB interrupt. 1: USB_DMAB_TX_DONE triggered a USB interrupt. Note: This bit is cleared by writing a 1. Clearing this bit also clears the DMADONE bit in the USBDMARIS register. Reset type: PER.RESET |
2 | USB_DMAB_RX_DONE | R/W1S | 1h | 0: USB_DMAB_RX_DONE has not triggered a USB interrupt. 1: USB_DMAB_RX_DONE triggered a USB interrupt. Note: This bit is cleared by writing a 1. Clearing this bit also clears the DMADONE bit in the USBDMARIS register. Reset type: PER.RESET |
1 | USB_DMAA_TX_DONE | R/W1S | 1h | 0: USB_DMAA_TX_DONE has not triggered a USB interrupt. 1: USB_DMAA_TX_DONE triggered a USB interrupt. Note: This bit is cleared by writing a 1. Clearing this bit also clears the DMADONE bit in the USBDMARIS register. Reset type: PER.RESET |
0 | USB_DMAA_Rx_DONE | R/W1S | 1h | 0: USB_DMAA_Rx_DONE has not triggered a USB interrupt. 1: USB_DMAA_Rx_DONE triggered a USB interrupt. Note: This bit is cleared by writing a 1. Clearing this bit also clears the DMADONE bit in the USBDMARIS register. Reset type: PER.RESET |