SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
Table 3-608 lists the memory-mapped registers for the CPU1_LFU_REGS registers. All register offset addresses not listed in Table 3-608 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | LFUConfig_CPU1 | LFU configuration Register | EALLOW | Go |
2h | LFUStatus_CPU1 | LFU Configuration Status Register | Go | |
10h | SWConfig1_SYSRSn | Spare registers reset by SYSRSn | EALLOW | Go |
12h | SWConfig2_SYSRSn | Spare registers reset by SYSRSn | EALLOW | Go |
14h | SWConfig1_XRSn | Spare registers reset by XRSn | EALLOW | Go |
16h | SWConfig2_XRSn | Spare registers reset by XRSn | EALLOW | Go |
18h | SWConfig1_PORESETn | Spare registers reset by PORESETn | EALLOW | Go |
1Ah | SWConfig2_PORESETn | Spare registers reset by PORESETn | EALLOW | Go |
1Ch | LFU_LOCK | LFU Lock Configuration | Go | |
1Eh | LFU_COMMIT | LFU Commit Configuration | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-609 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
LFUConfig_CPU1 is shown in Figure 3-570 and described in Table 3-610.
Return to the Summary Table.
LFU configuration Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | LS01Swap | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PieVectorSwap | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LFU_CLA1 | RESERVED | LFU_CPU | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | RESERVED | R/W | 0h | Reserved |
20 | LS01Swap | R/W | 0h | 0: LS0 and LS1 mapped to the original location 1: Location of LS0 and LS1 is swapped. Reset type: SYSRSn |
19-13 | RESERVED | R/W | 0h | Reserved |
12 | PieVectorSwap | R/W | 0h | 0: PIE vector table is mapped to the original location 1: PIE Vector Table is swapped to alternate location Reset type: SYSRSn |
11-9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7-5 | RESERVED | R/W | 0h | Reserved |
4 | LFU_CLA1 | R/W | 0h | 0: No pending LFU Requests 1: LFU Request in progress This bit is used by compiler/application code for implementing CLA1 LFU Reset type: SYSRSn |
3-1 | RESERVED | R/W | 0h | Reserved |
0 | LFU_CPU | R/W | 0h | 0: No pending LFU Requests 1: LFU Request in progress This bit is used by compiler/application code for implementing CPU LFU Reset type: SYSRSn |
LFUStatus_CPU1 is shown in Figure 3-571 and described in Table 3-611.
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LFU Configuration Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | LS01Swap | RESERVED | |||||
R-0-0h | R-0h | R-0-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PieVectorSwap | RESERVED | |||||
R-0-0h | R-0h | R-0-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | RESERVED | R-0 | 0h | Reserved |
20 | LS01Swap | R | 0h | 0: LS0 and LS1 mapped to the original location 1: Location of LS0 and LS1 is swapped. Note: An initiated LSx swap will become uncessful if the LS0 and LS1 memories have different security configurations Reset type: SYSRSn |
19-13 | RESERVED | R-0 | 0h | Reserved |
12 | PieVectorSwap | R | 0h | 0: PIE vector table is mapped to the original location 1: PIE Vector Table is swapped to alternate location Reset type: SYSRSn |
11-0 | RESERVED | R-0 | 0h | Reserved |
SWConfig1_SYSRSn is shown in Figure 3-572 and described in Table 3-612.
Return to the Summary Table.
Spare registers reset by SYSRSn
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BITS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BITS | R/W | 0h | R/W bits reset by SYSRSn to be used by the application software Reset type: SYSRSn |
SWConfig2_SYSRSn is shown in Figure 3-573 and described in Table 3-613.
Return to the Summary Table.
Spare registers reset by SYSRSn
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BITS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BITS | R/W | 0h | R/W bits reset by SYSRSn to be used by the application software Reset type: SYSRSn |
SWConfig1_XRSn is shown in Figure 3-574 and described in Table 3-614.
Return to the Summary Table.
Spare registers reset by XRSn
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BITS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BITS | R/W | 0h | R/W bits reset by XRSn to be used by the application software Reset type: XRSn |
SWConfig2_XRSn is shown in Figure 3-575 and described in Table 3-615.
Return to the Summary Table.
Spare registers reset by XRSn
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BITS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BITS | R/W | 0h | R/W bits reset by XRSn to be used by the application software Reset type: XRSn |
SWConfig1_PORESETn is shown in Figure 3-576 and described in Table 3-616.
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Spare registers reset by PORESETn
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BITS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BITS | R/W | 0h | R/W bits reset by PORESETn to be used by the application software Reset type: PORESETn |
SWConfig2_PORESETn is shown in Figure 3-577 and described in Table 3-617.
Return to the Summary Table.
Spare registers reset by PORESETn
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BITS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BITS | R/W | 0h | R/W bits reset by PORESETn to be used by the application software Reset type: PORESETn |
LFU_LOCK is shown in Figure 3-578 and described in Table 3-618.
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LFU Lock Configuration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SWConfig2_PORESETn | SWConfig1_PORESETn | SWConfig2_XRSn | SWConfig1_XRSn | SWConfig2_SYSRSn | SWConfig1_SYSRSn | |
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LFUConfig | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R-0 | 0h | Reserved |
13 | SWConfig2_PORESETn | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: SYSRSn |
12 | SWConfig1_PORESETn | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: SYSRSn |
11 | SWConfig2_XRSn | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: SYSRSn |
10 | SWConfig1_XRSn | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: SYSRSn |
9 | SWConfig2_SYSRSn | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: SYSRSn |
8 | SWConfig1_SYSRSn | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: SYSRSn |
7-1 | RESERVED | R-0 | 0h | Reserved |
0 | LFUConfig | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: SYSRSn |
LFU_COMMIT is shown in Figure 3-579 and described in Table 3-619.
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LFU Commit Configuration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SWConfig2_PORESETn | SWConfig1_PORESETn | SWConfig2_XRSn | SWConfig1_XRSn | SWConfig2_SYSRSn | SWConfig1_SYSRSn | |
R-0-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LFUConfig | ||||||
R-0-0h | R/WSonce-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R-0 | 0h | Reserved |
13 | SWConfig2_PORESETn | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register lock configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: SYSRSn |
12 | SWConfig1_PORESETn | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register lock configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: SYSRSn |
11 | SWConfig2_XRSn | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register lock configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: SYSRSn |
10 | SWConfig1_XRSn | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register lock configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: SYSRSn |
9 | SWConfig2_SYSRSn | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register lock configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: SYSRSn |
8 | SWConfig1_SYSRSn | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register lock configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: SYSRSn |
7-1 | RESERVED | R-0 | 0h | Reserved |
0 | LFUConfig | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register lock configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: SYSRSn |