SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
Using the INTERNALTEST mux, gain balancing between multiple ADCs can be performed. By calculating the relative gain error between the ADCs, conversion results can be post-processed in software such that each ADC has the same output for each equivalent input.
To activate gain calibration mode, configure the TESTSEL field of the INTERNALTESTCTL analog subsystem register to select ENZ_CALIB_GAIN_3P3V. In this mode, the voltage sampled by all ADCs when triggered is (VREFHI * 0.9), overriding the channel selection in ADCSOCxCTL.CHSEL. To turn off gain calibration mode and return to normal operation, configure the TESTSEL field of INTERNALTESTCTL to 0.