This section describes the hardware support
options for IPC communication between the two CPUs. These options can be used independently
or in combination. All flag definitions and data formats are entirely user-defined.
- The flag system supports event-based
communication via interrupts and register polling.
- CPUx can raise an IPC event by
writing to any of the 32 bits of the IPCSET register. This sets the corresponding bits
in the CPUx IPCFLG register and CPUy IPCSTS register.
- CPUy can signal the response to the
event by setting the appropriate bit in the IPCACK register. This clears the
corresponding bits in the CPUx IPCFLG register and the CPUy IPCSTS register.
- If CPUx needs to cancel an event,
CPUx can set the appropriate bit in the IPCCLR register. This has the same effect as
CPUy writing to IPCACK.
- Flags
0–3 (set using IPCSET[3:0]) fire interrupts to the remote CPU. The remote CPU must
configure the ePIE module properly to receive an IPC interrupt. Flags 4–31 (set using
IPCSET[31:4]) do not produce interrupts. Multiple flags can be set, acknowledged, and
cleared simultaneously.
- The command registers support sending
several distinct pieces of information and are named COM, ADDR, DATA, and REPLY for
convenience only and can hold whatever data the application needs.
- CPUx can write data to the
IPCSENDCOM, IPCSENDADDR, and IPCSENDDATA registers. CPUy receives these in the
IPCRECVCOM, IPCRECVADDR, and IPCRECVDATA registers.
- CPUy can respond by writing to the
IPCREPLY
register. CPUx receives this data in the IPCREPLY
register.
- There is an additional pair of command-like registers offered for boot-time IPC or any
other convenient use — IPCBOOTMODE and IPCBOOTSTS. Both CPUs can read these registers.
CPUx can only write to IPCBOOTMODE, and CPUy can only write to IPCBOOTSTS.
- There are two shared memories for passing large amounts of data between the CPUs. Each
CPU has a writable memory for sending data and a read-only memory for receiving data.
- Here is an example of how to use these features together. CPUx needs some data from
CPUy's LS RAM. The data is at CPUy address 0x9400 and is 0x80 16-bit words long. The
protocol can be implemented like this:
- CPUx writes 0x1 to IPCSENDCOM,
defined in software to mean "copy data from address". CPUx writes the address (0x9400)
to IPCSENDADDR and the data length (0x80) to IPCSENDDATA.
- CPUx writes to IPCSET[3] and
IPCSET[16]. Here, IPC flag 3 is configured to send an interrupt and IPCSET[16] is
defined in software to indicate an incoming command. CPUx begins polling for IPCFLG[3]
to go low.
- CPUy receives the interrupt. In the
interrupt handler, CPUy checks IPCSTS, finds that flag 16 is set, and runs a command
processor.
- CPUy reads the command (0x1) from
IPCRECVCOM, the address (0x9400) from IPCRECVADDR, and the data length (0x80) from
IPCRECVDATA. CPUy then copies the LS RAM data to an empty space in the writable shared
memory starting at offset 0x210.
- CPUy writes the shared memory address
(0x210) to the IPCLOCALREPLY register. CPUy then writes to IPCACK[16] and IPCACK[3] to
clear the flags and indicate completion of the command. CPUy's work is done.
- CPUx sees IPCFLG[3] go low. CPUx
reads IPCREMOTEREPLY to get the shared memory offset of the copied data (0x210).