SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
The Block Read (Figure 29-9) protocol is similar to a Read Word in structure, with the exception that there are more than 2 data bytes received from the target. The first data byte transmitted by the target represents the block length of the data being written by the target. If PEC processing is enabled, the target appends a PEC byte to the end of the message.
To initiate a Block Read message on the PMBus, the PMBCCR register is programmed with the block length in the Byte Count bits. This count excludes the command byte, any target address and the block length bytes in the message. The command byte to be transmitted to the target is written into bits 7-0 of the PMBTXBUF register prior to the programming of the PMBCCR register.
After configuring the PMBCCR register, the Block Read message is transmitted. The module interrupts the firmware upon receipt of 4 data bytes from the target. If the block length is 3, the EOM interrupt is received concurrently with the data ready interrupt. Otherwise, only a data ready interrupt is asserted, indicating 4 bytes are ready for reading by the firmware. At the end of the message, less than 4 bytes can be stored in the PMBRXBUF register. The RX Byte Count bits in the PMBSTS register indicate the number of bytes available in the final data transfer. The firmware can verify the received PEC upon detection of the End of Message interrupt.