SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
The receiver module interfaces to the FSI clock (RXCLK), and data lines (RXD0 and RXD1) after the data lines pass through an optional programmable delay line. The receiver core handles the data framing, CRC computation, and frame-related error checking. The receiver bit clock and state machine are run by the RXCLK input, which is asynchronous to the device system clock.
The receiver control registers allow the CPU (or the CLA) to program, control, and monitor the operation of the FSI receiver. The receive data buffer is accessible by the CPU, CLA, and the DMA.
The receiver core has the following features:
Figure 27-5 provides a high-level overview of the internal modules present in the FSI receiver. Figure 27-6 shows a view of the FSI receiver core submodule. Not all data paths and internal connections are shown.
The following sections describe the various aspects of the FSI receiver module.