SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
Counter0 and Counter1 are configured based on the ratio between the frequencies of Clock0 and Clock1 (Fclk1 × Counter0 = Fclk0×Counter1). The Valid0 counter provides tolerance and is configured based on the error in DCC. Since Clock0 and Clock1 are asynchronous, the start and stop of the counters do not occur synchronously. Hence, while configuring the counters, two different sources of errors must be accounted for:
DCC Error (in Clock0 Cycles) = Async. Error + Digitization Error
DCC error shows up as a frequency error for clock under measurement. This error is DCC induced and does not represent error in frequency of clock under measurement. The application needs to take this into consideration while configuring the counters, and determine a desirable tolerance for DCC error that defines the window of measurement. To illustrate:
Window (in Clock0 Cycles) = (DCC Error)/(0.01 × Tolerance)
For example, if DCC Error is 10 and the tolerance desired is ±0.1%, then:
Window (in Clock0 Cycles) = 10/(0.01 × 0.1) = 10000
Based on above formula for Window, if the desired tolerance is low, then the counter values are large and increase the window of measurement. This means that counter values for a tolerance of 0.1% are larger than that of 0.2%. So, based on the application defined tolerance, define the window of measurement in terms of Clock0 cycles.
The clock under measurement can have an allowed frequency error. If this error is expected, then the error can also be accounted while configuring counters. For example, if measuring INTOSC1/2 frequency using an external crystal as a reference clock, the allowable tolerance of INTOSC1/2 (for example, ±1%) can be accounted for and factored into the counter configuration. The formula is:
Frequency Error Allowed (in Clock0 Cycles) = Window × (Allowable Frequency Tolerance (in %) / 100)
Total Error (in Clock0 Cycles) = DCC Error + Frequency Error Allowed
The following equations are used to configure counter values:
Counter0 (DCCCNTSEED0) = Window - Total Error
Valid0 (DCCVALIDSEED0) = 2 × Total Error
Counter1 (DCCCNTSEED1) = Window × (Fclk1/Fclk0)
Tolerance (%) = (100 × DCC Error × (Fclk1/Fclk0)) / 1048575