SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
Logical Shift Right
MRa | CLA floating-point source/destination register (MR0 to MR3) |
#SHIFT | Number of bits to shift (1 to 32) |
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1000 0000
Logical shift-right of MRa by the number of bits indicated. The number of bits can be 1 to 32. Unlike the arithmetic shift (MASR32), the logical shift does not preserve the number's sign bit. Every bit in the operand is moved the specified number of bit positions, and the vacant bit positions are filled in with zeros.
MARa(31:0) = Logical Shift Right(MARa(31:0) by #SHIFT bits);
This instruction modifies the following flags in the MSTF register:
Flag | TF | ZF | NF | LUF | LVF |
---|---|---|---|---|---|
Modified | No | Yes | Yes | No | No |
The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1;}
This is a single-cycle instruction.
; Illustrate the difference between MASR32 and MLSR32
MMOVIZ MR0, #0xAAAA ; MR0 = 0xAAAA5555
MMOVXI MR0, #0x5555
MMOV32 MR1, MR0 ; MR1 = 0xAAAA5555
MMOV32 MR2, MR0 ; MR2 = 0xAAAA5555
MASR32 MR1, #1 ; MR1 = 0xD5552AAA
MLSR32 MR2, #1 ; MR2 = 0x55552AAA
MASR32 MR1, #1 ; MR1 = 0xEAAA9555
MLSR32 MR2, #1 ; MR2 = 0x2AAA9555
MASR32 MR1, #6 ; MR1 = 0xFFAAAA55
MLSR32 MR2, #6 ; MR2 = 0x00AAAA55