SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
The I2C module generates the interrupt requests described in Table 28-6. As shown in Figure 28-17, all requests are multiplexed through an arbiter to a single I2C interrupt request to the CPU. Each interrupt request has a flag bit in the status register (I2CSTR) and an enable bit in the interrupt enable register (I2CIER). When one of the specified events occurs, the flag bit is set. If the corresponding enable bit is 0, the interrupt request is blocked. If the enable bit is 1, the request is forwarded to the CPU as an I2C interrupt.
The I2C interrupt is one of the maskable interrupts of the CPU. As with any maskable interrupt request, if the request is properly enabled in the CPU, the CPU executes the corresponding interrupt service routine (I2CINT1A_ISR). The I2CINT1A_ISR for the I2C interrupt can determine the interrupt source by reading the interrupt source register, I2CISRC. Then the I2CINT1A_ISR can branch to the appropriate subroutine.
After the CPU reads I2CISRC, the following events occur:
I2C Interrupt Request | Interrupt Source |
---|---|
XRDYINT | Transmit ready condition: The data transmit register (I2CDXR) is ready to accept new data because the previous data has been copied from I2CDXR to the transmit shift register (I2CXSR). |
As an alternative to using XRDYINT, the CPU can poll the XRDY bit of the status register, I2CSTR. XRDYINT must not be used when in FIFO mode. Use the FIFO interrupts instead. | |
RRDYINT | Receive ready condition: The data receive register (I2CDRR) is ready to be read because data has been copied from the receive shift register (I2CRSR) to I2CDRR. |
As an alternative to using RRDYINT, the CPU can poll the RRDY bit of I2CSTR. RRDYINT must not be used when in FIFO mode. Use the FIFO interrupts instead. | |
ARDYINT | Register-access ready condition: The I2C module registers are ready to be accessed because the previously programmed address, data, and command values have been used. |
The specific events that generate ARDYINT are the same events that set the ARDY bit of I2CSTR. | |
As an alternative to using ARDYINT, the CPU can poll the ARDY bit. | |
NACKINT | No-acknowledgment condition: The I2C module is configured as a controller-transmitter and did not received acknowledgment from the target-receiver. |
As an alternative to using NACKINT, the CPU can poll the NACK bit of I2CSTR. | |
ARBLINT | Arbitration-lost condition: The I2C module has lost an arbitration contest with another controller-transmitter. |
As an alternative to using ARBLINT, the CPU can poll the ARBL bit of I2CSTR. | |
SCDINT | Stop condition detected: A STOP condition was detected on the I2C bus. |
As an alternative to using SCDINT, the CPU can poll the SCD bit of the status register, I2CSTR. | |
AASINT | Addressed as target condition: The I2C has been addressed as a target device by another controller on the I2C bus. |
As an alternative to using AASINT, the CPU can poll the AAS bit of the status register, I2CSTR. |
The priorities of the basic I2C interrupt requests are listed in order of highest priority to lowest priority:
The normal transmit interrupt timing makes it possible for stale data to remain in the transmit buffer if a transaction is aborted in the middle of a byte. To avoid this, set the FCM bit in the I2CEMDR register. When this bit is set, the transmit data ready interrupt is generated only when data is required for a bus transaction. In controller mode, the interrupt is first generated when the ACK of the address byte is received. In target mode, the interrupt is first generated when the address is matched. Further interrupts are generated when the data is ACKed. In this mode, XRDY is asserted at the same time as the transmit ready interrupt.
The I2C module has a backwards compatibility bit (BC) in the I2CEMDR register. The timing diagram in demonstrates the effect the backwards compatibility bit has on I2C module registers and interrupts when configured as a target-transmitter.