SPRUJ06 October   2021

 

  1.   Trademarks
  2. 1Introduction
  3. 2Revisions and Assembly Variants
  4. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Interfaces and Major Component Description
      1. 3.3.1 Breakout Board Section
      2. 3.3.2 IO-Link Section Overview and Major Component Description
        1. 3.3.2.1 IO Link Transceiver TIOL111DMWR
        2. 3.3.2.2 Smart Switch TPS4H160BQPWPRQ1
        3. 3.3.2.3 Serializer SN65HVS882
        4. 3.3.2.4 INA253
        5. 3.3.2.5 LED Driver TLC59282
        6. 3.3.2.6 Signal Routing
      3. 3.3.3 Power Section
        1. 3.3.3.1 Power Input
      4. 3.3.4 Board Mating Connections
  5. 4Known Issues
    1. 4.1 Issue 1: Voltage Spike Across the TX Line of the Transceiver

Serializer SN65HVS882

The SN65HVS882 is an eight channel, digital-input serializer for high-channel density digital input modules in industrial automation. In combination with galvanic isolators the device completes the interface between the high voltage signals on the field-side and the low-voltage signals on the controller side. Input signals are current-limited and then validated by internal debounce filters. Each digital input operates as a controlled current sink limiting the input current to a maximum value of I LIM. The current limit is derived from the reference current via I LIM = n × IREF, and IREF is determined by IREF = VREF/RLIM. Thus, changing the current limit requires the change of RLIM to a different value via: RLIM = n × VREF/I LIM. While the device is specified for a current limit of 3.6 mA, (via RLIM = 25 kΩ) The DI signals from the M12 connectors are connected to the input channels of the serializer. The serializer is SPI compatible Upon a low-level at the load input, LD, the information of the field inputs, IP0 to IP7 is latched into the shift register. Taking LD high again blocks the parallel inputs of the shift register from the field inputs. A low-level at the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial output, SOP. Data is clocked at the rising edge of CLK. Thus, after eight consecutive clock cycles all field input data have been clocked out of the shift register and the information of the serial input, SIP, appears at the serial output, SOP.