SPRUJ09D March   2022  – September 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 2.1 Sitara MCU+ Academy
    2. 2.2 If You Need Assistance
    3. 2.3 Important Usage Notes
  5. 2Control Card Overview
    1. 3.1 Kit Contents
    2. 3.2 Key Features
    3. 3.3 Component Identification
    4. 3.4 HSEC 180-pin Control Card Docking Station
    5. 3.5 Compliance
  6. 3Board Setup
    1. 4.1 Power Requirements
      1. 4.1.1 Power Input Using USB Type-C Connector
      2. 4.1.2 Power Status LEDs
      3. 4.1.3 Power Tree
      4. 4.1.4 Power Sequence
    2. 4.2 Push Buttons
    3. 4.3 Boot Mode Selection
    4. 4.4 JTAG Path Selection
  7. 4Hardware Description
    1. 5.1  Functional Block Diagram
    2. 5.2  GPIO Mapping
    3. 5.3  Reset
    4. 5.4  Clock
    5. 5.5  Memory Interface
      1. 5.5.1 QSPI
      2. 5.5.2 Board ID EEPROM
    6. 5.6  Ethernet Interface
      1. 5.6.1 RGMII
      2. 5.6.2 PRU-ICSS
      3. 5.6.3 LED Indication in RJ45 Connector
    7. 5.7  I2C
    8. 5.8  Industrial Application LEDs
    9. 5.9  SPI
    10. 5.10 UART
    11. 5.11 MCAN
    12. 5.12 FSI
    13. 5.13 JTAG
    14. 5.14 Test Automation Header
    15. 5.15 LIN
    16. 5.16 MMC
    17. 5.17 ADC and DAC
    18. 5.18 HSEC Pinout and Pinmux Mapping
  8. 5References
    1. 6.1 References
    2. 6.2 Other TI Components Used in This Design
  9.   Revision History
  10.   A E2 Design Changes
  11.   B E1 HSEC Pinout Table

4.6.2 PRU-ICSS

Note: The PRU internal pinmux mapping provided in the TRM is part of the original hardware definition of the PRU. However, due to the flexibility provided by the IP and associated firmware configurations, this is not necessarily a hard requirement. The first PRU implementation for AM65x had the MII TX pins swapped during initial SoC integration and this convention was maintained for subsequent PRU revisions to enable firmware reuse. To make use of the SDK firmware, use the SYSCONFIG generated PRU pin mapping.

The AM263x Control Card makes use of two on-die programmable real-time unit and industrial communication subsystem's (PRU-ICSS) of the AM263x SoC to interface with two Ethernet PHY transceivers. There is a Gigabit Ethernet PHY transceiver (DP83869HMRGZT) connected to PRU0 of the SoC and an industrial Ethernet PHY transceiver (DP83826ERHBT) connected to PRU1. The ethernet data signals of each PHY are terminated to an RJ45 connector. The RJ45 connectors are used on the board for Ethernet 10/100/1000 (DP83869HMRGZT) and 10/100 (DP83826ERHBT) Mbps connectivity with integrated magnetic and LEDs for link and activity indication.

GUID-20220422-SS0I-60DJ-ZBGN-Q63RTDKHBJSW-low.png Figure 4-11 ICSSM Overview

For the Gigabit Ethernet PHY:

  • The Ethernet PHY requires three separate power sources. VDDIO is the 3.3 V, system generated analog supply. There are dedicated LDO's for the 1.1 V and 2.5 V supplies for the Ethernet PHY.
  • The Ethernet PHY uses many functional pins as strap options to place the device into a specific mode of operation. Each functional pin has a default mode that is driven by an internal pull resistor.
  • There is a 2:1 mux (TMUX154EDGSR) that controls the mapping of MDIO and MDC signals for the ethernet PHY's.
Table 4-5 Gigabit Ethernet PHY MDIO/MDC MUX
SEL Condition Function
HIGH AM263x SoC MDIO0 MDIO/MDC signals selected A1/B1→A/B port
LOW PRU MDIO/MDC signals selected A0/B0→ A/B port

  • The Ethernet PHY uses many functional pins as strap options to place the device into a specific mode of operation. Each functional pin has a default mode that is driven by an internal pull resistor.
GUID-20220422-SS0I-NXKC-VMPS-LWZJQKMPBVHG-low.png Figure 4-12 PRU0 ICSS Gigabit Ethernet PHY Strapping Resistors
Table 4-6 PRU0 ICSS Gigabit Ethernet PHY Strapping Resistors
Functional Pin Default Mode Mode in CC Function
RX_D0 0 3 PHY address: 0011
RX_D1 0 0
JTAG_TDO/GGPIO_1 0 0 RGMII to Copper
RX_D3 0 0
RX_D2 0 0
RX_LINK 0 0 Auto-negotiation, 1000/100/10 advertised, auto MDI-X
RX_ER 0 0
LED_2 0 0
RX_DV 0 0 Port Mirroring Disabled

For the Industrial Ethernet PHY transceiver:

  • The Ethernet PHY requires two separate power sources. VDDIO is the 3.3 V, system generated analog supply. VSYS_IO_3V3 is the 3.3 V I/O supply.
  • The Ethernet PHY is set to ENHANCED mode by pulling the MODESELECT pin up to VDDIO.
    • ENHANCED mode allows the DP83826E to support real-time Ethernet applications in addition to standard Ethernet applications.
  • The Ethernet PHY uses many functional pins as strap options to place the device into a specific mode of operation. Each functional pin has a default mode that is driven by an internal pull resistor.

GUID-20220422-SS0I-BRKT-B9RH-NKBFQSZVPZFD-low.png Figure 4-13 PRU1 ICSS Industrial Ethernet PHY Strapping Resistors
Table 4-7 PRU1 ICSS Industrial Ethernet PHY Strapping Resistors
Functional Pin Default Mode Mode in CC Function
RX_D0 1 1 Auto-negotiation enable
LED1 1 1 Odd nibble detection enable
RX_LINK 0 1 PHY address: 001
CRS 0 0
COL 0 0
TX_CLK 0 0 RMII Controller Mode
RX_ER 0 1 LED1 on pin 31
RX_D3 0 0 Fast link-drop disable
RX_D2 0 0 MII MAC mode
RX_D1 0 0 Auto MDIX enable
RX_DV 0 0 MDIX (applicable only when auto-MIDX is disabled)

For both Ethernet PHY's:

  • There are series termination resistors on the transmit and receive clock signals located near the AM263x SoC.
  • The MDIO and Interrupt signals from the SoC to the PHY require 2.2KΩ pull up resistors to the I/O supply voltage for proper operation. The interrupt signal is driven by a GPIO signal that is mapped from the AM263x SoC.
  • The reset signal for the Ethernet PHY is driven by a 2-input AND gate. The AND gate's inputs are a GPIO signal that is generated by the IO Expander and PORz.
  • A 25 MHz clock is sourced from a four output clock buffer that has a 25 MHz oscillator as an input.
  • There are three 1:2 muxes (TS3DDR3812RUAR) that control the mapping of ethernet signals from the SoC to either the Ethernet PHY's or the HSEC connector. The select logic for the three muxes is driven by two GPIO signals that are generated by the IO expander.
Table 4-8 ICSS HSEC MUX
Select Signal Logic Level Condition Function
ICSSM1_MUX_SEL LOW PRU0 signals mapped to Ethernet PHY A[n] → B[n]
HIGH PRU0 signals mapped to HSEC A[n] → C[n]
ICSSM2_MUX_SEL LOW PRU1 signals mapped to Ethernet PHY A[n] → B[n]
HIGH PRU1 signals mapped to HSEC A[n] → C[n]