SPRUJ10D May   2022  – September 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 2.1 Sitara MCU+ Academy
    2. 2.2 If You Need Assistance
    3. 2.3 Important Usage Notes
  5. 2Kit Overview
    1. 3.1 Kit Contents
    2. 3.2 Key Features
    3. 3.3 Component Identification
    4. 3.4 BoosterPacks
    5. 3.5 Compliance
    6. 3.6 Security
  6. 3Board Setup
    1. 4.1 Power Requirements
      1. 4.1.1 Power Input Using USB Type-C Connector
      2. 4.1.2 Power Status LEDs
      3. 4.1.3 Power Tree
    2. 4.2 Push Buttons
    3. 4.3 Boot Mode Selection
  7. 4Hardware Description
    1. 5.1  Functional Block Diagram
    2. 5.2  GPIO Mapping
    3. 5.3  Reset
    4. 5.4  Clock
    5. 5.5  Memory Interface
      1. 5.5.1 QSPI
      2. 5.5.2 Board ID EEPROM
    6. 5.6  Ethernet Interface
      1. 5.6.1 Ethernet PHY #1 - CPSW RGMII/ICSSM
      2. 5.6.2 Ethernet PHY #2 - CPSW RGMII/ICSSM
      3. 5.6.3 LED Indication in RJ45 Connector
    7. 5.7  I2C
    8. 5.8  Industrial Application LEDs
    9. 5.9  SPI
    10. 5.10 UART
    11. 5.11 MCAN
    12. 5.12 FSI
    13. 5.13 JTAG
    14. 5.14 Test Automation Header
    15. 5.15 LIN
    16. 5.16 MMC
    17. 5.17 ADC and DAC
    18. 5.18 EQEP and SDFM
    19. 5.19 EPWM
    20. 5.20 BoosterPack Headers
    21. 5.21 Pinmux Mapping
  8. 5References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  9. 6Revision History

4.6.1 Ethernet PHY #1 - CPSW RGMII/ICSSM

Note: The PRU internal pinmux mapping provided in the TRM is part of the original hardware definition of the PRU. However, due to the flexibility provided by the IP and associated firmware configuraitons, this is not necessarily a hard requirement. The first PRU implementation for AM65x had the MII TX pins swapped during initial SoC integration and this convention was maintained for subsequent PRU revisions to enable firmware reuse. To make use of the SDK firmware, use the SYSCONFIG generated PRU pin mapping.

The AM263x LaunchPad utilizes a 48-pin ethernet PHY (DP83869HMRGZT) connected to either CPSW RGMII or one on-die programmable real-time unit and industrial communication subsystem (PRU-ICSS). There is a 2:1 mux that selects between the RGMII or PRU-ICSS signals. The PHY is configured to advertise 1-Gb operation. The ethernet data signals of the PHY are terminated to an RJ45 connector. The RJ45 connector is used on the board for Ethernet 10/100/1000 Mbps connectivity with integrated magnetics and LEDs for link and activity indication.

GUID-20220502-SS0I-WTKB-JRBF-Q9D1DZ33RHCP-low.png
A. The series termination resistors that are oulined with a red dotted box were updated from 0Ω to 33Ω to improve signal integrity between the AM263x MCU MDIO pins and the attached PHY pins. The modification is signified by an "M1" sticker on the top side of the LaunchPad near the PORz push button.
Figure 4-8 Ethernet PHY #1

The Ethernet PHY requires three separate power sources. VDDIO is the 3.3V, system generated supply. There are dedicated LDO's for the 1.1V and 2.5V supplies for the Ethernet PHY.

There are series termination resistors on the transmit clock and data signals located near the SoC. There are series termination resistors on the receive clock and data signals near the Ethernet PHY.

The MDC and MDIO signals from the SoC to the PHY require 4.7KΩ pull up resistors to the 3.3 V system supply voltage for proper operation. There is an analog switch (TS5A23159DGSR) that selects between the CPSW MDIO/MDC and the ICSSM MDIO/MDC signals to be routed to the ethernet PHY.

Both the 2:1 Mux and analog switch are controlled by a GPIO signal that selects between CPSW RGMII and ICSSM signals.

Table 4-2 Ethernet PHY #1 CPSW/ICSSM Select
GPIO105 Condition Function of Mux
LOW RGMII CPSW Selected Port A ↔ Port B
HIGH ICSSM Selected Port A ↔ Port C

The reset input for the Ethernet PHY is controlled by the WARMRESET AM263x SoC output signal.

The Ethernet PHY uses many functional pins as strap option to place the device into specific modes of operation.

Table 4-3 Ethernet PHY #1 Strapping Resistors
Functional Pin Default Mode Mode in LP Function
RX_D0 0 3 PHY address: 0011
RX_D1 0 0
JTAG_TDO/GPIO_1 0 0 RGMII to Copper
RX_D3 0 0
RX_D2 0 0
LED_0 0 0 Auto-negotiation, 1000/100/10 advertised, auto MDI-X
RX_ER 0 0
LED_2 0 0
RX_DV 0 0 Port Mirroring Disabled
Note: Each strap pin has an internal pull down resistance of 9KΩ
Note: RX_D0 and RX_D1 are on a 4-level strap resistor mode scheme. All other signals are 2-level strap resistor modes.