SPRUJ10D May   2022  – September 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 2.1 Sitara MCU+ Academy
    2. 2.2 If You Need Assistance
    3. 2.3 Important Usage Notes
  5. 2Kit Overview
    1. 3.1 Kit Contents
    2. 3.2 Key Features
    3. 3.3 Component Identification
    4. 3.4 BoosterPacks
    5. 3.5 Compliance
    6. 3.6 Security
  6. 3Board Setup
    1. 4.1 Power Requirements
      1. 4.1.1 Power Input Using USB Type-C Connector
      2. 4.1.2 Power Status LEDs
      3. 4.1.3 Power Tree
    2. 4.2 Push Buttons
    3. 4.3 Boot Mode Selection
  7. 4Hardware Description
    1. 5.1  Functional Block Diagram
    2. 5.2  GPIO Mapping
    3. 5.3  Reset
    4. 5.4  Clock
    5. 5.5  Memory Interface
      1. 5.5.1 QSPI
      2. 5.5.2 Board ID EEPROM
    6. 5.6  Ethernet Interface
      1. 5.6.1 Ethernet PHY #1 - CPSW RGMII/ICSSM
      2. 5.6.2 Ethernet PHY #2 - CPSW RGMII/ICSSM
      3. 5.6.3 LED Indication in RJ45 Connector
    7. 5.7  I2C
    8. 5.8  Industrial Application LEDs
    9. 5.9  SPI
    10. 5.10 UART
    11. 5.11 MCAN
    12. 5.12 FSI
    13. 5.13 JTAG
    14. 5.14 Test Automation Header
    15. 5.15 LIN
    16. 5.16 MMC
    17. 5.17 ADC and DAC
    18. 5.18 EQEP and SDFM
    19. 5.19 EPWM
    20. 5.20 BoosterPack Headers
    21. 5.21 Pinmux Mapping
  8. 5References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  9. 6Revision History

4.20 BoosterPack Headers

GUID-20220510-SS0I-R80R-SQPX-RKWLVDFQXPTS-low.png Figure 4-24 AM263x LaunchPad BoosterPack Pinout
Note: This pinout represents the default signals mapped to the BoosterPack Header. Additional signal options for each header are available through Pinmuxing. Two signals for one pin represents an externally muxed option
Note: A gray background for a signal on the pinout shows that the signal does not follow the BoosterPack Standard pinout.

The AM263x LaunchPad supports two fully independent BoosterPack XL connectors. BoosterPack site #1 (J1/J3, J2/J4) is located in between the SoC and the micro-B USB Connector. BoosterPack site #2 (J5/J7, J6/J8) is located in between the SoC and the RJ45 connectors. Each GPIO has multiple functions available through the GPIO mux. The signals connected from the SoC to the BoosterPack headers include:

  • Various ADC inputs
  • DAC Out
  • UART1
  • Various GPIO signals
  • SPI0 and SPI1
  • I2C1 and I2C3
  • Various EPWM Channels
  • LIN1 and LIN2
  • MCAN1
  • SDFM0