SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
The registers TPCC_A_ERRAGG_MASK, TPCC_A_ERRAGG_STATUS, and TPCC_A_ERRAGG_STATUS_RAW are associated with the aggregated interrupt from EDMA TPCC_A_ERRAGGR. The TPCC_A_ERRAGG_MASK register can be configured to mask unwanted interrupt sources from EDMA from triggering the TPCC_A_ERRAGGR interrupt. The TPCC_A_ERRAGG_STATUS register indicates the status of interrupt sources which caused the TPCC_A_ERRAGGR interrupt to occur. The TPCC_A_ERRAGG_STATUS_RAW register indicates the raw status of interrupt sources of the TPCC_A_ERRAGGR interrupt.