The processor has the ability to perform multiple
MCSPI word access to the receive or transmit registers within a single 32-bit
interface access by setting the MCSPI_MODULCTRL[7] MOA to 1 under specific
conditions:
- The channel selected has the
FIFO enable.
- Only FIFO sense enabled
support the kind of access.
- MCSPI_MODULCTRL[7] MOA is set
to 1.
- Only 32-bit interface access
and data width can be performed to receive or transmit registers, for other
kind of access the processor must de-assert MCSPI_MODULCTRL[7] MOA bit.
- The level
MCSPI_XFERLEVEL[7-0] AEL and MCSPI_XFERLEVEL[15-8] AFL must be 32-bit
aligned, it means that AEL[0] = AEL[1] = 1 or AFL[0] = AFL[1] = 1.
- If MCSPI_XFERLEVEL[31-16]
WCNT is used it must be configured according to MCSPI word length.
- The word length of MCSPI
words allows to perform multiple MCSPI access, that means that
MCSPI_CHCONF_0/1/2/3[11-7] WL is <16.
The number of MCSPI word access depends on MCSPI word length:
- 3 ≤ WL ≤ 7, MCSPI word length smaller or equal to
byte length, 4 MCSPI words accessed per 32-bit interface read/write. If word
count is used (MCSPI_XFERLEVEL[31-16] WCNT), set the bit field to WCNT[0] =
WCNT[1] = 0.
- 8 ≤ WL ≤ 15, MCSPI word length greater than byte
or equal to 16-bit length, 2 MCSPI words accessed per 32-bit interface
read/write. If word count is used (MCSPI_XFERLEVEL[31-16] WCNT]), set the
bit field to WCNT[0] = 0.
- 16 ≤ WL Multiple MCSPI word access is not applicable.