SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
The base ADC clock is provided directly by the system clock (SYSCLK). SYSCLK is used to generate the ADC acquisition window. The register ADCCTL2 has a PRESCALE field that determines the ADCCLK. ADCCLK is used to clock the converter, and ADCCLK is only active during the conversion phase. At all other times, including during the sample-and-hold window, the ADCCLK signal is gated off.
In 12-bit mode, this process requires approximately 11.5 ADCLK cycles. The choice of resolution determines the necessary duration of the acquisition window.