SPRUJ17H March   2022  – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
      1.      Glossary
      2.      Trademarks
      3.      Export Control Notice
      4.      Related Documentation From Texas Instruments
    2.     8
    3.     Support Resources
    4.     Release History
  3. 1 Introduction
    1. 1.1 Overview
    2. 1.2 Device Block Diagram
    3. 1.3 Module Allocation and Instances
      1.      AM263x Register Addendum Link
    4. 1.4 Device Modules
      1.      Arm Cortex-R5F Processor (R5FSS)
      2. 1.4.1  Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
      3. 1.4.2  Hardware Security Module (HSM)
      4. 1.4.3  Real-time Control Subsystem (CONTROLSS)
      5. 1.4.4  Spinlock (SPINLOCK)
      6. 1.4.5  Enhanced Data Movement Architecture (EDMA)
      7. 1.4.6  General Purpose Input/Output Interface (GPIO)
      8. 1.4.7  Inter-Integrated Circuit Interface (I2C)
      9. 1.4.8  Serial Peripheral Interface (SPI)
      10. 1.4.9  Universal Asynchronous Receiver/Transmitter (UART)
      11. 1.4.10 3-port Gigabit Ethernet Switch (CPSW)
      12. 1.4.11 Quad Serial Peripheral Interface (QSPI)
      13. 1.4.12 General Purpose Memory Controller (GPMC)
      14. 1.4.13 Error Location Module (ELM)
      15. 1.4.14 Multi-Media Card/Secure Digital Interface (MMCSD)
      16. 1.4.15 Controller Area Network (MCAN)
      17. 1.4.16 Local Interconnect Network (LIN)
      18. 1.4.17 Timers
      19. 1.4.18 Internal Diagnostics Modules
    5. 1.5 Device Identification
  4. 2 Memory Map
    1. 2.1 Device Memory Map
    2. 2.2 R5FSS Memory Map
    3. 2.3 PRU-ICSS Memory Map
  5. 3 System Interconnect
    1. 3.1  System Interconnect Overview
    2. 3.2  CORE VBUSM Interconnect
    3. 3.3  CORE VBUSP Interconnect
    4. 3.4  PERI VBUSP Interconnect
    5. 3.5  INFRA0 VBUSP Interconnect
    6. 3.6  INFRA1 VBUSP Interconnect
    7. 3.7  CONTROLSS Interconnect
    8. 3.8  Interconnect Safety
    9. 3.9  Bus Safety Errors
      1. 3.9.1 Error Signaling Integration
      2. 3.9.2 Programming sequence
      3. 3.9.3 Diagnostic Check Mechanism
    10. 3.10 System Memory Protection Unit (MPU)/Firewalls
      1. 3.10.1 MPU Overview
      2. 3.10.2 MPU Instances
      3. 3.10.3 MPU Functional Description
        1. 3.10.3.1 Functional Operation
        2. 3.10.3.2 Protection of the MPU Configuration Registers
        3. 3.10.3.3 MPU Interrupt Requests
      4. 3.10.4 MPU Parameters
      5. 3.10.5 MPU Default HW Configuration
      6. 3.10.6 ISC (Initiator-side Security Control)
        1. 3.10.6.1 ID Allocation
          1. 3.10.6.1.1 65
  6. 4 Module Integration
    1. 4.1  ADC Integration
    2. 4.2  DAC Integration
    3. 4.3  eCAP Integration
    4. 4.4  EPWM Integration
    5. 4.5  EQEP Integration
    6. 4.6  FSI Integration
    7. 4.7  SDFM Integration
    8. 4.8  SOC_TIMESYNC_XBAR0 Integration
    9. 4.9  SOC_TIMESYNC_XBAR1 Integration
    10. 4.10 GPIO Integration
    11. 4.11 I2C Integration
    12. 4.12 SPI Integration
    13. 4.13 UART Integration
    14. 4.14 CPSW Integration
    15. 4.15 GPMC Integration
    16. 4.16 ELM Integration
    17. 4.17 MMCSD Integration
    18. 4.18 QSPI Integration
    19. 4.19 MCAN Integration
    20. 4.20 LIN Integration
    21. 4.21 RTI Integration
    22. 4.22 WWDT Integration
    23. 4.23 DCC Integration
    24. 4.24 ESM Integration
    25. 4.25 ECC Aggregator Integration
    26. 4.26 MCRC Integration
    27. 4.27 ICSSM_XBAR_INTROUTER Integration
    28. 4.28 GPIO_XBAR Integration
  7. 5 Initialization
    1. 5.1 Initialization Overview
      1. 5.1.1 ROM Code Overview
      2. 5.1.2 Bootloader Modes
      3. 5.1.3 Boot Terminology
    2. 5.2 Boot Process
      1. 5.2.1 Public ROM Code Architecture
        1. 5.2.1.1 Public ROM Entry
        2. 5.2.1.2 Main Module
        3. 5.2.1.3 Boot Loop
        4. 5.2.1.4 Modules
        5. 5.2.1.5 Drivers
        6. 5.2.1.6 IPC
    3. 5.3 Boot Mode Pins
      1. 5.3.1 BOOTMODE Pin Mapping
    4. 5.4 Boot Modes
      1. 5.4.1 QSPI Boot
        1. 5.4.1.1 QSPI (4S)
          1. 5.4.1.1.1 QSPI (4S) Bootloader Operation
          2. 5.4.1.1.2 QSPI (4S) Loading Process
        2. 5.4.1.2 QSPI (1S)
          1. 5.4.1.2.1 QSPI (1S) Bootloader Operation
          2. 5.4.1.2.2 QSPI (1S) Loading Process
      2. 5.4.2 UART Boot
        1. 5.4.2.1 UART Bootloader Operation
          1. 5.4.2.1.1 Initialization Process
          2. 5.4.2.1.2 UART Loading Process
            1. 5.4.2.1.2.1 UART XMODEM
          3. 5.4.2.1.3 UART Hand-Over Process
      3. 5.4.3 DevBoot
    5. 5.5 Redundant boot support
    6. 5.6 PLL Configuration
    7. 5.7 Secure Boot Flow
      1. 5.7.1 Overview
      2. 5.7.2 x509 Certificate Structure
      3. 5.7.3 Certificate expectations
      4. 5.7.4 Object Identifiers
        1. 5.7.4.1 Boot Information OID (1.3.6.1.4.1.294.1.1)
        2. 5.7.4.2 Software Revision OID (1.3.6.1.4.1.294.1.3)
        3. 5.7.4.3 Image Integrity OID (1.3.6.1.4.1.294.1.2)
        4. 5.7.4.4 Image Encryption OID (1.3.6.1.4.1.294.1.4)
        5. 5.7.4.5 Derivation OID (1.3.6.1.4.1.294.1.5)
        6. 5.7.4.6 Debug OID (1.3.6.1.4.1.294.1.8)
      5. 5.7.5 Binary Image Creation
      6. 5.7.6 Binary Image Verification
      7. 5.7.7 R5 SBL Handoff
      8. 5.7.8 HSM RunTime Handoff
      9. 5.7.9 Post Boot Status
        1. 5.7.9.1 R5
          1. 5.7.9.1.1 Memory
          2. 5.7.9.1.2 Clock
          3. 5.7.9.1.3 IP Blocks
          4. 5.7.9.1.4 Pinmux Settings
          5. 5.7.9.1.5 PBIST
        2. 5.7.9.2 Assets
    8. 5.8 Boot Image Format
      1. 5.8.1 Overall Structure
      2. 5.8.2 Generating X.509 Certificates
        1. 5.8.2.1 Key Generation
          1. 5.8.2.1.1 RSA Key Generation
        2. 5.8.2.2 Configuration Script
        3. 5.8.2.3 Image Data
    9. 5.9 Boot Memory Maps
      1. 5.9.1 Memory Layout/MPU
      2. 5.9.2 Logger
  8. 6 Device Configuration
    1. 6.1 Control Module
      1. 6.1.1 Control Overview
        1. 6.1.1.1 MMR Write Protection
        2. 6.1.1.2 MMR Access Error Interrupt
      2. 6.1.2 TOP_CTRL
        1. 6.1.2.1 TOP_CTRL Integration
      3. 6.1.3 MSS_CTRL
        1. 6.1.3.1 MSS_CTRL Integration
        2. 6.1.3.2 MSS_CTRL Functional Description
          1. 6.1.3.2.1  R5FSS CPU Global Configuration and Control
            1. 6.1.3.2.1.1 R5SS Lock Step/Dual Core Configuration
            2. 6.1.3.2.1.2 R5 Core Halting and Unhalting
            3. 6.1.3.2.1.3 R5 Wait-For-Interrupt (WFI)
          2. 6.1.3.2.2  Memory Initialization
            1. 6.1.3.2.2.1 R5 TCM Memory Initialization
            2. 6.1.3.2.2.2 L2 OCRAM and Mailbox RAM and EDMA RAM Memory Initialization
          3. 6.1.3.2.3  EDMA Configuration
            1. 6.1.3.2.3.1 EDMA Global Configuration and Event Aggregation
            2. 6.1.3.2.3.2 EDMA Error Aggregation
          4. 6.1.3.2.4  CPSW Global Configuration
          5. 6.1.3.2.5  ICSSM Global Configuration
          6. 6.1.3.2.6  GPMC Global Configuration
          7. 6.1.3.2.7  MPU Interrupt Aggregator
          8. 6.1.3.2.8  MMR Access Error Interrupt Aggregator
          9. 6.1.3.2.9  Safety Registers
            1. 6.1.3.2.9.1 R5 Memory ECC Error Aggregator
            2. 6.1.3.2.9.2 R5SS TCM Address Parity Error Aggregator
            3. 6.1.3.2.9.3 Interconnect Safety
          10. 6.1.3.2.10 MSS_CTRL MMR Kick Protection Registers
          11. 6.1.3.2.11 MSS_CTRL MMR Access Error Registers
      4. 6.1.4 CONTROLSS_CTRL (CTRLMMR2)
      5. 6.1.5 IOMUX (PADCFG_CTRLMMR0)
      6. 6.1.6 TOPRCM (RCM_CTRLMMR0): SoC-level Clock and Reset control registers
      7. 6.1.7 MSS_RCM (RCM_CTRLMMR1): SoC and Peripheral-level Clock and Reset control registers
    2. 6.2 Power
      1. 6.2.1 Power Management Overview
      2. 6.2.2 Power Management Unit
        1. 6.2.2.1 PMU Reference System (REFSYS)
          1. 6.2.2.1.1 Power OK (POK) Modules
          2. 6.2.2.1.2 Power on Reset module
        2. 6.2.2.2 PMU Safety System (SAFETYSYS)
          1. 6.2.2.2.1 Power OK (POK) Modules
          2. 6.2.2.2.2 Thermal Manager
            1. 6.2.2.2.2.1 Thermal Manager Features
            2. 6.2.2.2.2.2 Thermal Manager Functional Description
            3. 6.2.2.2.2.3 Thermal FSM
            4. 6.2.2.2.2.4 Thermal Alert Comparator
            5. 6.2.2.2.2.5 Temperature Timestamp Registers
            6. 6.2.2.2.2.6 FIFO Management
            7. 6.2.2.2.2.7 ADC Values Versus Temperature
      3. 6.2.3 Power Control Modules
        1. 6.2.3.1 Clock ICG controls
        2. 6.2.3.2 L2OCRAM Power Control
      4. 6.2.4 Device Power States
        1. 6.2.4.1 Overview of Device Power Modes
        2. 6.2.4.2 Device Power States and Transitions
    3. 6.3 Reset
      1. 6.3.1 Overview
        1. 6.3.1.1 SoC Supported Resets
      2. 6.3.2 Reset Details
        1. 6.3.2.1 PORz Reset
        2. 6.3.2.2 Warm Resets
          1. 6.3.2.2.1 Warm Reset by WARMRSTn HW Pin
          2. 6.3.2.2.2 Internal Warm Reset Sources
            1. 6.3.2.2.2.1 Debugger Reset
            2. 6.3.2.2.2.2 WDT Resets
          3. 6.3.2.2.3 SW Warm Reset
        3. 6.3.2.3 Local Module Resets
        4. 6.3.2.4 R5FSS Reset
        5. 6.3.2.5 Reset - High Heating Value (HHV)
      3. 6.3.3 Core and Cluster Reset logic
      4. 6.3.4 Reset Status
      5. 6.3.5 Reset Registers
      6. 6.3.6 Reset Power up Sequence
    4. 6.4 Clocking
      1. 6.4.1 Overview
        1. 6.4.1.1 Analog Modules
          1. 6.4.1.1.1 PLL Module
          2. 6.4.1.1.2 CORE PLL Overview
          3. 6.4.1.1.3 PER PLL Overview
          4. 6.4.1.1.4 PLL Hookup
          5. 6.4.1.1.5 HSDIVIDER Module
        2. 6.4.1.2 R5SS and SYSCLK Clock Tree
      2. 6.4.2 Clock IO
        1. 6.4.2.1 Overview
        2. 6.4.2.2 Clock IO Mapping
      3. 6.4.3 IP Clocking
        1. 6.4.3.1 IP Clocks Having GCM
        2. 6.4.3.2 IP Clocks working on SYS_CLK
        3. 6.4.3.3 Clock Selection
      4. 6.4.4 Clock Gating
      5. 6.4.5 Limp Mode
      6. 6.4.6 Clocking Registers
      7. 6.4.7 Programming Guide
        1. 6.4.7.1 PLL and Root Clocks Programming Guide
          1. 6.4.7.1.1 PLL Configurations
            1. 6.4.7.1.1.1 Kick Protection Mechanism
            2. 6.4.7.1.1.2 Sequence to Configure the CORE PLL
            3. 6.4.7.1.1.3 Sequence to Configure the PER PLL
            4. 6.4.7.1.1.4 Sequence to Re-Configure the PLL
          2. 6.4.7.1.2 Root Clock Configurations
            1. 6.4.7.1.2.1 Sequence for Programming SYS and R5 Clocks
            2. 6.4.7.1.2.2 Sequence for Programming TRACE Clock
            3. 6.4.7.1.2.3 Sequence for Programming CLKOUT Clock
        2. 6.4.7.2 IP Clock Configurations
          1. 6.4.7.2.1  RTI CLOCK
          2. 6.4.7.2.2  WDT CLOCK
          3. 6.4.7.2.3  QSPI CLOCK
          4. 6.4.7.2.4  MCSPI CLOCK
          5. 6.4.7.2.5  I2C CLOCK
          6. 6.4.7.2.6  LIN_UART CLOCK
          7. 6.4.7.2.7  ICSSM UART CLOCK
          8. 6.4.7.2.8  MCAN CLOCK
          9. 6.4.7.2.9  MMCx CLOCK
          10. 6.4.7.2.10 CPTS CLOCK
          11. 6.4.7.2.11 HSM RTI CLOCK
          12. 6.4.7.2.12 HSM WDT CLOCK
          13. 6.4.7.2.13 HSM RTC CLOCK
          14. 6.4.7.2.14 HSM DMTA CLOCK
          15. 6.4.7.2.15 HSM DMTB CLOCK
          16. 6.4.7.2.16 GPMC CLOCK
          17. 6.4.7.2.17 CONTROLSS PLL CLOCK
          18. 6.4.7.2.18 RGMII5 CLK
          19. 6.4.7.2.19 RGMII50 CLK
          20. 6.4.7.2.20 RGMII250 CLK
          21. 6.4.7.2.21 XTAL MMC 32K CLOCK
          22. 6.4.7.2.22 XTAL TEMPSENSE 32K CLOCK
          23. 6.4.7.2.23 MSS_ELM CLOCK
  9. 7 Processors and Accelerators
    1. 7.1 Arm Cortex R5F Subsystem (R5FSS)
      1. 7.1.1 R5FSS Overview
        1. 7.1.1.1 R5FSS Features
        2. 7.1.1.2 R5FSS Not Supported Features
      2. 7.1.2 R5FSS Integration
        1. 7.1.2.1 R5FSS Integration
      3. 7.1.3 R5FSS Functional Description
        1. 7.1.3.1  R5FSS Block Diagram
        2. 7.1.3.2  R5FSS Cortex-R5F Core
          1. 7.1.3.2.1 L1 Caches
          2. 7.1.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 7.1.3.2.3 R5FSS Special Signals
        3. 7.1.3.3  R5FSS Interfaces
          1. 7.1.3.3.1 Initiator Interfaces
          2. 7.1.3.3.2 Target Interfaces
        4. 7.1.3.4  R5FSS Power, Clocking and Reset
          1. 7.1.3.4.1 R5FSS Power
          2. 7.1.3.4.2 R5FSS Clocking
          3. 7.1.3.4.3 R5FSS Reset
          4. 7.1.3.4.4 R5FSS Reset Sequencing
        5. 7.1.3.5  R5FSS Vectored Interrupt Manager (VIM)
        6. 7.1.3.6  R5FSS ECC Support
        7. 7.1.3.7  R5FSS Memory View
        8. 7.1.3.8  R5FSS Interrupts
        9. 7.1.3.9  R5FSS Debug and Trace
        10. 7.1.3.10 R5FSS Boot Options
        11. 7.1.3.11 R5FSS Events
          1. 7.1.3.11.1 R5FSS Core Memory ECC Events
        12. 7.1.3.12 R5FSS TCM Address Parity Error
        13. 7.1.3.13 R5FSS Lockstep Compare
          1. 7.1.3.13.1 Overview
            1. 7.1.3.13.1.1 Main Features
            2. 7.1.3.13.1.2 Block Diagram
          2. 7.1.3.13.2 Module Operation
            1. 7.1.3.13.2.1 CPU/VIM Output Compare Diagnostic
              1. 7.1.3.13.2.1.1 Active Compare lockstep Mode
              2. 7.1.3.13.2.1.2 Self-Test Mode
                1. 7.1.3.13.2.1.2.1 Compare Match Test
                2. 7.1.3.13.2.1.2.2 Compare Mismatch Test
              3. 7.1.3.13.2.1.3 Error Forcing Mode
              4. 7.1.3.13.2.1.4 Self-Test Error Forcing Mode
            2. 7.1.3.13.2.2 CPU Input Inversion Diagnostic
            3. 7.1.3.13.2.3 Checker CPU Inactivity Monitor
              1. 7.1.3.13.2.3.1 Active Compare Mode
              2. 7.1.3.13.2.3.2 Self-Test Mode
                1. 7.1.3.13.2.3.2.1 Compare Match Test
                2. 7.1.3.13.2.3.2.2 Compare Mismatch Test
              3. 7.1.3.13.2.3.3 Error Forcing Mode
              4. 7.1.3.13.2.3.4 Self-Test Error Forcing Mode
            4. 7.1.3.13.2.4 Operation During CPU Debug Mode
          3. 7.1.3.13.3 Control Registers
            1. 7.1.3.13.3.1 CCM-R5F Status Register 1 (CCMSR1)
            2. 7.1.3.13.3.2 CCM-R5F Key Register 1 (CCMKEYR1)
            3. 7.1.3.13.3.3 CCM-R5F Status Register 2 (CCMSR2)
            4. 7.1.3.13.3.4 CCM-R5F Key Register 2 (CCMKEYR2)
            5. 7.1.3.13.3.5 CCM-R5F Status Register 3 (CCMSR3)
            6. 7.1.3.13.3.6 CCM-R5F Key Register 3 (CCMKEYR3)
            7. 7.1.3.13.3.7 CCM-R5F Polarity Control Register (CCMPOLCNTRL)
        14. 7.1.3.14 R5FSS Selftest Logic
    2. 7.2 Programmable Real-Time Unit Subsystem (PRU-ICSS)
      1. 7.2.1  PRU-ICSS Overview
        1. 7.2.1.1 PRU-ICSS Key Features
        2. 7.2.1.2 Not Supported Features
        3.       353
      2. 7.2.2  PRU-ICSS Environment
        1. 7.2.2.1 PRU-ICSS Internal Pinmux
          1.        PRU-ICSS I/O Signals
        2.       357
      3. 7.2.3  PRU-ICSS Integration
      4. 7.2.4  PRU-ICSS Top Level Resources Functional Description
        1. 7.2.4.1 PRU-ICSS Reset Management
        2. 7.2.4.2 PRU-ICSS Power and Clock Management
          1. 7.2.4.2.1 PRU-ICSS CORE Clock Generation
          2. 7.2.4.2.2 PRU-ICSS Protect
          3. 7.2.4.2.3 Module Clock Configurations at PRU-ICSS Top Level
        3. 7.2.4.3 Other PRU-ICSS Module Functional Registers at Subsystem Level
        4. 7.2.4.4 PRU-ICSS Memory Maps
          1. 7.2.4.4.1 PRU-ICSS Local Memory Map
            1. 7.2.4.4.1.1 PRU-ICSS Local Instruction Memory Map
            2. 7.2.4.4.1.2 PRU-ICSS Local Data Memory Map
          2. 7.2.4.4.2 PRU-ICSS Global Memory Map
        5.       371
      5. 7.2.5  PRU-ICSS PRU Cores
        1. 7.2.5.1 PRU Cores Overview
        2. 7.2.5.2 PRU Cores Functional Description
          1. 7.2.5.2.1 PRU Constant Table
          2. 7.2.5.2.2 PRU Module Interface
            1. 7.2.5.2.2.1 Real-Time Status Interface Mapping (R31): Interrupt Events Input
            2. 7.2.5.2.2.2 Event Interface Mapping (R31): PRU System Events
            3. 7.2.5.2.2.3 General-Purpose Inputs (R31): Enhanced PRU GP Module
              1. 7.2.5.2.2.3.1 PRU EGPIs Direct Input
              2. 7.2.5.2.2.3.2 PRU EGPIs 16-Bit Parallel Capture
              3. 7.2.5.2.2.3.3 PRU EGPIs 28-Bit Shift In
                1. 7.2.5.2.2.3.3.1 PRU EGPI Programming Model
              4. 7.2.5.2.2.3.4 General-Purpose Outputs (R30): Enhanced PRU GP Module
                1. 7.2.5.2.2.3.4.1 PRU EGPOs Direct Output
                2. 7.2.5.2.2.3.4.2 PRU EGPO Shift Out
                  1. 2.5.2.2.3.4.2.1 PRU EGPO Programming Model
              5. 7.2.5.2.2.3.5 Sigma Delta (SD) Decimation Filtering
                1. 7.2.5.2.2.3.5.1 Sigma Delta Block Diagram and Signals
                2. 7.2.5.2.2.3.5.2 PRU R30 / R31 Interface
                3. 7.2.5.2.2.3.5.3 Sigma Delta Description
                4. 7.2.5.2.2.3.5.4 Sigma Delta Basic Programming Example
              6. 7.2.5.2.2.3.6 Three Channel Peripheral Interface
                1. 7.2.5.2.2.3.6.1 Peripheral Interface Block Diagram and Signal Configuration
                2. 7.2.5.2.2.3.6.2 PRU R30 and R31 Interface
                3. 7.2.5.2.2.3.6.3 Clock Generation
                  1. 2.5.2.2.3.6.3.1 Configuration
                  2. 2.5.2.2.3.6.3.2 Clock Output Start Conditions
                    1. 5.2.2.3.6.3.2.1 TX Mode (RX_EN = 0)
                    2. 5.2.2.3.6.3.2.2 RX Mode (RX_EN = 1)
                  3. 2.5.2.2.3.6.3.3 Stop Conditions
                4. 7.2.5.2.2.3.6.4 Three Peripheral Mode Basic Programming Model
                  1. 2.5.2.2.3.6.4.1 Clock Generation
                  2. 2.5.2.2.3.6.4.2 TX - Single Shot
                  3. 2.5.2.2.3.6.4.3 TX - Continuous FIFO Loading
                  4. 2.5.2.2.3.6.4.4 RX - Auto Arm or Non-Auto Arm
        3. 7.2.5.3 PRU-ICSS RAM Index Allocation
        4.       408
      6. 7.2.6  PRU-ICSS Broadside Accelerators
        1. 7.2.6.1 PRU-ICSS Broadside Accelerators Overview
        2. 7.2.6.2 PRU-ICSS Data Processing Accelerators Functional
          1. 7.2.6.2.1 PRU Multiplier with Accumulation (MPY/MAC)
            1. 7.2.6.2.1.1 PRU MAC Operations
              1. 7.2.6.2.1.1.1 PRU versus MAC Interface
              2. 7.2.6.2.1.1.2 Multiply only mode(default state), MAC_MODE = 0
                1. 7.2.6.2.1.1.2.1 Programming PRU MAC in "Multiply-ONLY" mode
              3. 7.2.6.2.1.1.3 Multiply and Accumulate Mode, MAC_MODE = 1
                1. 7.2.6.2.1.1.3.1 Programming PRU MAC in Multiply and Accumulate Mode
          2. 7.2.6.2.2 PRU CRC16/32 Module
            1. 7.2.6.2.2.1 PRU and CRC16/32 Interface
            2. 7.2.6.2.2.2 CRC Programming Model
            3. 7.2.6.2.2.3 PRU and CRC16/32 Interface (R9:R2)
          3. 7.2.6.2.3 PRU-ICSS Scratch Pad Memory
            1. 7.2.6.2.3.1 PRU0/1 Scratch Pad Overview
            2. 7.2.6.2.3.2 PRU0 /1 Scratch Pad Operations
              1. 7.2.6.2.3.2.1 Optional XIN/XOUT Shift
              2. 7.2.6.2.3.2.2 Scratch Pad Operations Examples
        3. 7.2.6.3 PRU-ICSS Data Movement Accelerators Functional
          1. 7.2.6.3.1 PRU-ICSS XFR2VBUS Hardware Accelerator
            1. 7.2.6.3.1.1 Blocking Conditions
            2. 7.2.6.3.1.2 Read Operation with Auto Disabled
            3. 7.2.6.3.1.3 Read Operation with Auto Enabled
            4. 7.2.6.3.1.4 PRU to XFR2VBUS Interface
            5. 7.2.6.3.1.5 XFR2VBUS Programming Model
        4.       435
      7. 7.2.7  PRU-ICSS Local INTC
        1. 7.2.7.1 PRU-ICSS Interrupt Controller Functional Description
          1. 7.2.7.1.1 PRU-ICSS Interrupt Controller System Events Flow
            1. 7.2.7.1.1.1 PRU-ICSS Interrupt Processing
              1. 7.2.7.1.1.1.1 PRU-ICSS Interrupt Enabling
            2. 7.2.7.1.1.2 PRU-ICSS Interrupt Status Checking
            3. 7.2.7.1.1.3 PRU-ICSS Interrupt Channel Mapping
              1. 7.2.7.1.1.3.1 PRU-ICSS Host Interrupt Mapping
              2. 7.2.7.1.1.3.2 PRU-ICSS Interrupt Prioritization
            4. 7.2.7.1.1.4 PRU-ICSS Interrupt Nesting
            5. 7.2.7.1.1.5 PRU-ICSS Interrupt Status Clearing
          2. 7.2.7.1.2 PRU-ICSS Interrupt Disabling
        2. 7.2.7.2 PRU-ICSS Interrupt Controller Basic Programming Model
        3. 7.2.7.3 PRU-ICSS Interrupt Requests Mapping
        4.       450
      8. 7.2.8  PRU-ICSS UART Module
        1. 7.2.8.1 PRU-ICSS UART Overview
        2. 7.2.8.2 PRU-ICSS UART Environment
          1. 7.2.8.2.1 PRU-ICSS UART Pin Multiplexing
          2. 7.2.8.2.2 PRU-ICSS UART Signal Descriptions
          3. 7.2.8.2.3 PRU-ICSS UART Protocol Description and Data Format
            1. 7.2.8.2.3.1 PRU-ICSS UART Transmission Protocol
            2. 7.2.8.2.3.2 PRU-ICSS UART Reception Protocol
            3. 7.2.8.2.3.3 PRU-ICSS UART Data Format
              1. 7.2.8.2.3.3.1 Frame Formatting
          4. 7.2.8.2.4 PRU-ICSS UART Clock Generation and Control
        3. 7.2.8.3 PRU-ICSS UART Functional Description
          1. 7.2.8.3.1 PRU-ICSS UART Functional Block Diagram
          2. 7.2.8.3.2 PRU-ICSS UART Reset Considerations
            1. 7.2.8.3.2.1 PRU-ICSS UART Software Reset Considerations
            2. 7.2.8.3.2.2 PRU-ICSS UART Hardware Reset Considerations
          3. 7.2.8.3.3 PRU-ICSS UART Power Management
          4. 7.2.8.3.4 PRU-ICSS UART Interrupt Support
            1. 7.2.8.3.4.1 PRU-ICSS UART Interrupt Events and Requests
            2. 7.2.8.3.4.2 PRU-ICSS UART Interrupt Multiplexing
          5. 7.2.8.3.5 PRU-ICSS UART DMA Event Support
          6. 7.2.8.3.6 PRU-ICSS UART Operations
            1. 7.2.8.3.6.1 PRU-ICSS UART FIFO Modes
              1. 7.2.8.3.6.1.1 PRU-ICSS UART FIFO Interrupt Mode
              2. 7.2.8.3.6.1.2 PRU-ICSS UART FIFO Poll Mode
            2. 7.2.8.3.6.2 PRU-ICSS UART Autoflow Control
              1. 7.2.8.3.6.2.1 PRU-ICSS UART Signal UART0_RTS Behavior
              2. 7.2.8.3.6.2.2 PRU-ICSS UART Signal UART0_CTS Behavior
            3. 7.2.8.3.6.3 PRU-ICSS UART Loopback Control
          7. 7.2.8.3.7 PRU-ICSS UART Emulation Considerations
          8. 7.2.8.3.8 PRU-ICSS UART Exception Processing
            1. 7.2.8.3.8.1 PRU-ICSS UART Divisor Latch Not Programmed
            2. 7.2.8.3.8.2 Changing Operating Mode During Busy Serial Communication of PRU-ICSS UART
        4.       484
      9. 7.2.9  PRU-ICSS ECAP Module
        1. 7.2.9.1 PRU-ICSS eCAP Overview
          1. 7.2.9.1.1 Purpose of the PRU-ICSS eCAP Peripheral
          2. 7.2.9.1.2 PRU-ICSS eCAP Features
        2. 7.2.9.2 PRU-ICSS ECAP Functional Description
          1. 7.2.9.2.1 PRU-ICSS Capture and APWM Operating Mode
          2. 7.2.9.2.2 PRU-ICSS eCAP Capture Mode Description
            1. 7.2.9.2.2.1 PRU-ICSS eCAP Event Prescaler
            2. 7.2.9.2.2.2 PRU-ICSS eCAP Edge Polarity Select and Qualifier
            3. 7.2.9.2.2.3 eCAP Continuous/One-Shot Control
            4. 7.2.9.2.2.4 PRU-ICSS eCAP 32-bit Counter and Phase Control
            5. 7.2.9.2.2.5 PRU-ICSS Enhanced Capture CAP1-CAP4 Registers
            6. 7.2.9.2.2.6 PRU-ICSS eCAP Interrupt Control
            7. 7.2.9.2.2.7 PRU-ICSS eCAP Shadow Load and Lockout Control
            8. 7.2.9.2.2.8 CEVT Flag Registers
          3. 7.2.9.2.3 PRU-ICSS eCAP Module APWM Mode Operation
        3.       501
      10. 7.2.10 PRU-ICSS MII_RT Module
        1. 7.2.10.1 PRU-ICSS MII_RT Introduction
          1. 7.2.10.1.1 PRU-ICSS MII_RT Features
          2. 7.2.10.1.2 Unsupported Features
          3. 7.2.10.1.3 PRU-ICSS MII_RT Block Diagram
        2. 7.2.10.2 MII_RT Functional Description
          1. 7.2.10.2.1 MII_RT Data Path Configuration
            1. 7.2.10.2.1.1 Auto-forward with Optional PRU Snoop
            2. 7.2.10.2.1.2 8- or 16-bit Processing with On-the-Fly Modifications
            3. 7.2.10.2.1.3 32-byte Double Buffer or Ping-Pong Processing
          2. 7.2.10.2.2 MII_RT Definition and Terms
            1. 7.2.10.2.2.1 MII_RT Data Frame Structure
            2. 7.2.10.2.2.2 PRU R30 and R31
            3. 7.2.10.2.2.3 RX and TX L1 FIFO Data Movement
            4. 7.2.10.2.2.4 Receive CRC Computation
            5. 7.2.10.2.2.5 Transmit CRC Computation
            6. 7.2.10.2.2.6 Transmit CRC Computation for fragmented frames
          3. 7.2.10.2.3 RX MII Interface
            1. 7.2.10.2.3.1 RX MII Receive Data Latch
            2. 7.2.10.2.3.2 RX MII Start of Frame Detection
            3. 7.2.10.2.3.3 CRC Error Detection
            4. 7.2.10.2.3.4 RX Error Detection and Action
            5. 7.2.10.2.3.5 RX Data Path Options to PRU
            6. 7.2.10.2.3.6 RX MII Port → RX L1 FIFO → PRU
            7. 7.2.10.2.3.7 RX MII Port → RX L1 FIFO → RX L2 Buffer → PRU
              1. 7.2.10.2.3.7.1 RX L2 Status in mode 0, none IET mode (when ICSS_M_CFG[2] RX_L2_G_EN= 0h)
              2. 7.2.10.2.3.7.2 RX L2 XFR Identification
              3. 7.2.10.2.3.7.3 RX L2 XFR Status
              4. 7.2.10.2.3.7.4 Broadside Stitch FIFO
          4. 7.2.10.2.4 PRU-ICSS TX MII Interface
            1. 7.2.10.2.4.1 TX Data Path Options to TX L1 FIFO
              1. 7.2.10.2.4.1.1 PRU → TX L1 FIFO → TX MII Port
                1. 7.2.10.2.4.1.1.1 TX L2 FIFO Features
                2. 7.2.10.2.4.1.1.2 TX Insertion
                3. 7.2.10.2.4.1.1.3 TX Preemption
                  1. 2.10.2.4.1.1.3.1 TX Preemption Programming Model
              2. 7.2.10.2.4.1.2 RX L1 FIFO → TX L1 FIFO (Direct Connection) → TX MII Port
          5. 7.2.10.2.5 PRU R31 Command Interface
          6. 7.2.10.2.6 Other Configuration Options
            1. 7.2.10.2.6.1 Nibble and Byte Order
            2. 7.2.10.2.6.2 MII_RT Preamble Source
            3. 7.2.10.2.6.3 PRU and MII Port Multiplexer
              1. 7.2.10.2.6.3.1 Receive Multiplexer
              2. 7.2.10.2.6.3.2 Transmit Multiplexer
            4. 7.2.10.2.6.4 RX L2 Scratch Pad
        3.       547
      11. 7.2.11 PRU-ICSS MII MDIO Module
        1. 7.2.11.1 PRU-ICSS MII MDIO Overview
        2. 7.2.11.2 PRU-ICSS MII MDIO Functional Description
          1. 7.2.11.2.1 MDIO Clause 22 Frame Formats
            1. 7.2.11.2.1.1 PRU-ICSS MDIO Control and Interface Signals
          2. 7.2.11.2.2 MDIO Clause 45 Frame Formats
          3. 7.2.11.2.3 PRU-ICSS MII MDIO Interractions
          4. 7.2.11.2.4 PRU-ICSS MII MDIO Interrupts
            1. 7.2.11.2.4.1 Normal Mode ([30]STATECHANGEMODE = 0h)
            2. 7.2.11.2.4.2 State Change Mode ([30]STATECHANGEMODE = 1h)
          5. 7.2.11.2.5 Manual Mode
        3. 7.2.11.3 PRU-ICSS MII MDIO Receive/Transmit Frame Host Software Interface
        4.       560
      12. 7.2.12 PRU-ICSS IEP
        1. 7.2.12.1 PRU-ICSS IEP Overview
        2. 7.2.12.2 PRU-ICSS IEP Functional Description
          1. 7.2.12.2.1 PRU-ICSS IEP Clock Generation
          2. 7.2.12.2.2 PRU-ICSS IEP Timer
            1. 7.2.12.2.2.1 PRU-ICSS IEP Timer Features
          3. 7.2.12.2.3 32-Bit Shadow Mode
          4. 7.2.12.2.4 PRU-ICSS IEP Timer Basic Programming Sequence
          5. 7.2.12.2.5 Industrial Ethernet Mapping
          6. 7.2.12.2.6 PRU-ICSS IEP Sync0/Sync1 Module
            1. 7.2.12.2.6.1 PRU-ICSS IEP Sync0/Sync1 Features
            2. 7.2.12.2.6.2 PRU-ICSS IEP Sync0/Sync1 Generation Modes
          7. 7.2.12.2.7 PRU-ICSS IEP WatchDog
          8. 7.2.12.2.8 PRU-ICSS IEP DIGIO
            1. 7.2.12.2.8.1 PRU-ICSS IEP DIGIO Features
            2. 7.2.12.2.8.2 PRU-ICSS IEP DIGIO Block Diagrams
            3. 7.2.12.2.8.3 PRU-ICSS IEP Basic Programming Model
        3.       578
    3. 7.3 Hardware Security Module (HSM)
      1. 7.3.1 Security Features
      2. 7.3.2 Security Features not Supported
      3. 7.3.3 Security Device Types
      4. 7.3.4 Crypto Hardware Accelerators
        1. 7.3.4.1 DTHE
          1. 7.3.4.1.1 DMA Channel Map
          2. 7.3.4.1.2 HSM_DTHE Memory Map
        2. 7.3.4.2 CRC Engine
          1. 7.3.4.2.1 Overview
          2. 7.3.4.2.2 Endian Configuration
          3. 7.3.4.2.3 CRC Programming Model
        3. 7.3.4.3 AES Engine - Symmetric Encryption and Decryption
          1. 7.3.4.3.1 Functional Description
          2. 7.3.4.3.2 Global Control FSM and DMA I/O
          3. 7.3.4.3.3 Register Interface
          4. 7.3.4.3.4 AES Wide-bus Engine
            1. 7.3.4.3.4.1 Mode Control FSM
            2. 7.3.4.3.4.2 AES Key Scheduler (aes ctrl)
            3. 7.3.4.3.4.3 AES Encrypt Core (aes enc)
            4. 7.3.4.3.4.4 AES Decrypt Core (aes dec)
            5. 7.3.4.3.4.5 AES Feedback Mode Block
            6. 7.3.4.3.4.6 GHASH Block
            7. 7.3.4.3.4.7 Key Selection Mechanism
          5. 7.3.4.3.5 AES Algorithm
          6. 7.3.4.3.6 Supported Modes of Operation
            1. 7.3.4.3.6.1  ECB Feedback Mode
            2. 7.3.4.3.6.2  CBC Feedback Mode
            3. 7.3.4.3.6.3  CTR Feedback Mode
            4. 7.3.4.3.6.4  CFB128 Feedback Mode
            5. 7.3.4.3.6.5  f8 Feedback Mode
            6. 7.3.4.3.6.6  XTS Operation
            7. 7.3.4.3.6.7  f9 Authentication Mode
            8. 7.3.4.3.6.8  CBC-MAC Authentication Mode
            9. 7.3.4.3.6.9  GCM Operation
            10. 7.3.4.3.6.10 CCM Operation
          7. 7.3.4.3.7 Extended/Combined Modes of Operations
            1. 7.3.4.3.7.1 XTS Pre-calculation
            2. 7.3.4.3.7.2 GCM Protocol Operation
            3. 7.3.4.3.7.3 CCM Protocol Operation
          8. 7.3.4.3.8 AES Module Programming Guide
            1. 7.3.4.3.8.1 AES Low-Level Programming Models
              1. 7.3.4.3.8.1.1 Global Initialization
              2. 7.3.4.3.8.1.2 Initialization Subsequence
              3. 7.3.4.3.8.1.3 Operational Modes Configuration
              4. 7.3.4.3.8.1.4 AES Events Servicing
          9. 7.3.4.3.9 HSM_AES Memory Map
        4. 7.3.4.4 Asymmetric Cryptography
          1. 7.3.4.4.1 Public Key Accelerator (PKA)
            1. 7.3.4.4.1.1 PKA Introduction and Features
            2. 7.3.4.4.1.2 PKA Embedded Memories
            3. 7.3.4.4.1.3 PKA Clock Management
            4. 7.3.4.4.1.4 PKA PKCP Operations
            5. 7.3.4.4.1.5 PKA LNME Operations
              1. 7.3.4.4.1.5.1 LNME Unit Operational Parameters
              2. 7.3.4.4.1.5.2 LNME MMM Type Operations (MMM, MMMNEXT, MMM3A)
                1. 7.3.4.4.1.5.2.1 LNME Actual Usage of MMM-type Operations
              3. 7.3.4.4.1.5.3 LNME MMEXP Operation
                1. 7.3.4.4.1.5.3.1 PKA Exponent Re-coding
                2. 7.3.4.4.1.5.3.2 Actual Usage of the MMEXP Operation
            6. 7.3.4.4.1.6 PKA GF(2m) Operations
              1. 7.3.4.4.1.6.1 GF2m CLR Operation
              2. 7.3.4.4.1.6.2 GF2m COPY Operation
              3. 7.3.4.4.1.6.3 GF2m ADD Operation
              4. 7.3.4.4.1.6.4 GF2m MUL Operation
                1. 7.3.4.4.1.6.4.1 GF2m Multiplications
                  1. 3.4.4.1.6.4.1.1 Operand and Polynomial Loading for Multiplication
                  2. 3.4.4.1.6.4.1.2 Aspects of the GF(2m) Multiplication Operation
              5. 7.3.4.4.1.6.5 GF2m SXL Operation
              6. 7.3.4.4.1.6.6 GF2m DEGREE Operation
            7. 7.3.4.4.1.7 PKA Sequencer Controlled Operations
              1. 7.3.4.4.1.7.1 Sequencer Command Execution
              2. 7.3.4.4.1.7.2 Sequencer Complex Commands
                1. 7.3.4.4.1.7.2.1 Alignment Words
                2. 7.3.4.4.1.7.2.2 Buffer Words
              3. 7.3.4.4.1.7.3 Sequencer Command Descriptions
                1. 7.3.4.4.1.7.3.1 Operations for Modular Exponentiation
                2. 7.3.4.4.1.7.3.2 Operations for Modular Inversion
                  1. 3.4.4.1.7.3.2.1 Modular Inversion for Regular Numbers
                  2. 3.4.4.1.7.3.2.2 Modular Inversion for Binary Fields
                  3. 3.4.4.1.7.3.2.3 Modular Inversion with an Even Modulus (Special Case)
                  4. 3.4.4.1.7.3.2.4 Modular Inversion with a Prime Modulus (Special Case)
                3. 7.3.4.4.1.7.3.3 Operations for ECC on Curves over Prime Fields
                4. 7.3.4.4.1.7.3.4 Operations for ECC on Curves over Binary Fields
                5. 7.3.4.4.1.7.3.5 Single-command ECDSAp Signature Generation and Verification
                6. 7.3.4.4.1.7.3.6 Basic Operations for Montgomery Curves (Curve25519 and Curve448)
              4. 7.3.4.4.1.7.4 Sequencer Operation Examples
                1. 7.3.4.4.1.7.4.1 MODEXP-CRT Operation Example
                2. 7.3.4.4.1.7.4.2 ECpMULxyz Operation Example
              5. 7.3.4.4.1.7.5 Sequencer Firmware Download
            8. 7.3.4.4.1.8 PKA Operation Sequences Basics
            9. 7.3.4.4.1.9 PKA Memory Address Space Assignment
          2. 7.3.4.4.2 HSM_PKA_RAM Memory Map
        5. 7.3.4.5 Hashing Function
          1. 7.3.4.5.1 SHA/MD5 Functional Description
            1. 7.3.4.5.1.1 SHA/MD5 Block Diagram
              1. 7.3.4.5.1.1.1 Configuration Registers
              2. 7.3.4.5.1.1.2 Hash/HMAC Engine
              3. 7.3.4.5.1.1.3 Hash Core Control
              4. 7.3.4.5.1.1.4 Host Interface Bank
            2. 7.3.4.5.1.2 DMA and Interrupt Requests
            3. 7.3.4.5.1.3 Operation Description
              1. 7.3.4.5.1.3.1 SHA Mode
                1. 7.3.4.5.1.3.1.1 Starting a New Hash
                2. 7.3.4.5.1.3.1.2 Outer Digest Registers
                  1. 3.4.5.1.3.1.2.1 Outer Digest Register Tables
                3. 7.3.4.5.1.3.1.3 Inner Digest Registers
                  1. 3.4.5.1.3.1.3.1 Inner Digest Registers Table
                4. 7.3.4.5.1.3.1.4 Closing a Hash
              2. 7.3.4.5.1.3.2 MD5 Mode
                1. 7.3.4.5.1.3.2.1 Starting a New Hash
                2. 7.3.4.5.1.3.2.2 Closing a Hash
              3. 7.3.4.5.1.3.3 Generating a Software Interrupt
            4. 7.3.4.5.1.4 SHA/MD5 Programming Guide
              1. 7.3.4.5.1.4.1 Global Initialization
                1. 7.3.4.5.1.4.1.1 Surrounding Modules Global Initialization
                2. 7.3.4.5.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
                  1. 3.4.5.1.4.1.2.1 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
                3. 7.3.4.5.1.4.1.3 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
                4. 7.3.4.5.1.4.1.4 Operational Modes Configuration
                5. 7.3.4.5.1.4.1.5 SHA/MD5 Event Servicing
                  1. 3.4.5.1.4.1.5.1 Interrupt Servicing
          2. 7.3.4.5.2 HSM_SHA Memory Map
        6. 7.3.4.6 Random Number Generator
          1. 7.3.4.6.1 True Random Number Generator (TRNG) with DRBG
            1. 7.3.4.6.1.1 TRNG Introduction and Features
            2. 7.3.4.6.1.2 TRNG Operation Sequences
              1. 7.3.4.6.1.2.1 Starting up and Obtaining Random Data Without a DRBG
              2. 7.3.4.6.1.2.2 SP 800-90A DRBG 'Initialize' Operation
              3. 7.3.4.6.1.2.3 SP 800-90A DRBG 'Reseed' Operation
              4. 7.3.4.6.1.2.4 SP 800-90A DRBG 'Generate' Operation
            3. 7.3.4.6.1.3 TRNG Clock Configuration for First Random Value Generation
            4. 7.3.4.6.1.4 TRNG Sampling Rate Selection
            5. 7.3.4.6.1.5 TRNG Secure Reading Mode
            6. 7.3.4.6.1.6 TRNG Software Operating Strategies
          2. 7.3.4.6.2 HSM_TRNG Memory Map
      5. 7.3.5 How to Request Access for HSM Addendum
    4. 7.4 Real-time Control Subsystem (CONTROLSS)
      1. 7.4.1  Real-time Control Subsystem (CONTROLSS) Overview
      2. 7.4.2  Analog-to-Digital Converter (ADC)
        1. 7.4.2.1  Introduction
          1. 7.4.2.1.1 Features
        2. 7.4.2.2  ADC Integration
        3. 7.4.2.3  ADC Configurability
          1. 7.4.2.3.1 Clock Configuration
          2. 7.4.2.3.2 Resolution
          3. 7.4.2.3.3 Voltage Reference
            1. 7.4.2.3.3.1 Internal ADC Voltage Reference Buffer Control
            2. 7.4.2.3.3.2 ADC External Reference
          4. 7.4.2.3.4 Signal Mode
        4. 7.4.2.4  SOC Principle of Operation
          1. 7.4.2.4.1 SOC Configuration
          2. 7.4.2.4.2 Trigger Operation
          3. 7.4.2.4.3 ADC Triggers
          4. 7.4.2.4.4 ADC Acquisition (Sample and Hold) Window
          5. 7.4.2.4.5 ADC Input Models
          6. 7.4.2.4.6 Channel Selection
        5. 7.4.2.5  ADC Conversion Priority
        6. 7.4.2.6  Burst Mode
          1. 7.4.2.6.1 Burst Mode Example
          2. 7.4.2.6.2 Burst Mode Priority Example
        7. 7.4.2.7  EOC and Interrupt Operation
          1. 7.4.2.7.1 Interrupt Overflow
          2. 7.4.2.7.2 Continue to Interrupt Mode
        8. 7.4.2.8  Post-Processing Blocks
          1. 7.4.2.8.1 PPB Offset Correction
          2. 7.4.2.8.2 PPB Error Calculation
          3. 7.4.2.8.3 PPB Limit Detection and Zero-Crossing Detection
          4. 7.4.2.8.4 PPB Sample Delay Capture
        9. 7.4.2.9  Power-Up Sequence
        10. 7.4.2.10 ADC Timings
          1. 7.4.2.10.1 ADC Timing Diagrams
        11. 7.4.2.11 ADC Programming Guide
        12. 7.4.2.12 Additional Information
          1. 7.4.2.12.1 Ensuring Synchronous Operation
            1. 7.4.2.12.1.1 Basic Synchronous Operation
            2. 7.4.2.12.1.2 Synchronous Operation with Multiple Trigger Sources
            3. 7.4.2.12.1.3 Synchronous Operation with Uneven SOC Numbers
            4. 7.4.2.12.1.4 Non-overlapping Conversions
          2. 7.4.2.12.2 Choosing an Acquisition Window Duration
            1. 7.4.2.12.2.1 Result Register Mapping
            2. 7.4.2.12.2.2 Designing an External Reference Circuit
      3. 7.4.3  Comparator Subsystem (CMPSS)
        1. 7.4.3.1 Introduction
          1. 7.4.3.1.1 Features
          2. 7.4.3.1.2 Comparator
          3. 7.4.3.1.3 Block Diagram
        2. 7.4.3.2 ADC-CMPSS Signal Connections
        3. 7.4.3.3 Reference DAC
        4. 7.4.3.4 Ramp Generator
          1. 7.4.3.4.1 Ramp Generator Overview
          2. 7.4.3.4.2 Ramp Generator Behavior
          3. 7.4.3.4.3 Ramp Generator Behavior at Corner Cases
        5. 7.4.3.5 Digital Filter
          1. 7.4.3.5.1 Filter Initialization Sequence
        6. 7.4.3.6 Using the CMPSS
          1. 7.4.3.6.1 LATCHCLR, EPWMSYNCPER and EPWMBLANK Signals
          2. 7.4.3.6.2 Synchronizer, Digital Filter, and Latch Delays
          3. 7.4.3.6.3 Calibrating the CMPSS Trip Levels
            1. 7.4.3.6.3.1 CMPSS Hysteresis
        7. 7.4.3.7 Enabling and Disabling the CMPSS Clock
        8. 7.4.3.8 CMPSS Programming Guide
      4. 7.4.4  Buffered Digital-to-Analog Converter (DAC)
        1. 7.4.4.1 Introduction
          1. 7.4.4.1.1 Features
          2. 7.4.4.1.2 Block Diagram
        2. 7.4.4.2 Using the DAC
          1. 7.4.4.2.1 Initialization Sequence
          2. 7.4.4.2.2 DAC Offset Adjustment
          3. 7.4.4.2.3 EPWMSYNCPER Signal
        3. 7.4.4.3 Lock Registers
        4. 7.4.4.4 DAC Programming Guide
      5. 7.4.5  Enhanced Pulse Width Modulator (ePWM)
        1. 7.4.5.1  Introduction
          1. 7.4.5.1.1 Submodule Overview
          2. 7.4.5.1.2 EPWM Related Collateral
        2. 7.4.5.2  EPWM Integration
        3. 7.4.5.3  ePWM Modules Overview
        4. 7.4.5.4  Time-Base (TB) Submodule
          1. 7.4.5.4.1 Purpose of the Time-Base Submodule
          2. 7.4.5.4.2 Controlling and Monitoring the Time-Base Submodule
          3. 7.4.5.4.3 Calculating PWM Period and Frequency
            1. 7.4.5.4.3.1 Time-Base Period Shadow Register
            2. 7.4.5.4.3.2 Time-Base Clock Synchronization
            3. 7.4.5.4.3.3 Time-Base Counter Synchronization
            4. 7.4.5.4.3.4 ePWM SYNC Selection
          4. 7.4.5.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
          5. 7.4.5.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
          6. 7.4.5.4.6 Time-Base Counter Modes and Timing Waveforms
          7. 7.4.5.4.7 Edge Detection Within a Programmable TBCTR Range
          8. 7.4.5.4.8 Global Load
            1. 7.4.5.4.8.1 Global Load Pulse Pre-Scalar
            2. 7.4.5.4.8.2 One-Shot Load Mode
            3. 7.4.5.4.8.3 One-Shot Sync Mode
        5. 7.4.5.5  Counter-Compare (CC) Submodule
          1. 7.4.5.5.1 Purpose of the Counter-Compare Submodule
          2. 7.4.5.5.2 Controlling and Monitoring the Counter-Compare Submodule
          3. 7.4.5.5.3 Operational Highlights for the Counter-Compare Submodule
          4. 7.4.5.5.4 Count Mode Timing Waveforms
        6. 7.4.5.6  Action-Qualifier (AQ) Submodule
          1. 7.4.5.6.1 Purpose of the Action-Qualifier Submodule
          2. 7.4.5.6.2 Action-Qualifier Submodule Control and Status Register Definitions
          3. 7.4.5.6.3 Action-Qualifier Event Priority
          4. 7.4.5.6.4 AQCTLA and AQCTLB Shadow Mode Operations
          5. 7.4.5.6.5 Configuration Requirements for Common Waveforms
        7. 7.4.5.7  Dead-Band Generator (DB) Submodule
          1. 7.4.5.7.1 Purpose of the Dead-Band Submodule
          2. 7.4.5.7.2 Dead-band Submodule Additional Operating Modes
          3. 7.4.5.7.3 Simultaneous Writes to DBRED and DBFED Registers Between ePWM Modules (Type 5 EPWM)
          4. 7.4.5.7.4 Operational Highlights for the Dead-Band Submodule
        8. 7.4.5.8  Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
          1. 7.4.5.8.1 Minimum Dead-Band (MINDB)
          2. 7.4.5.8.2 Illegal Combo Logic (ICL)
        9. 7.4.5.9  PWM Chopper (PC) Submodule
          1. 7.4.5.9.1 Purpose of the PWM Chopper Submodule
          2. 7.4.5.9.2 Operational Highlights for the PWM Chopper Submodule
          3. 7.4.5.9.3 Waveforms
            1. 7.4.5.9.3.1 One-Shot Pulse
            2. 7.4.5.9.3.2 Duty Cycle Control
        10. 7.4.5.10 Trip-Zone (TZ) Submodule
          1. 7.4.5.10.1 Purpose of the Trip-Zone Submodule
          2. 7.4.5.10.2 Operational Highlights for the Trip-Zone Submodule
            1. 7.4.5.10.2.1 Trip-Zone Configurations
          3. 7.4.5.10.3 Generating Trip Event Interrupts
        11. 7.4.5.11 Diode Emulation (DE) Submodule
          1. 7.4.5.11.1 DEACTIVE Mode
          2. 7.4.5.11.2 Exiting DE Mode
          3. 7.4.5.11.3 Re-Entering DE Mode
          4. 7.4.5.11.4 DE Monitor
        12. 7.4.5.12 Event-Trigger (ET) Submodule
          1. 7.4.5.12.1 Operational Overview of the ePWM Event-Trigger Submodule
        13. 7.4.5.13 Digital Compare (DC) Submodule
          1. 7.4.5.13.1 Purpose of the Digital Compare Submodule
          2. 7.4.5.13.2 Enhanced Trip Action Using CMPSS
          3. 7.4.5.13.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
          4. 7.4.5.13.4 Operation Highlights of the Digital Compare Submodule
            1. 7.4.5.13.4.1 Digital Compare Events
            2. 7.4.5.13.4.2 Valley Switching
            3. 7.4.5.13.4.3 Event Filtering
            4. 7.4.5.13.4.4 Event Detection
              1. 7.4.5.13.4.4.1 Input Signal Detection
              2. 7.4.5.13.4.4.2 MIN and MAX Detection Circuit
        14. 7.4.5.14 XCMP Submodule
          1. 7.4.5.14.1 XCMP Complex Waveform Generator Mode
          2. 7.4.5.14.2 MIN-MAX Event Logic
          3. 7.4.5.14.3 XCMP Shadow Buffers
          4. 7.4.5.14.4 XCMP Allocation to CMPA and CMPB
          5. 7.4.5.14.5 XCMP Operation
        15. 7.4.5.15 High-Resolution Pulse Width Modulator (HRPWM)
          1. 7.4.5.15.1 Operational Description of HRPWM
            1. 7.4.5.15.1.1 Controlling the HRPWM Capabilities
            2. 7.4.5.15.1.2 HRPWM Source Clock
            3. 7.4.5.15.1.3 Configuring the HRPWM
            4. 7.4.5.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
            5. 7.4.5.15.1.5 Principle of Operation
              1. 7.4.5.15.1.5.1 Edge Positioning
              2. 7.4.5.15.1.5.2 Scaling Considerations
              3. 7.4.5.15.1.5.3 Duty Cycle Range Limitation
              4. 7.4.5.15.1.5.4 High-Resolution Period
                1. 7.4.5.15.1.5.4.1 High-Resolution Period Configuration
            6. 7.4.5.15.1.6 Deadband High-Resolution Operation
            7. 7.4.5.15.1.7 Scale Factor Optimizing Software (SFO)
        16. 7.4.5.16 ePWM Crossbar (XBAR)
        17. 7.4.5.17 Register Lock Protection
        18. 7.4.5.18 Applications to Power Topologies
          1. 7.4.5.18.1  Overview of Multiple Modules
          2. 7.4.5.18.2  Key Configuration Capabilities
          3. 7.4.5.18.3  Controlling Multiple Buck Converters With Independent Frequencies
          4. 7.4.5.18.4  Controlling Multiple Buck Converters With Same Frequencies
          5. 7.4.5.18.5  Controlling Multiple Half H-Bridge (HHB) Converters
          6. 7.4.5.18.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
          7. 7.4.5.18.7  Practical Applications Using Phase Control Between PWM Modules
          8. 7.4.5.18.8  Controlling a 3-Phase Interleaved DC/DC Converter
          9. 7.4.5.18.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
          10. 7.4.5.18.10 Controlling a Peak Current Mode Controlled Buck Module
          11. 7.4.5.18.11 Controlling H-Bridge LLC Resonant Converter
        19. 7.4.5.19 EPWM Programming Guide
      6. 7.4.6  Enhanced Capture (eCAP)
        1. 7.4.6.1  Introduction
          1. 7.4.6.1.1 Features
        2. 7.4.6.2  eCAP Integration
          1. 7.4.6.2.1 eCAP Input Selection
        3. 7.4.6.3  Description
        4. 7.4.6.4  Capture Mode Operation
          1. 7.4.6.4.1 Event Prescaler
          2. 7.4.6.4.2 Glitch Filter
          3. 7.4.6.4.3 Input Capture Signal Selection
          4. 7.4.6.4.4 Modulo 4 Counter
          5. 7.4.6.4.5 Edge Polarity Select and Qualifier
          6. 7.4.6.4.6 Continuous/One-Shot Control
          7. 7.4.6.4.7 32-Bit Counter and Phase Control
          8. 7.4.6.4.8 CAP1-CAP4 Registers
        5. 7.4.6.5  APWM Mode Operation
        6. 7.4.6.6  eCAP Synchronization and Events
          1. 7.4.6.6.1 eCAP Synchronization
            1. 7.4.6.6.1.1 Example 1 - Using SWSYNC with ECAP Module
          2. 7.4.6.6.2 Interrupt Control
          3. 7.4.6.6.3 DMA Interrupt
          4. 7.4.6.6.4 ADC SOC Event
          5. 7.4.6.6.5 Shadow Load and Lockout Control
        7. 7.4.6.7  Signal Monitoring Unit
          1. 7.4.6.7.1 Pulse Width and Period Monitoring
          2. 7.4.6.7.2 Edge Monitoring
          3. 7.4.6.7.3 Error Events
          4. 7.4.6.7.4 Disabling the Signal Monitoring Unit
          5. 7.4.6.7.5 Shadow Control
          6. 7.4.6.7.6 Trip Signal
        8. 7.4.6.8  Application of the eCAP Module
          1. 7.4.6.8.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
          2. 7.4.6.8.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
          3. 7.4.6.8.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
          4. 7.4.6.8.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
        9. 7.4.6.9  Application of the APWM Mode
          1. 7.4.6.9.1 Example 1 - Simple PWM Generation (Independent Channels)
        10. 7.4.6.10 eCAP Programming Guide
      7. 7.4.7  Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.4.7.1  Introduction
        2. 7.4.7.2  Configuring Device Pins
        3. 7.4.7.3  EQEP Integration
        4. 7.4.7.4  Description
          1. 7.4.7.4.1 EQEP Inputs
          2. 7.4.7.4.2 Functional Description
          3. 7.4.7.4.3 eQEP Memory Map
        5. 7.4.7.5  Quadrature Decoder Unit (QDU)
          1. 7.4.7.5.1 Position Counter Input Modes
            1. 7.4.7.5.1.1 Quadrature Count Mode
            2. 7.4.7.5.1.2 Direction-Count Mode
            3. 7.4.7.5.1.3 Up-Count Mode
            4. 7.4.7.5.1.4 Down-Count Mode
          2. 7.4.7.5.2 eQEP Input Polarity Selection
          3. 7.4.7.5.3 Position-Compare Sync Output
        6. 7.4.7.6  Position Counter and Control Unit (PCCU)
          1. 7.4.7.6.1 Position Counter Operating Modes
            1. 7.4.7.6.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
            2. 7.4.7.6.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
            3. 7.4.7.6.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
            4. 7.4.7.6.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
          2. 7.4.7.6.2 Position Counter Latch
            1. 7.4.7.6.2.1 Index Event Latch
            2. 7.4.7.6.2.2 Strobe Event Latch
          3. 7.4.7.6.3 Position Counter Initialization
          4. 7.4.7.6.4 eQEP Position-compare Unit
        7. 7.4.7.7  eQEP Edge Capture Unit
        8. 7.4.7.8  eQEP Watchdog
        9. 7.4.7.9  eQEP Unit Timer Base
        10. 7.4.7.10 eQEP Interrupt Structure
        11. 7.4.7.11 EQEP Programming Guide
      8. 7.4.8  Fast Serial Interface (FSI)
        1. 7.4.8.1 Introduction
          1. 7.4.8.1.1 FSI Features
          2. 7.4.8.1.2 Block Diagram
        2. 7.4.8.2 System-level Integration
          1. 7.4.8.2.1 Signal Description
            1. 7.4.8.2.1.1 Configuring Device Pins
          2. 7.4.8.2.2 FSI Interrupts
            1. 7.4.8.2.2.1 Transmitter Interrupts
            2. 7.4.8.2.2.2 Receiver Interrupts
            3. 7.4.8.2.2.3 Configuring Interrupts
            4. 7.4.8.2.2.4 Handling Interrupts
          3. 7.4.8.2.3 DMA Interface
          4. 7.4.8.2.4 External Frame Trigger Mux
        3. 7.4.8.3 FSI Functional Description
          1. 7.4.8.3.1  FSI Functional Description
          2. 7.4.8.3.2  FSI Transmitter Module
            1. 7.4.8.3.2.1 Initialization
            2. 7.4.8.3.2.2 FSI_TX Clocking
            3. 7.4.8.3.2.3 Transmitting Frames
              1. 7.4.8.3.2.3.1 Software Triggered Frames
              2. 7.4.8.3.2.3.2 Externally Triggered Frames
              3. 7.4.8.3.2.3.3 Ping Frame Generation
                1. 7.4.8.3.2.3.3.1 Automatic Ping Frames
                2. 7.4.8.3.2.3.3.2 Software Triggered Ping Frame
                3. 7.4.8.3.2.3.3.3 Externally Triggered Ping Frame
              4. 7.4.8.3.2.3.4 Transmitting Frames with DMA
            4. 7.4.8.3.2.4 Delay Line Control
            5. 7.4.8.3.2.5 Transmit Buffer Management
            6. 7.4.8.3.2.6 CRC Submodule
            7. 7.4.8.3.2.7 Conditions in Which the Transmitter Must Undergo a Soft Reset
            8. 7.4.8.3.2.8 Reset
          3. 7.4.8.3.3  FSI Receiver Module
            1. 7.4.8.3.3.1  Initialization
            2. 7.4.8.3.3.2  FSI_RX Clocking
            3. 7.4.8.3.3.3  Receiving Frames
              1. 7.4.8.3.3.3.1 Receiving Frames with DMA
            4. 7.4.8.3.3.4  Ping Frame Watchdog
            5. 7.4.8.3.3.5  Frame Watchdog
            6. 7.4.8.3.3.6  Delay Line Control
            7. 7.4.8.3.3.7  Buffer Management
            8. 7.4.8.3.3.8  CRC Submodule
            9. 7.4.8.3.3.9  Using the Zero Bits of the Receiver Tag Registers
            10. 7.4.8.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
            11. 7.4.8.3.3.11 FSI_RX Reset
          4. 7.4.8.3.4  Frame Format
            1. 7.4.8.3.4.1 FSI Frame Phases
            2. 7.4.8.3.4.2 Frame Types
              1. 7.4.8.3.4.2.1 Ping Frames
              2. 7.4.8.3.4.2.2 Error Frames
              3. 7.4.8.3.4.2.3 Data Frames
            3. 7.4.8.3.4.3 Multi-Lane Transmission
          5. 7.4.8.3.5  Flush Sequence
          6. 7.4.8.3.6  Internal Loopback
          7. 7.4.8.3.7  CRC Generation
          8. 7.4.8.3.8  ECC Module
          9. 7.4.8.3.9  FSI Trigger Generation
          10. 7.4.8.3.10 FSI-SPI Compatibility Mode
            1. 7.4.8.3.10.1 Available SPI Modes
              1. 7.4.8.3.10.1.1 FSITX as SPI Controller, Transmit Only
                1. 7.4.8.3.10.1.1.1 Initialization
                2. 7.4.8.3.10.1.1.2 Operation
              2. 7.4.8.3.10.1.2 FSIRX as SPI Peripheral, Receive Only
                1. 7.4.8.3.10.1.2.1 Initialization
                2. 7.4.8.3.10.1.2.2 Operation
              3. 7.4.8.3.10.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
                1. 7.4.8.3.10.1.3.1 Initialization
                2. 7.4.8.3.10.1.3.2 Operation
        4. 7.4.8.4 FSI Programing Guide
          1. 7.4.8.4.1 Establishing the Communication Link
            1. 7.4.8.4.1.1 Establishing the Communication Link from the Main Device
            2. 7.4.8.4.1.2 Establishing the Communication Link from the Remote Device
          2. 7.4.8.4.2 Register Protection
          3. 7.4.8.4.3 Emulation Mode
      9. 7.4.9  Sigma Delta Filter Module (SDFM)
        1. 7.4.9.1  Introduction
          1. 7.4.9.1.1 Features
          2. 7.4.9.1.2 Block Diagram
        2. 7.4.9.2  SDFM Integration
        3. 7.4.9.3  Configuring Device Pins
        4. 7.4.9.4  Input Qualification
        5. 7.4.9.5  Input Control Unit
        6. 7.4.9.6  SDFM Clock Control
        7. 7.4.9.7  Sinc Filter
          1. 7.4.9.7.1 Data Rate and Latency of the Sinc Filter
        8. 7.4.9.8  Data (Primary) Filter Unit
          1. 7.4.9.8.1 32-bit or 16-bit Data Filter Output Representation
          2. 7.4.9.8.2 Data FIFO
          3. 7.4.9.8.3 SDSYNC Event
        9. 7.4.9.9  Comparator (Secondary) Filter Unit
          1. 7.4.9.9.1 Higher Threshold (HLT) Comparators
          2. 7.4.9.9.2 Lower Threshold (LLT) Comparators
          3. 7.4.9.9.3 Digital Filter
        10. 7.4.9.10 Theoretical SDFM Filter Output
        11. 7.4.9.11 Interrupt Unit
          1. 7.4.9.11.1 SDFM (SDy_ERR) Interrupt Sources
          2. 7.4.9.11.2 Data Ready (DRINT) Interrupt Sources
        12. 7.4.9.12 SDFM Programming Guide
      10. 7.4.10 Crossbar (XBAR)
        1. 7.4.10.1 INPUTXBAR
        2. 7.4.10.2 PWMXBAR
        3. 7.4.10.3 MDLXBAR
        4. 7.4.10.4 ICLXBAR
        5. 7.4.10.5 INTXBAR
        6. 7.4.10.6 DMAXBAR
        7. 7.4.10.7 OUTPUTXBAR
          1. 7.4.10.7.1 OUTPUTXBAR Input Connection Table
        8. 7.4.10.8 PWMSYNCOUTXBAR
        9. 7.4.10.9 XBAR Programming Guide
  10. 8 Interprocessor Communication (IPC)
    1. 8.1 Mailbox
      1. 8.1.1 Mailbox
      2. 8.1.2 Maibox Message Scheme
      3. 8.1.3 Maibox Message Example
      4. 8.1.4 Maibox Registers
        1. 8.1.4.1 R5SS0_CORE0 Mailbox Registers
        2. 8.1.4.2 R5SS0_CORE1 Mailbox Registers
        3. 8.1.4.3 R5SS1_CORE0 Mailbox Registers
        4. 8.1.4.4 R5SS1_CORE1 Mailbox Registers
        5. 8.1.4.5 ICSSM_PRU0 Mailbox Registers
        6. 8.1.4.6 ICSSM_PRU1 Mailbox Registers
        7. 8.1.4.7 HSM Mailbox Registers
    2. 8.2 Spinlock
      1. 8.2.1 Spinlock Overview
        1. 8.2.1.1 Spinlock Not Supported Features
      2. 8.2.2 Spinlock Integration
        1.       Spinlock Integration
      3. 8.2.3 Spinlock Functional Description
        1. 8.2.3.1 Spinlock Software Reset
        2. 8.2.3.2 About Spinlocks
        3. 8.2.3.3 Spinlock Functional Operation
      4. 8.2.4 Spinlock Programming Guide
        1. 8.2.4.1 Spinlock Low-level Programming Models
          1. 8.2.4.1.1 Basic Spinlock Operations
            1. 8.2.4.1.1.1 Spinlocks Clearing After a System Bug Recovery
            2. 8.2.4.1.1.2 Take and Release Spinlock
  11. 9 Memory Controllers
    1. 9.1 Memory Controllers Overview
  12. 10Interrupts
    1. 10.1 Interrupt Architecture
    2. 10.2 Interrupt Controllers
      1. 10.2.1 Vectored Interrupt Manager (VIM)
        1. 10.2.1.1 VIM Overview
        2. 10.2.1.2 VIM Interrupt Inputs
        3. 10.2.1.3 VIM Interrupt Outputs
        4. 10.2.1.4 VIM Interrupt Vector Table (VIM RAM)
        5. 10.2.1.5 VIM Interrupt Prioritization
        6. 10.2.1.6 VIM ECC Support
        7. 10.2.1.7 VIM IDLE State
        8. 10.2.1.8 VIM Interrupt Handling
          1. 10.2.1.8.1 Servicing IRQ Through Vector Interface
          2. 10.2.1.8.2 Servicing IRQ Through MMR Interface
          3. 10.2.1.8.3 Servicing IRQ Through MMR Interface (Alternative)
          4. 10.2.1.8.4 Servicing FIQ
          5. 10.2.1.8.5 Servicing FIQ (Alternative)
      2. 10.2.2 Other Interrupt Controllers
    3. 10.3 Interrupt Routers
      1. 10.3.1 INTRTR Overview
      2. 10.3.2 INTRTR Integration
        1. 10.3.2.1 PRU-ICSS XBAR INTRTR0
        2. 10.3.2.2 EDMA XBAR INTRTR0
        3. 10.3.2.3 GPIO XBAR INTRTR0
    4. 10.4 Interrupt Sources
      1. 10.4.1 R5FSS0_CORE0 Interrupt Map
      2. 10.4.2 R5FSS0_CORE1 Interrupt Map
      3. 10.4.3 R5FSS1_CORE0 Interrupt Map
      4. 10.4.4 R5FSS1_CORE1 Interrupt Map
      5. 10.4.5 PRU-ICSS Interrupt Map
      6. 10.4.6 ESM0 Interrupt Map
  13. 11Data Movement Architecture
    1. 11.1 Overview
    2. 11.2 Definition of Terms
    3. 11.3 Enhanced Direct Memory Access (EDMA)
      1. 11.3.1 EDMA Module Overview
        1. 11.3.1.1 EDMA Features
      2. 11.3.2 EDMA Integration
        1. 11.3.2.1 EDMA Integration
        2. 11.3.2.2 EDMA Interrupt Aggregator
        3. 11.3.2.3 EDMA Error Interrupt Aggregator
        4. 11.3.2.4 EDMA Configuration
      3. 11.3.3 EDMA Controller Functional Description
        1. 11.3.3.1  Block Diagram
          1. 11.3.3.1.1 Third-Party Channel Controller
          2. 11.3.3.1.2 Third-Party Transfer Controller
        2. 11.3.3.2  Types of EDMA Controller Transfers
          1. 11.3.3.2.1 A-Synchronized Transfers
          2. 11.3.3.2.2 AB-Synchronized Transfers
        3. 11.3.3.3  Parameter RAM (PaRAM)
          1. 11.3.3.3.1 PaRAM
          2. 11.3.3.3.2 EDMA Channel PaRAM Set Entry Fields
            1. 11.3.3.3.2.1  Channel Options Parameter (OPT)
            2. 11.3.3.3.2.2  Channel Source Address (SRC)
            3. 11.3.3.3.2.3  Channel Destination Address (DST)
            4. 11.3.3.3.2.4  Count for 1st Dimension (ACNT)
            5. 11.3.3.3.2.5  Count for 2nd Dimension (BCNT)
            6. 11.3.3.3.2.6  Count for 3rd Dimension (CCNT)
            7. 11.3.3.3.2.7  BCNT Reload (BCNTRLD)
            8. 11.3.3.3.2.8  Source B Index (SBIDX)
            9. 11.3.3.3.2.9  Destination B Index (DBIDX)
            10. 11.3.3.3.2.10 Source C Index (SCIDX)
            11. 11.3.3.3.2.11 Destination C Index (DCIDX)
            12. 11.3.3.3.2.12 Link Address (LINK)
          3. 11.3.3.3.3 Null PaRAM Set
          4. 11.3.3.3.4 Dummy PaRAM Set
          5. 11.3.3.3.5 Dummy Versus Null Transfer Comparison
          6. 11.3.3.3.6 Parameter Set Updates
          7. 11.3.3.3.7 Linking Transfers
          8. 11.3.3.3.8 Constant Addressing Mode Transfers/Alignment Issues
          9. 11.3.3.3.9 Element Size
        4. 11.3.3.4  Initiating a DMA Transfer
          1. 11.3.3.4.1 DMA Channels
            1. 11.3.3.4.1.1 Event-Triggered Transfer Request
            2. 11.3.3.4.1.2 Manually-Triggered Transfer Request
            3. 11.3.3.4.1.3 Chain-Triggered Transfer Request
          2. 11.3.3.4.2 QDMA Channels
            1. 11.3.3.4.2.1 Auto-Triggered and Link-Triggered Transfer Request
          3. 11.3.3.4.3 Comparison Between DMA and QDMA Channels
        5. 11.3.3.5  Completion of a DMA Transfer
          1. 11.3.3.5.1 Normal Completion
          2. 11.3.3.5.2 Early Completion
          3. 11.3.3.5.3 Dummy or Null Completion
        6. 11.3.3.6  Event, Channel, and PaRAM Mapping
          1. 11.3.3.6.1 DMA Channel to PaRAM Mapping
          2. 11.3.3.6.2 QDMA Channel to PaRAM Mapping
        7. 11.3.3.7  EDMA Channel Controller Regions
          1. 11.3.3.7.1 Region Overview
          2. 11.3.3.7.2 Channel Controller Regions
            1. 11.3.3.7.2.1 Resource Pool Division Across Two Regions
          3. 11.3.3.7.3 Region Interrupts
        8. 11.3.3.8  Chaining EDMA Channels
        9. 11.3.3.9  EDMA Interrupts
          1. 11.3.3.9.1 Transfer Completion Interrupts
            1. 11.3.3.9.1.1 Enabling Transfer Completion Interrupts
            2. 11.3.3.9.1.2 Clearing Transfer Completion Interrupts
          2. 11.3.3.9.2 EDMA Interrupt Servicing
          3. 11.3.3.9.3 Interrupt Servicing
          4. 11.3.3.9.4 1202
          5. 11.3.3.9.5 Interrupt Servicing
          6. 11.3.3.9.6 Interrupt Evaluation Operations
          7. 11.3.3.9.7 Error Interrupts
        10. 11.3.3.10 Memory Protection
          1. 11.3.3.10.1 Active Memory Protection
          2. 11.3.3.10.2 Proxy Memory Protection
        11. 11.3.3.11 Event Queue(s)
          1. 11.3.3.11.1 DMA/QDMA Channel to Event Queue Mapping
          2. 11.3.3.11.2 Queue RAM Debug Visibility
          3. 11.3.3.11.3 Queue Resource Tracking
          4. 11.3.3.11.4 Performance Considerations
        12. 11.3.3.12 EDMA Transfer Controller (EDMA_TPTC)
          1. 11.3.3.12.1 Architecture Details
            1. 11.3.3.12.1.1 Command Fragmentation
            2. 11.3.3.12.1.2 TR Pipelining
            3. 11.3.3.12.1.3 Command Fragmentation (DBS = 64)
            4. 11.3.3.12.1.4 Performance Tuning
          2. 11.3.3.12.2 Memory Protection
          3. 11.3.3.12.3 Error Generation
          4. 11.3.3.12.4 Debug Features
            1. 11.3.3.12.4.1 Destination FIFO Register Pointer
        13. 11.3.3.13 Event Dataflow
        14. 11.3.3.14 EDMA Controller Prioritization
          1. 11.3.3.14.1 Channel Priority
          2. 11.3.3.14.2 Trigger Source Priority
          3. 11.3.3.14.3 Dequeue Priority
        15. 11.3.3.15 Emulation Considerations
      4. 11.3.4 EDMA Transfer Examples
        1. 11.3.4.1 Block Move Example
        2. 11.3.4.2 Subframe Extraction Example
        3. 11.3.4.3 Data Sorting Example
        4. 11.3.4.4 Setting Up an EDMA Transfer
      5. 11.3.5 EDMA Debug Checklist and Programming Tips
        1. 11.3.5.1 EDMA Debug Checklist
        2. 11.3.5.2 EDMA Programming Tips
      6. 11.3.6 EDMA Event Map
  14. 12Time Sync
    1. 12.1 Time Sync Architecture
      1. 12.1.1 Time Sync Architecture Overview
    2. 12.2 Time Sync Routers
      1. 12.2.1 Time Sync Routers Overview
        1. 12.2.1.1 SOC_TIMESYNC_XBAR0 Overview
        2. 12.2.1.2 SOC_TIMESYNC_XBAR1 Overview
      2. 12.2.2 Time Sync Routers Integration
        1. 12.2.2.1 SOC_TIMESYNC_XBAR0 Integration
        2. 12.2.2.2 SOC_TIMESYNC_XBAR1 Integration
      3. 12.2.3 Time Sync Routers Registers
        1. 12.2.3.1 SOC_TIMESYNC_XBAR0 Registers
        2. 12.2.3.2 SOC_TIMESYNC_XBAR1 Registers
    3. 12.3 Time Sync and Compare Events
      1. 12.3.1 TimeSync Event Sources
        1. 12.3.1.1 SOC_TIMESYNC_XBAR0 Event Map
        2. 12.3.1.2 SOC_TIMESYNC_XBAR1 Event Map
        3. 12.3.1.3 PRU-ICSS Event Map
        4. 12.3.1.4 CPSW0_CPTS Event Map
  15. 13Peripherals
    1. 13.1 General Connectivity Peripherals
      1. 13.1.1 General-Purpose Interface (GPIO)
        1. 13.1.1.1 GPIO Overview
        2. 13.1.1.2 GPIO Environment
        3. 13.1.1.3 GPIO Integration
        4. 13.1.1.4 GPIO Functional Description
          1. 13.1.1.4.1 GPIO Block Diagram
          2. 13.1.1.4.2 GPIO Function
          3. 13.1.1.4.3 GPIO Interrupt and Event Generation
            1. 13.1.1.4.3.1 Interrupt Enable (per Bank)
            2. 13.1.1.4.3.2 Trigger Configuration (per Bit)
            3. 13.1.1.4.3.3 Interrupt Status and Clear (per Bit)
          4. 13.1.1.4.4 Input Qualification
            1. 13.1.1.4.4.1 No Synchronization (Asynchronous Input)
            2. 13.1.1.4.4.2 Synchronization to SYSCLK Only
            3. 13.1.1.4.4.3 Qualification Using a Sampling Window
          5. 13.1.1.4.5 GPIO Interrupt Connectivity
          6. 13.1.1.4.6 GPIO Emulation Halt Operation
      2. 13.1.2 Inter-Integrated Circuit (I2C) Interface
        1. 13.1.2.1 I2C Overview
          1. 13.1.2.1.1 I2C Features
          2. 13.1.2.1.2 I2C Not Supported Features
        2. 13.1.2.2 I2C Environment
          1. 13.1.2.2.1 I2C Typical Application
            1. 13.1.2.2.1.1 I2C Interface Typical Connections
            2. 13.1.2.2.1.2 1284
          2. 13.1.2.2.2 I2C Typical Connection Protocol and Data Format
            1. 13.1.2.2.2.1  I2C Serial Data Formats
            2. 13.1.2.2.2.2  I2C Data Validity
            3. 13.1.2.2.2.3  I2C Start and Stop Conditions
            4. 13.1.2.2.2.4  I2C Addressing
              1. 13.1.2.2.2.4.1 7-Bit Addressing Format
              2. 13.1.2.2.2.4.2 10-Bit Addressing Format
              3. 13.1.2.2.2.4.3 Using the Repeated START Condition
              4. 13.1.2.2.2.4.4 Free Data Format
            5. 13.1.2.2.2.5  I2C Controller Transmitter
            6. 13.1.2.2.2.6  I2C Controller Receiver
            7. 13.1.2.2.2.7  I2C Target Transmitter
            8. 13.1.2.2.2.8  I2C Target Receiver
            9. 13.1.2.2.2.9  I2C Bus Arbitration
            10. 13.1.2.2.2.10 I2C Clock Generation and Synchronization
        3. 13.1.2.3 I2C Integration
        4. 13.1.2.4 I2C Functional Description
          1. 13.1.2.4.1 I2C Block Diagram
          2. 13.1.2.4.2 I2C Clocks
            1. 13.1.2.4.2.1 I2C Clocking
          3. 13.1.2.4.3 I2C Software Reset
          4. 13.1.2.4.4 I2C Interrupt Requests
          5. 13.1.2.4.5 I2C Noise Filter
        5. 13.1.2.5 I2C Programming Guide
          1. 13.1.2.5.1 I2C Low-Level Programming Models
            1. 13.1.2.5.1.1 I2C Programming Model
              1. 13.1.2.5.1.1.1 Main Program
                1. 13.1.2.5.1.1.1.1 Module State after Reset
                2. 13.1.2.5.1.1.1.2 Initialization Procedure
                3. 13.1.2.5.1.1.1.3 Section
                4. 13.1.2.5.1.1.1.4 Configure Address Registers
                5. 13.1.2.5.1.1.1.5 Initiate a Transfer
                6. 13.1.2.5.1.1.1.6 Receive Data
                7. 13.1.2.5.1.1.1.7 Transmit Data
              2. 13.1.2.5.1.1.2 Interrupt Subroutine Sequence
      3. 13.1.3 Multichannel Serial Peripheral Interface (MCSPI)
        1. 13.1.3.1 MCSPI Overview
          1. 13.1.3.1.1 SPI Features
          2. 13.1.3.1.2 SPI Not Supported Features
        2. 13.1.3.2 SPI Environment
          1. 13.1.3.2.1 MCSPI Protocol and Data Format
            1. 13.1.3.2.1.1 Transfer Format
          2. 13.1.3.2.2 MCSPI in Controller Mode
          3. 13.1.3.2.3 MCSPI in Peripheral Mode
        3. 13.1.3.3 SPI Integration
        4. 13.1.3.4 MCSPI Functional Description
          1. 13.1.3.4.1 SPI Block Diagram
          2. 13.1.3.4.2 MCSPI Reset
          3. 13.1.3.4.3 MCSPI Controller Mode
            1. 13.1.3.4.3.1 Controller Mode Features
            2. 13.1.3.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 13.1.3.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 13.1.3.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 13.1.3.4.3.5 Single-Channel Controller Mode
              1. 13.1.3.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 13.1.3.4.3.5.2 Force SPIEN[i] Mode
              3. 13.1.3.4.3.5.3 Turbo Mode
            6. 13.1.3.4.3.6 Start-Bit Mode
            7. 13.1.3.4.3.7 Chip-Select Timing Control
            8. 13.1.3.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 13.1.3.4.3.8.1 Clock Ratio Granularity
          4. 13.1.3.4.4 MCSPI Peripheral Mode
            1. 13.1.3.4.4.1 Dedicated Resources
            2. 13.1.3.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 13.1.3.4.4.3 Peripheral Transmit-Only Mode
            4. 13.1.3.4.4.4 Peripheral Receive-Only Mode
          5. 13.1.3.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 13.1.3.4.6 MCSPI FIFO Buffer Management
            1. 13.1.3.4.6.1 Buffer Almost Full
            2. 13.1.3.4.6.2 Buffer Almost Empty
            3. 13.1.3.4.6.3 End of Transfer Management
            4. 13.1.3.4.6.4 Multiple MCSPI Word Access
            5. 13.1.3.4.6.5 First MCSPI Word Delay
          7. 13.1.3.4.7 MCSPI Interrupts
            1. 13.1.3.4.7.1 Interrupt Events in Controller Mode
              1. 13.1.3.4.7.1.1 TXx_EMPTY
              2. 13.1.3.4.7.1.2 TXx_UNDERFLOW
              3. 13.1.3.4.7.1.3 RXx_ FULL
              4. 13.1.3.4.7.1.4 End Of Word Count
            2. 13.1.3.4.7.2 Interrupt Events in Peripheral Mode
              1. 13.1.3.4.7.2.1 TXx_EMPTY
              2. 13.1.3.4.7.2.2 TXx_UNDERFLOW
              3. 13.1.3.4.7.2.3 RXx_FULL
              4. 13.1.3.4.7.2.4 RX0_OVERFLOW
              5. 13.1.3.4.7.2.5 End Of Word Count
            3. 13.1.3.4.7.3 Interrupt-Driven Operation
            4. 13.1.3.4.7.4 Polling
          8. 13.1.3.4.8 MCSPI DMA Requests
        5. 13.1.3.5 MCSPI Programming Guide
          1. 13.1.3.5.1 MCSPI Global Initialization
            1. 13.1.3.5.1.1 MCSPI Global Initialization
              1. 13.1.3.5.1.1.1 Main Sequence – MCSPI Global Initialization
          2. 13.1.3.5.2 MCSPI Operational Mode Configuration
            1. 13.1.3.5.2.1 MCSPI Operational Modes
              1. 13.1.3.5.2.1.1 Common Transfer Sequence
              2. 13.1.3.5.2.1.2 End of Transfer Sequences
              3. 13.1.3.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 13.1.3.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 13.1.3.5.2.1.4.1 Based on Interrupt Requests
                2. 13.1.3.5.2.1.4.2 Based on DMA Write Requests
              5. 13.1.3.5.2.1.5 Controller Normal Receive-Only
                1. 13.1.3.5.2.1.5.1 Based on Interrupt Requests
                2. 13.1.3.5.2.1.5.2 Based on DMA Read Requests
              6. 13.1.3.5.2.1.6 Controller Turbo Receive-Only
                1. 13.1.3.5.2.1.6.1 Based on Interrupt Requests
                2. 13.1.3.5.2.1.6.2 Based on DMA Read Requests
              7. 13.1.3.5.2.1.7 Peripheral Receive-Only
              8. 13.1.3.5.2.1.8 Transfer Procedures With FIFO
                1. 13.1.3.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 13.1.3.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 13.1.3.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 13.1.3.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 13.1.3.5.2.1.8.5 Transmit-Only
                6. 13.1.3.5.2.1.8.6 Receive-Only With Word Count
                7. 13.1.3.5.2.1.8.7 Receive-Only Without Word Count
              9. 13.1.3.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 13.1.3.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 13.1.3.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 13.1.3.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 13.1.3.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
          3. 13.1.3.5.3 Common Transfer Procedures Without FIFO – Polling Method
            1. 13.1.3.5.3.1 Receive-Only Procedure – Polling Method
            2. 13.1.3.5.3.2 Receive-Only Procedure – Interrupt Method
            3. 13.1.3.5.3.3 Transmit-Only Procedure – Polling Method
            4. 13.1.3.5.3.4 Transmit-and-Receive Procedure – Polling Method
      4. 13.1.4 Universal Asynchronous Receiver/Transmitter (UART)
        1. 13.1.4.1 UART Overview
          1. 13.1.4.1.1 UART Features
          2. 13.1.4.1.2 IrDA Features
          3. 13.1.4.1.3 CIR Features
          4. 13.1.4.1.4 ISO 7816 (Smartcard) Functions
        2. 13.1.4.2 UART Environment
          1. 13.1.4.2.1 UART Functional Interfaces
            1. 13.1.4.2.1.1 System Using UART Communication With Hardware Handshake
            2. 13.1.4.2.1.2 UART Interface Description
            3. 13.1.4.2.1.3 UART Protocol and Data Format
          2. 13.1.4.2.2 RS-485 Functional Interfaces
            1. 13.1.4.2.2.1 System Using RS-485 Communication
            2. 13.1.4.2.2.2 RS-485 Interface Description
          3. 13.1.4.2.3 IrDA Functional Interfaces
            1. 13.1.4.2.3.1 System Using IrDA Communication Protocol
            2. 13.1.4.2.3.2 IrDA Interface Description
            3. 13.1.4.2.3.3 IrDA Protocol and Data Format
              1. 13.1.4.2.3.3.1 SIR Mode
                1. 13.1.4.2.3.3.1.1 Frame Format
                2. 13.1.4.2.3.3.1.2 Asynchronous Transparency
                3. 13.1.4.2.3.3.1.3 Abort Sequence
                4. 13.1.4.2.3.3.1.4 Pulse Shaping
                5. 13.1.4.2.3.3.1.5 Encoder
                6. 13.1.4.2.3.3.1.6 Decoder
                7. 13.1.4.2.3.3.1.7 IR Address Checking
              2. 13.1.4.2.3.3.2 SIR Free-Format Mode
              3. 13.1.4.2.3.3.3 MIR Mode
                1. 13.1.4.2.3.3.3.1 MIR Encoder/Decoder
                2. 13.1.4.2.3.3.3.2 SIP Generation
              4. 13.1.4.2.3.3.4 FIR Mode
          4. 13.1.4.2.4 CIR Functional Interfaces
            1. 13.1.4.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 13.1.4.2.4.2 CIR Interface Description
            3. 13.1.4.2.4.3 CIR Protocol and Data Format
              1. 13.1.4.2.4.3.1 Carrier Modulation
              2. 13.1.4.2.4.3.2 Pulse Duty Cycle
              3. 13.1.4.2.4.3.3 Consumer IR Encoding/Decoding
        3. 13.1.4.3 UART Integration
        4. 13.1.4.4 UART Functional Description
          1. 13.1.4.4.1 UART Block Diagram
          2. 13.1.4.4.2 UART Clock Configuration
          3. 13.1.4.4.3 UART Software Reset
            1. 13.1.4.4.3.1 Independent TX/RX
          4. 13.1.4.4.4 UART Power Management
            1. 13.1.4.4.4.1 UART Mode Power Management
              1. 13.1.4.4.4.1.1 Module Power Saving
              2. 13.1.4.4.4.1.2 System Power Saving
            2. 13.1.4.4.4.2 IrDA Mode Power Management
              1. 13.1.4.4.4.2.1 Module Power Saving
              2. 13.1.4.4.4.2.2 System Power Saving
            3. 13.1.4.4.4.3 CIR Mode Power Management
              1. 13.1.4.4.4.3.1 Module Power Saving
              2. 13.1.4.4.4.3.2 System Power Saving
            4. 13.1.4.4.4.4 Local Power Management
          5. 13.1.4.4.5 UART Interrupt Requests
            1. 13.1.4.4.5.1 UART Mode Interrupt Management
              1. 13.1.4.4.5.1.1 UART Interrupts
              2. 13.1.4.4.5.1.2 Wake-Up Interrupt
            2. 13.1.4.4.5.2 IrDA Mode Interrupt Management
              1. 13.1.4.4.5.2.1 IrDA Interrupts
              2. 13.1.4.4.5.2.2 Wake-Up Interrupts
            3. 13.1.4.4.5.3 CIR Mode Interrupt Management
              1. 13.1.4.4.5.3.1 CIR Interrupts
              2. 13.1.4.4.5.3.2 Wake-Up Interrupts
          6. 13.1.4.4.6 UART FIFO Management
            1. 13.1.4.4.6.1 FIFO Trigger
              1. 13.1.4.4.6.1.1 Transmit FIFO Trigger
              2. 13.1.4.4.6.1.2 Receive FIFO Trigger
            2. 13.1.4.4.6.2 FIFO Interrupt Mode
            3. 13.1.4.4.6.3 FIFO Polled Mode Operation
            4. 13.1.4.4.6.4 FIFO DMA Mode Operation
              1. 13.1.4.4.6.4.1 DMA sequence to disable TX DMA
              2. 13.1.4.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 13.1.4.4.6.4.3 DMA Transmission
              4. 13.1.4.4.6.4.4 DMA Reception
          7. 13.1.4.4.7 UART Mode Selection
            1. 13.1.4.4.7.1 Register Access Modes
              1. 13.1.4.4.7.1.1 Operational Mode and Configuration Modes
              2. 13.1.4.4.7.1.2 Register Access Submode
              3. 13.1.4.4.7.1.3 Registers Available for the Register Access Modes
            2. 13.1.4.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 13.1.4.4.7.2.1 Registers Available for the UART Function
              2. 13.1.4.4.7.2.2 Registers Available for the IrDA Function
              3. 13.1.4.4.7.2.3 Registers Available for the CIR Function
          8. 13.1.4.4.8 UART Protocol Formatting
            1. 13.1.4.4.8.1 UART Mode
              1. 13.1.4.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 13.1.4.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 13.1.4.4.8.1.3 Multi-drop Parity Mode with Address Match
              4. 13.1.4.4.8.1.4 Time-guard
              5. 13.1.4.4.8.1.5 UART Data Formatting
                1. 13.1.4.4.8.1.5.1 Frame Formatting
                2. 13.1.4.4.8.1.5.2 Hardware Flow Control
                3. 13.1.4.4.8.1.5.3 Software Flow Control
                  1. 1.4.4.8.1.5.3.1 Receive (RX)
                  2. 1.4.4.8.1.5.3.2 Transmit (TX)
                4. 13.1.4.4.8.1.5.4 Autobauding Modes
                5. 13.1.4.4.8.1.5.5 Error Detection
                6. 13.1.4.4.8.1.5.6 Overrun During Receive
                7. 13.1.4.4.8.1.5.7 Time-Out and Break Conditions
                  1. 1.4.4.8.1.5.7.1 Time-Out Counter
                  2. 1.4.4.8.1.5.7.2 Break Condition
            2. 13.1.4.4.8.2 RS-485 Mode
              1. 13.1.4.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 13.1.4.4.8.3 IrDA Mode
              1. 13.1.4.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 13.1.4.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 13.1.4.4.8.3.3 IrDA Data Formatting
                1. 13.1.4.4.8.3.3.1 IR RX Polarity Control
                2. 13.1.4.4.8.3.3.2 IrDA Reception Control
                3. 13.1.4.4.8.3.3.3 IR Address Checking
                4. 13.1.4.4.8.3.3.4 Frame Closing
                5. 13.1.4.4.8.3.3.5 Store and Controlled Transmission
                6. 13.1.4.4.8.3.3.6 Error Detection
                7. 13.1.4.4.8.3.3.7 Underrun During Transmission
                8. 13.1.4.4.8.3.3.8 Overrun During Receive
                9. 13.1.4.4.8.3.3.9 Status FIFO
              4. 13.1.4.4.8.3.4 SIR Mode Data Formatting
                1. 13.1.4.4.8.3.4.1 Abort Sequence
                2. 13.1.4.4.8.3.4.2 Pulse Shaping
                3. 13.1.4.4.8.3.4.3 SIR Free Format Programming
              5. 13.1.4.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 13.1.4.4.8.4 CIR Mode
              1. 13.1.4.4.8.4.1 CIR Mode Clock Generation
              2. 13.1.4.4.8.4.2 CIR Data Formatting
                1. 13.1.4.4.8.4.2.1 IR RX Polarity Control
                2. 13.1.4.4.8.4.2.2 CIR Transmission
                3. 13.1.4.4.8.4.2.3 CIR Reception
        5. 13.1.4.5 UART Programming Guide
          1. 13.1.4.5.1 UART Global Initialization
            1. 13.1.4.5.1.1 Surrounding Modules Global Initialization
            2. 13.1.4.5.1.2 UART Module Global Initialization
          2. 13.1.4.5.2 UART Mode selection
          3. 13.1.4.5.3 UART Submode selection
          4. 13.1.4.5.4 UART Load FIFO trigger and DMA mode settings
            1. 13.1.4.5.4.1 DMA mode Settings
            2. 13.1.4.5.4.2 FIFO Trigger Settings
          5. 13.1.4.5.5 UART Protocol, Baud rate and interrupt settings
            1. 13.1.4.5.5.1 Baud rate settings
            2. 13.1.4.5.5.2 Interrupt settings
            3. 13.1.4.5.5.3 Protocol settings
            4. 13.1.4.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 13.1.4.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 13.1.4.5.6 UART Hardware and Software Flow Control Configuration
            1. 13.1.4.5.6.1 Hardware Flow Control Configuration
            2. 13.1.4.5.6.2 Software Flow Control Configuration
          7. 13.1.4.5.7 IrDA Programming Model
            1. 13.1.4.5.7.1 SIR mode
              1. 13.1.4.5.7.1.1 Receive
              2. 13.1.4.5.7.1.2 Transmit
            2. 13.1.4.5.7.2 MIR mode
              1. 13.1.4.5.7.2.1 Receive
              2. 13.1.4.5.7.2.2 Transmit
            3. 13.1.4.5.7.3 FIR mode
              1. 13.1.4.5.7.3.1 Receive
              2. 13.1.4.5.7.3.2 Transmit
    2. 13.2 High-speed Serial Interfaces
      1. 13.2.1 Gigabit Ethernet Switch (CPSW)
        1. 13.2.1.1 CPSW0 Overview
          1. 13.2.1.1.1 CPSW0 Features
          2. 13.2.1.1.2 CPSW0 Not Supported Features
          3. 13.2.1.1.3 CPSW Terminology
        2. 13.2.1.2 CPSW0 Environment
          1. 13.2.1.2.1 CPSW0 MII Interface
          2. 13.2.1.2.2 CPSW0 RMII Interface
          3. 13.2.1.2.3 CPSW0 RGMII Interface
        3. 13.2.1.3 CPSW Integration
        4. 13.2.1.4 CPSW0 Functional Description
          1. 13.2.1.4.1  Functional Block Diagram
          2. 13.2.1.4.2  CPSW Ports
            1. 13.2.1.4.2.1 Interface Mode Selection
          3. 13.2.1.4.3  Clocking
            1. 13.2.1.4.3.1 Subsystem Clocking
            2. 13.2.1.4.3.2 Interface Clocking
              1. 13.2.1.4.3.2.1 RGMII Interface Clocking
              2. 13.2.1.4.3.2.2 RMII Interface Clocking
              3. 13.2.1.4.3.2.3 MDIO Clocking
          4. 13.2.1.4.4  Software IDLE
          5. 13.2.1.4.5  Interrupt Functionality
          6. 13.2.1.4.6  CPSW
            1. 13.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 13.2.1.4.6.1.1  Error Handling
              2. 13.2.1.4.6.1.2  Bypass Operations
              3. 13.2.1.4.6.1.3  OUI Deny or Accept
              4. 13.2.1.4.6.1.4  Statistics Counting
              5. 13.2.1.4.6.1.5  Automotive Security Features
              6. 13.2.1.4.6.1.6  CPSW Switching Solutions
                1. 13.2.1.4.6.1.6.1 Basics of 3-port Switch Type
              7. 13.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 13.2.1.4.6.1.7.1 InterVLAN Routing
                2. 13.2.1.4.6.1.7.2 OAM Operations
              8. 13.2.1.4.6.1.8  Supervisory packets
              9. 13.2.1.4.6.1.9  Address Table Entry
                1. 13.2.1.4.6.1.9.1  Free Table Entry
                2. 13.2.1.4.6.1.9.2  OUI Unicast Address Table Entry
                3. 13.2.1.4.6.1.9.3  Unicast Address Table Entry (Bit 40 == 0)
                4. 13.2.1.4.6.1.9.4  Multicast Address Table Entry (Bit 40==1)
                5. 13.2.1.4.6.1.9.5  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                6. 13.2.1.4.6.1.9.6  VLAN/Multicast Address Table Entry (Bit 40==1)
                7. 13.2.1.4.6.1.9.7  Inner VLAN Table Entry
                8. 13.2.1.4.6.1.9.8  Outer VLAN Table Entry
                9. 13.2.1.4.6.1.9.9  EtherType Table Entry
                10. 13.2.1.4.6.1.9.10 IPv4 Table Entry
                11. 13.2.1.4.6.1.9.11 IPv6 Table Entry High
                12. 13.2.1.4.6.1.9.12 IPv6 Table Entry Low
              10. 13.2.1.4.6.1.10 Multicast Address
                1. 13.2.1.4.6.1.10.1 Multicast Ranges
              11. 13.2.1.4.6.1.11 Aging and Auto Aging
              12. 13.2.1.4.6.1.12 ALE Policing and Classification
                1. 13.2.1.4.6.1.12.1 ALE Policing
                2. 13.2.1.4.6.1.12.2 Classifier to Host Thread Mapping
                3. 13.2.1.4.6.1.12.3 ALE Classification
              13. 13.2.1.4.6.1.13 Mirroring
              14. 13.2.1.4.6.1.14 Trunking
              15. 13.2.1.4.6.1.15 DSCP
              16. 13.2.1.4.6.1.16 Packet Forwarding Processes
                1. 13.2.1.4.6.1.16.1 Ingress Filtering Process
                2. 13.2.1.4.6.1.16.2 VLAN Lookup Process
                3. 13.2.1.4.6.1.16.3 Egress Process
                4. 13.2.1.4.6.1.16.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.16.4.1 Learning Process
                  2. 2.1.4.6.1.16.4.2 Updating Process
                  3. 2.1.4.6.1.16.4.3 Touching Process
              17. 13.2.1.4.6.1.17 VLAN Aware Mode
              18. 13.2.1.4.6.1.18 VLAN Unaware Mode
              19. 13.2.1.4.6.1.19 Transmit VLAN Processing
                1. 13.2.1.4.6.1.19.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 13.2.1.4.6.1.19.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 13.2.1.4.6.1.19.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
            2. 13.2.1.4.6.2  Packet Priority Handling
              1. 13.2.1.4.6.2.1 Ethernet Port Receive
              2. 13.2.1.4.6.2.2 CPDMA Port Receive
              3. 13.2.1.4.6.2.3 CPDMA Port Transmit
              4. 13.2.1.4.6.2.4 Priority Mapping and Transmit VLAN Priority
            3. 13.2.1.4.6.3  CPPI Port Ingress
            4. 13.2.1.4.6.4  Packet CRC Handling
              1. 13.2.1.4.6.4.1 Ethernet Port Ingress Packet CRC
              2. 13.2.1.4.6.4.2 Ethernet Port Egress Packet CRC
              3. 13.2.1.4.6.4.3 CPPI Port Ingress Packet CRC
              4. 13.2.1.4.6.4.4 CPPI Port Egress Packet CRC
            5. 13.2.1.4.6.5  FIFO Memory Control
            6. 13.2.1.4.6.6  FIFO Transmit Queue Control
            7. 13.2.1.4.6.7  Rate Limiting (Traffic Shaping)
              1. 13.2.1.4.6.7.1 CPPI Port Receive Rate Limiting
              2. 13.2.1.4.6.7.2 Ethernet Port Transmit Rate Limiting
            8. 13.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 13.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 13.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 13.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 13.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 13.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 13.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 13.2.1.4.6.9  Audio Video Bridging
              1. 13.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 13.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 13.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 13.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 13.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 13.2.1.4.6.10 Ethernet MAC Sliver
              1. 13.2.1.4.6.10.1 Ethernet MAC Sliver Overview
                1. 13.2.1.4.6.10.1.1 CRC Insertion
                2. 13.2.1.4.6.10.1.2 MTXER
                3. 13.2.1.4.6.10.1.3 Adaptive Performance Optimization (APO)
                4. 13.2.1.4.6.10.1.4 Inter-Packet-Gap Enforcement
                5. 13.2.1.4.6.10.1.5 Back Off
                6. 13.2.1.4.6.10.1.6 Programmable Transmit Inter-Packet Gap
                7. 13.2.1.4.6.10.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 13.2.1.4.6.10.2 RMII Interface
                1. 13.2.1.4.6.10.2.1 Features
                2. 13.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 13.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 13.2.1.4.6.10.3 RGMII Interface
                1. 13.2.1.4.6.10.3.1 Features
                2. 13.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 13.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 13.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 13.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 13.2.1.4.6.10.4 Frame Classification
              5. 13.2.1.4.6.10.5 Receive FIFO Architecture
            11. 13.2.1.4.6.11 Embedded Memories
            12. 13.2.1.4.6.12 Memory Error Detection and Correction
              1. 13.2.1.4.6.12.1 Packet Header ECC
              2. 13.2.1.4.6.12.2 Packet Protect CRC
              3. 13.2.1.4.6.12.3 Aggregator RAM Control
            13. 13.2.1.4.6.13 Ethernet Port Flow Control
              1. 13.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 13.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 13.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 13.2.1.4.6.13.2 Flow Control Trigger
              3. 13.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 13.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 13.2.1.4.6.15 Ethernet Switch Latency
            16. 13.2.1.4.6.16 MAC Emulation Control
            17. 13.2.1.4.6.17 MAC Command IDLE
            18. 13.2.1.4.6.18 CPSW Network Statistics
              1. 13.2.1.4.6.18.1 Rx-only Statistics Descriptions
                1. 13.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h)
                2. 13.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 13.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 13.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 13.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 13.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 13.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 13.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 13.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 13.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h)
                11. 13.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A05Ch)
                12. 13.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h)
                13. 13.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 13.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h)
                15. 13.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 13.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h)
                17. 13.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 13.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 13.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.1.4.6.18.1.19.11 ALE Policer Match (Offset = 3A0C0h)
                  12. 2.1.4.6.18.1.19.12 ALE Policer Match Red (Offset = 3A0C4h)
                  13. 2.1.4.6.18.1.19.13 ALE Policer Match Yellow (Offset = 3A0C8h)
              2. 13.2.1.4.6.18.2 Tx-only Statistics Descriptions
                1. 13.2.1.4.6.18.2.1  Good Tx Frames (Offset = 3A034h)
                2. 13.2.1.4.6.18.2.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 13.2.1.4.6.18.2.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 13.2.1.4.6.18.2.4  Pause Tx Frames (Offset = 3A040h)
                5. 13.2.1.4.6.18.2.5  Deferred Tx Frames (Offset = 3A044h)
                6. 13.2.1.4.6.18.2.6  Collisions (Offset = 3A048h)
                7. 13.2.1.4.6.18.2.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 13.2.1.4.6.18.2.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 13.2.1.4.6.18.2.9  Excessive Collisions (Offset = 3A054h)
                10. 13.2.1.4.6.18.2.10 Late Collisions (Offset = 3A058h)
                11. 13.2.1.4.6.18.2.11 Carrier Sense Errors (Offset = 3A060h)
                12. 13.2.1.4.6.18.2.12 Tx Octets (Offset = 3A064h)
                13. 13.2.1.4.6.18.2.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 13.2.1.4.6.18.2.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8)
                15. 13.2.1.4.6.18.2.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 13.2.1.4.6.18.2.16 Tx CRC Errors
              3. 13.2.1.4.6.18.3 Rx- and Tx (Shared) Statistics Descriptions
                1. 13.2.1.4.6.18.3.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 13.2.1.4.6.18.3.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 13.2.1.4.6.18.3.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 13.2.1.4.6.18.3.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 13.2.1.4.6.18.3.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 13.2.1.4.6.18.3.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 13.2.1.4.6.18.3.7 Net Octets (Offset = 3A080h)
              4. 13.2.1.4.6.18.4 1765
          7. 13.2.1.4.7  Common Platform Time Sync (CPTS)
            1. 13.2.1.4.7.1  CPTS Architecture
            2. 13.2.1.4.7.2  CPTS Initialization
            3. 13.2.1.4.7.3  32-bit Time Stamp Value
            4. 13.2.1.4.7.4  64-bit Time Stamp Value
            5. 13.2.1.4.7.5  64-Bit Timestamp Nudge
            6. 13.2.1.4.7.6  64-bit Timestamp PPM
            7. 13.2.1.4.7.7  Event FIFO
            8. 13.2.1.4.7.8  Timestamp Compare Output
              1. 13.2.1.4.7.8.1 Non-Toggle Mode: 32-bit
              2. 13.2.1.4.7.8.2 Non-Toggle Mode: 64-bit
              3. 13.2.1.4.7.8.3 Toggle Mode: 32-bit
              4. 13.2.1.4.7.8.4 Toggle Mode: 64-bit
            9. 13.2.1.4.7.9  Timestamp Sync Output
            10. 13.2.1.4.7.10 Timestamp GENFn Output
              1. 13.2.1.4.7.10.1 GENFn Nudge
              2. 13.2.1.4.7.10.2 GENFn PPM
            11. 13.2.1.4.7.11 Timestamp ESTFn
            12. 13.2.1.4.7.12 Time Sync Events
              1. 13.2.1.4.7.12.1 Time Stamp Push Event
              2. 13.2.1.4.7.12.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 13.2.1.4.7.12.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 13.2.1.4.7.12.4 Hardware Time Stamp Push Event
              5. 13.2.1.4.7.12.5 Ethernet Port Events
                1. 13.2.1.4.7.12.5.1 Ethernet Port Receive Event
                2. 13.2.1.4.7.12.5.2 Ethernet Port Transmit Event
                3. 13.2.1.4.7.12.5.3 1792
            13. 13.2.1.4.7.13 Timestamp Compare Event
              1. 13.2.1.4.7.13.1 32-Bit Mode
              2. 13.2.1.4.7.13.2 64-Bit Mode
            14. 13.2.1.4.7.14 Host Transmit Event
            15. 13.2.1.4.7.15 CPTS Interrupt Handling
          8. 13.2.1.4.8  CPDMA Host Interface
            1. 13.2.1.4.8.1 Functional Operation
            2. 13.2.1.4.8.2 Transmit CPDMA Interface
              1. 13.2.1.4.8.2.1 Transmit CPDMA Host Configuration
              2. 13.2.1.4.8.2.2 Transmit CPDMA Buffer Descriptors
              3. 13.2.1.4.8.2.3 Transmit Channel Teardown
            3. 13.2.1.4.8.3 Receive CPDMA Interface
              1. 13.2.1.4.8.3.1 Receive CPDMA Host Configuration
              2. 13.2.1.4.8.3.2 Receive DMA Host Configuration
              3. 13.2.1.4.8.3.3 Receive Channel Teardown
              4. 13.2.1.4.8.3.4 Receive CPDMA Hardware Controlled Packet Transmission
            4. 13.2.1.4.8.4 VLAN Aware Mode
            5. 13.2.1.4.8.5 VLAN Unaware Mode
            6. 13.2.1.4.8.6 CPDMA Big Endian Mode
            7. 13.2.1.4.8.7 CPDMA Command IDLE
            8. 13.2.1.4.8.8 CPDMA CPPI 3.0 Interface Bandwidth
          9. 13.2.1.4.9  CPPI Checksum Offload
            1. 13.2.1.4.9.1 CPPI Transmit Checksum Offload
              1. 13.2.1.4.9.1.1 IPV4 UDP
              2. 13.2.1.4.9.1.2 IPV4 TCP
              3. 13.2.1.4.9.1.3 IPV6 UDP
              4. 13.2.1.4.9.1.4 IPV6 TCP
              5. 13.2.1.4.9.1.5 Transmit Checksum Encapsulation Word
            2. 13.2.1.4.9.2 CPPI Receive Checksum Offload
              1. 13.2.1.4.9.2.1 Receive Checksum Encapsulation Word
          10. 13.2.1.4.10 Egress Packet Operations
          11. 13.2.1.4.11 MII Management Interface (MDIO)
            1. 13.2.1.4.11.1 MDIO Frame Formats
            2. 13.2.1.4.11.2 MDIO Functional Description
        5. 13.2.1.5 CPSW0 Programming Guide
          1. 13.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 13.2.1.5.2 Transmit Operation
          3. 13.2.1.5.3 Receive Operation
          4. 13.2.1.5.4 CPSW Reset
          5. 13.2.1.5.5 MDIO Software Interface
            1. 13.2.1.5.5.1 Initializing the MDIO Module
            2. 13.2.1.5.5.2 Writing Data To a PHY Register
            3. 13.2.1.5.5.3 Reading Data From a PHY Register
    3. 13.3 Memory Interfaces
      1. 13.3.1 General-Purpose Memory Controller (GPMC)
        1. 13.3.1.1 GPMC Overview
          1. 13.3.1.1.1 GPMC Features
          2. 13.3.1.1.2 GPMC Not Supported Features
        2. 13.3.1.2 GPMC Environment
          1. 13.3.1.2.1 GPMC Modes
          2. 13.3.1.2.2 GPMC I/O Signals
        3. 13.3.1.3 GPMC Integration
        4. 13.3.1.4 GPMC Functional Description
          1. 13.3.1.4.1  GPMC Block Diagram
          2. 13.3.1.4.2  GPMC Clock Configuration
          3. 13.3.1.4.3  GPMC Power Management
          4. 13.3.1.4.4  GPMC Interrupt Requests
          5. 13.3.1.4.5  GPMC Interconnect Port Interface
          6. 13.3.1.4.6  GPMC Address and Data Bus
            1. 13.3.1.4.6.1 GPMC I/O Configuration Setting
          7. 13.3.1.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 13.3.1.4.7.1 Chip-Select Base Address and Region Size
            2. 13.3.1.4.7.2 Access Protocol
              1. 13.3.1.4.7.2.1 Supported Devices
              2. 13.3.1.4.7.2.2 Access Size Adaptation and Device Width
              3. 13.3.1.4.7.2.3 Address/Data-Multiplexing Interface
            3. 13.3.1.4.7.3 External Signals
              1. 13.3.1.4.7.3.1 WAIT Pin Monitoring Control
                1. 13.3.1.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 13.3.1.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 13.3.1.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 13.3.1.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 13.3.1.4.7.3.1.5 Wait With NAND Device
                6. 13.3.1.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.1.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.1.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.1.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 13.3.1.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 13.3.1.4.7.3.2 DIR Pin
              3. 13.3.1.4.7.3.3 Reset
              4. 13.3.1.4.7.3.4 Write Protect Signal (nWP)
              5. 13.3.1.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 13.3.1.4.7.4 Error Handling
          8. 13.3.1.4.8  GPMC Timing Setting
            1. 13.3.1.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 13.3.1.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 13.3.1.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 13.3.1.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 13.3.1.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 13.3.1.4.8.6  GPMC_CLKOUT
            7. 13.3.1.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 13.3.1.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 13.3.1.4.8.8.1 Access Time on Read Access
              2. 13.3.1.4.8.8.2 Access Time on Write Access
            9. 13.3.1.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 13.3.1.4.8.9.1 Page Burst Access Time on Read Access
              2. 13.3.1.4.8.9.2 Page Burst Access Time on Write Access
            10. 13.3.1.4.8.10 Bus Keeping Support
          9. 13.3.1.4.9  GPMC NOR Access Description
            1. 13.3.1.4.9.1 Asynchronous Access Description
              1. 13.3.1.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 13.3.1.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 13.3.1.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 13.3.1.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 13.3.1.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 13.3.1.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 13.3.1.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 13.3.1.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 13.3.1.4.9.2 Synchronous Access Description
              1. 13.3.1.4.9.2.1 Synchronous Single Read
              2. 13.3.1.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 13.3.1.4.9.2.3 Synchronous Single Write
              4. 13.3.1.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 13.3.1.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 13.3.1.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 13.3.1.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 13.3.1.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 13.3.1.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 13.3.1.4.9.4 Page and Burst Support
            5. 13.3.1.4.9.5 System Burst vs External Device Burst Support
          10. 13.3.1.4.10 GPMC pSRAM Access Specificities
          11. 13.3.1.4.11 GPMC NAND Access Description
            1. 13.3.1.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 13.3.1.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 13.3.1.4.11.1.2 NAND Device Command and Address Phase Control
              3. 13.3.1.4.11.1.3 Command Latch Cycle
              4. 13.3.1.4.11.1.4 Address Latch Cycle
              5. 13.3.1.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 13.3.1.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 13.3.1.4.11.1.7 Read and Write Access Size Adaptation
                1. 13.3.1.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 13.3.1.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 13.3.1.4.11.2 NAND Device-Ready Pin
              1. 13.3.1.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 13.3.1.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 13.3.1.4.11.3 ECC Calculator
              1. 13.3.1.4.11.3.1 Hamming Code
                1. 13.3.1.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 13.3.1.4.11.3.1.2 ECC Enabling
                3. 13.3.1.4.11.3.1.3 ECC Computation
                4. 13.3.1.4.11.3.1.4 ECC Comparison and Correction
                5. 13.3.1.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 13.3.1.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 13.3.1.4.11.3.2 BCH Code
                1. 13.3.1.4.11.3.2.1 Requirements
                2. 13.3.1.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.1.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.1.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.1.4.11.3.2.2.3 Wrapping Modes
                    1. 1.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 1.4.11.3.2.2.3.2  Mode 0x1
                    3. 1.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 1.4.11.3.2.2.3.4  Mode 0x2
                    5. 1.4.11.3.2.2.3.5  Mode 0x3
                    6. 1.4.11.3.2.2.3.6  Mode 0x7
                    7. 1.4.11.3.2.2.3.7  Mode 0x8
                    8. 1.4.11.3.2.2.3.8  Mode 0x4
                    9. 1.4.11.3.2.2.3.9  Mode 0x9
                    10. 1.4.11.3.2.2.3.10 Mode 0x5
                    11. 1.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 1.4.11.3.2.2.3.12 Mode 0x6
                3. 13.3.1.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.1.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.1.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.1.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 13.3.1.4.11.4 Prefetch and Write-Posting Engine
              1. 13.3.1.4.11.4.1 General Facts About the Engine Configuration
              2. 13.3.1.4.11.4.2 Prefetch Mode
              3. 13.3.1.4.11.4.3 FIFO Control in Prefetch Mode
              4. 13.3.1.4.11.4.4 Write-Posting Mode
              5. 13.3.1.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 13.3.1.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 13.3.1.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 13.3.1.4.12 GPMC Memory Regions
          13. 13.3.1.4.13 GPMC Use Cases and Tips
            1. 13.3.1.4.13.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 13.3.1.4.13.1.1 External Memory Attached to the GPMC Module
              2. 13.3.1.4.13.1.2 Typical GPMC Setup
                1. 13.3.1.4.13.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 13.3.1.4.13.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 13.3.1.4.13.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 13.3.1.4.13.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 13.3.1.4.13.2.1 Supported Memories or Devices
                1. 13.3.1.4.13.2.1.1 Memory Pin Multiplexing
                2. 13.3.1.4.13.2.1.2 NAND Interface Protocol
                3. 13.3.1.4.13.2.1.3 NOR Interface Protocol
                4. 13.3.1.4.13.2.1.4 Other Technologies
        5. 13.3.1.5 GPMC Basic Programming Model
          1. 13.3.1.5.1 GPMC High-Level Programming Model Overview
          2. 13.3.1.5.2 GPMC Initialization
          3. 13.3.1.5.3 GPMC Configuration in NOR Mode
          4. 13.3.1.5.4 GPMC Configuration in NAND Mode
          5. 13.3.1.5.5 Set Memory Access
          6. 13.3.1.5.6 GPMC Timing Parameters
            1. 13.3.1.5.6.1 GPMC Timing Parameters Formulas
              1. 13.3.1.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 13.3.1.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 13.3.1.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
      2. 13.3.2 Error Location Module (ELM)
        1. 13.3.2.1 ELM Overview
          1. 13.3.2.1.1 ELM Features
          2. 13.3.2.1.2 ELM Not Supported Features
        2. 13.3.2.2 ELM Integration
        3. 13.3.2.3 ELM Functional Description
          1. 13.3.2.3.1 ELM Software Reset
          2. 13.3.2.3.2 ELM Power Management
          3. 13.3.2.3.3 ELM Interrupt Requests
          4. 13.3.2.3.4 ELM Processing Initialization
          5. 13.3.2.3.5 ELM Processing Sequence
          6. 13.3.2.3.6 ELM Processing Completion
        4. 13.3.2.4 ELM Basic Programming Model
          1. 13.3.2.4.1 ELM Low-Level Programming Model
            1. 13.3.2.4.1.1 Processing Initialization
            2. 13.3.2.4.1.2 Read Results
          2. 13.3.2.4.2 Use Case: ELM Used in Continuous Mode
          3. 13.3.2.4.3 Use Case: ELM Used in Page Mode
      3. 13.3.3 Multimedia Card (MMC)
        1. 13.3.3.1 Introduction
          1. 13.3.3.1.1 MMCSD Features
          2. 13.3.3.1.2 Unsupported MMCSD Features
        2. 13.3.3.2 Integration
          1. 13.3.3.2.1 MMCSD Integration
          2. 13.3.3.2.2 MMCSD Connectivity Attributes
          3. 13.3.3.2.3 MMCSD Clock and Reset Management
          4. 13.3.3.2.4 MMCSD Pin List
        3. 13.3.3.3 Functional Description
          1. 13.3.3.3.1  MMC/SD/SDIO Functional Modes
            1. 13.3.3.3.1.1 MMC/SD/SDIO Connected to an MMC, an SD Card, or an SDIO Card
            2. 13.3.3.3.1.2 Protocol and Data Format
              1. 13.3.3.3.1.2.1 Protocol
              2. 13.3.3.3.1.2.2 Data Format
          2. 13.3.3.3.2  Resets
            1. 13.3.3.3.2.1 Hardware Reset
            2. 13.3.3.3.2.2 Software Reset
          3. 13.3.3.3.3  Power Management
            1. 13.3.3.3.3.1 Normal Mode
            2. 13.3.3.3.3.2 Idle Mode
            3. 13.3.3.3.3.3 Transition from Normal Mode to Smart-Idle Mode
            4. 13.3.3.3.3.4 Transition from Smart-Idle Mode to Normal Mode
            5. 13.3.3.3.3.5 Force-Idle Mode
            6. 13.3.3.3.3.6 Local Power Management
          4. 13.3.3.3.4  Interrupt Requests
            1. 13.3.3.3.4.1 Interrupt-Driven Operation
            2. 13.3.3.3.4.2 Polling
          5. 13.3.3.3.5  DMA Modes
            1. 13.3.3.3.5.1 DMA Responder Mode Operations
              1. 13.3.3.3.5.1.1 DMA Receive Mode
              2. 13.3.3.3.5.1.2 DMA Transmit Mode
          6. 13.3.3.3.6  Mode Selection
          7. 13.3.3.3.7  Buffer Management
            1. 13.3.3.3.7.1 Data Buffer
              1. 13.3.3.3.7.1.1 Memory Size, Block Length, and Buffer Management Relationship
              2. 13.3.3.3.7.1.2 Data Buffer Status
          8. 13.3.3.3.8  Transfer Process
            1. 13.3.3.3.8.1 Different Types of Commands
            2. 13.3.3.3.8.2 Different Types of Responses
          9. 13.3.3.3.9  Transfer or Command Status and Error Reporting
            1. 13.3.3.3.9.1 Busy Timeout for R1b, R5b Response Type
            2. 13.3.3.3.9.2 Busy Timeout After Write CRC Status
            3. 13.3.3.3.9.3 Write CRC Status Timeout
            4. 13.3.3.3.9.4 Read Data Timeout
          10. 13.3.3.3.10 Transfer Stop
          11. 13.3.3.3.11 Output Signals Generation
            1. 13.3.3.3.11.1 Generation on Falling Edge of MMC Clock
            2. 13.3.3.3.11.2 Generation on Rising Edge of MMC Clock
          12. 13.3.3.3.12 CE-ATA Command Completion Disable Management
          13. 13.3.3.3.13 Test Registers
          14. 13.3.3.3.14 MMC/SD/SDIO Hardware Status Features
        4. 13.3.3.4 Low-Level Programming Models
          1. 13.3.3.4.1 Surrounding Modules Global Initialization
          2. 13.3.3.4.2 MMC/SD/SDIO Controller Initialization Flow
            1. 13.3.3.4.2.1 Enable OCP and CLKADPI Clocks
            2. 13.3.3.4.2.2 SD Soft Reset Flow
            3. 13.3.3.4.2.3 Set SD Default Capabilities
            4. 13.3.3.4.2.4 Wake-Up Configuration
            5. 13.3.3.4.2.5 MMC Host and Bus Configuration
          3. 13.3.3.4.3 Operational Modes Configuration
            1. 13.3.3.4.3.1 Basic Operations for MMC/SD/SDIO Host Controller
            2. 13.3.3.4.3.2 Card Detection, Identification, and Selection
      4. 13.3.4 Quad Serial Peripheral Interface (QSPI)
        1. 13.3.4.1 Quad Serial Peripheral Interface Overview
          1. 13.3.4.1.1 Features Supported
          2. 13.3.4.1.2 Features Not Supported
        2. 13.3.4.2 QSPI Environment
        3. 13.3.4.3 QSPI Integration
        4. 13.3.4.4 QSPI Functional Description
          1. 13.3.4.4.1 QSPI Block Diagram
            1. 13.3.4.4.1.1 SFI Memory Mapped Protocol
              1. 13.3.4.4.1.1.1 SFI Register Control
              2. 13.3.4.4.1.1.2 SFI Translator
            2. 13.3.4.4.1.2 SPI Configurable Block
              1. 13.3.4.4.1.2.1 SPI Control Interface
              2. 13.3.4.4.1.2.2 SPI Clock Generator
              3. 13.3.4.4.1.2.3 SPI Control State-Machine
              4. 13.3.4.4.1.2.4 SPI Data Shifter
          2. 13.3.4.4.2 QSPI Interrupt Requests
          3. 13.3.4.4.3 QSPI Memory Regions
    4. 13.4 Industrial and Control Interfaces
      1. 13.4.1 Modular Controller Area Network (MCAN)
        1. 13.4.1.1 MCAN Overview
          1. 13.4.1.1.1 MCAN Features
          2. 13.4.1.1.2 MCAN Not Supported Features
        2. 13.4.1.2 MCAN Environment
          1. 13.4.1.2.1 CAN Network Basics
        3. 13.4.1.3 MCAN Integration
        4. 13.4.1.4 MCAN Functional Description
          1. 13.4.1.4.1  Module Clocking Requirements
          2. 13.4.1.4.2  Interrupt and DMA Requests
            1. 13.4.1.4.2.1 Interrupt Requests
            2. 13.4.1.4.2.2 DMA Requests
          3. 13.4.1.4.3  Operating Modes
            1. 13.4.1.4.3.1 Software Initialization
            2. 13.4.1.4.3.2 Normal Operation
            3. 13.4.1.4.3.3 CAN FD Operation
            4. 13.4.1.4.3.4 Transmitter Delay Compensation
              1. 13.4.1.4.3.4.1 Description
              2. 13.4.1.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 13.4.1.4.3.5 Restricted Operation Mode
            6. 13.4.1.4.3.6 Bus Monitoring Mode
            7. 13.4.1.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 13.4.1.4.3.7.1 Frame Transmission in DAR Mode
            8. 13.4.1.4.3.8 Power Down (Sleep Mode)
              1. 13.4.1.4.3.8.1 External Clock Stop Mode
              2. 13.4.1.4.3.8.2 Suspend Mode
              3. 13.4.1.4.3.8.3 Wakeup request
            9. 13.4.1.4.3.9 Test Modes
              1. 13.4.1.4.3.9.1 Internal Loopback Mode
          4. 13.4.1.4.4  Timestamp Generation
            1. 13.4.1.4.4.1 External Timestamp Counter
          5. 13.4.1.4.5  Timeout Counter
          6. 13.4.1.4.6  ECC Support
            1. 13.4.1.4.6.1 ECC Wrapper
          7. 13.4.1.4.7  Rx Handling
            1. 13.4.1.4.7.1 Acceptance Filtering
              1. 13.4.1.4.7.1.1 Range Filter
              2. 13.4.1.4.7.1.2 Filter for specific IDs
              3. 13.4.1.4.7.1.3 Classic Bit Mask Filter
              4. 13.4.1.4.7.1.4 Standard Message ID Filtering
              5. 13.4.1.4.7.1.5 Extended Message ID Filtering
            2. 13.4.1.4.7.2 Rx FIFOs
              1. 13.4.1.4.7.2.1 Rx FIFO Blocking Mode
              2. 13.4.1.4.7.2.2 Rx FIFO Overwrite Mode
            3. 13.4.1.4.7.3 Dedicated Rx Buffers
              1. 13.4.1.4.7.3.1 Rx Buffer Handling
            4. 13.4.1.4.7.4 Debug on CAN Support
          8. 13.4.1.4.8  Tx Handling
            1. 13.4.1.4.8.1 Transmit Pause
            2. 13.4.1.4.8.2 Dedicated Tx Buffers
            3. 13.4.1.4.8.3 Tx FIFO
            4. 13.4.1.4.8.4 Tx Queue
            5. 13.4.1.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 13.4.1.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 13.4.1.4.8.7 Transmit Cancellation
            8. 13.4.1.4.8.8 Tx Event Handling
          9. 13.4.1.4.9  FIFO Acknowledge Handling
          10. 13.4.1.4.10 Message RAM
            1. 13.4.1.4.10.1 Message RAM Configuration
            2. 13.4.1.4.10.2 Rx Buffer and FIFO Element
            3. 13.4.1.4.10.3 Tx Buffer Element
            4. 13.4.1.4.10.4 Tx Event FIFO Element
            5. 13.4.1.4.10.5 Standard Message ID Filter Element
            6. 13.4.1.4.10.6 Extended Message ID Filter Element
        5. 13.4.1.5 MCAN Programming Guide
      2. 13.4.2 Local Interconnect Network (LIN)
        1. 13.4.2.1 LIN Overview
          1. 13.4.2.1.1 SCI Features
          2. 13.4.2.1.2 LIN Mode Features
          3. 13.4.2.1.3 Block Diagram
        2.       2161
        3. 13.4.2.2 LIN Integration
        4. 13.4.2.3 Serial Communications Interface Module
          1. 13.4.2.3.1 SCI Communication Formats
            1. 13.4.2.3.1.1 SCI Frame Formats
            2. 13.4.2.3.1.2 SCI Asynchronous Timing Mode
            3. 13.4.2.3.1.3 SCI Baud Rate
            4. 13.4.2.3.1.4 SCI Multiprocessor Communication Modes
              1. 13.4.2.3.1.4.1 Idle-Line Multiprocessor Modes
              2. 13.4.2.3.1.4.2 Address-Bit Multiprocessor Mode
            5. 13.4.2.3.1.5 SCI Multibuffered Mode
          2. 13.4.2.3.2 SCI Interrupts
            1. 13.4.2.3.2.1 Transmit Interrupt
            2. 13.4.2.3.2.2 Receive Interrupt
            3. 13.4.2.3.2.3 WakeUp Interrupt
            4. 13.4.2.3.2.4 Error Interrupts
          3. 13.4.2.3.3 SCI DMA Interface
            1. 13.4.2.3.3.1 Receive DMA Requests
            2. 13.4.2.3.3.2 Transmit DMA Requests
          4. 13.4.2.3.4 SCI Configurations
            1. 13.4.2.3.4.1 Receiving Data
              1. 13.4.2.3.4.1.1 Receiving Data in Single-Buffer Mode
              2. 13.4.2.3.4.1.2 Receiving Data in Multibuffer Mode
            2. 13.4.2.3.4.2 Transmitting Data
              1. 13.4.2.3.4.2.1 Transmitting Data in Single-Buffer Mode
              2. 13.4.2.3.4.2.2 Transmitting Data in Multibuffer Mode
          5. 13.4.2.3.5 SCI Low-Power Mode
            1. 13.4.2.3.5.1 Sleep Mode for Multiprocessor Communication
        5. 13.4.2.4 Local Interconnect Network Module
          1. 13.4.2.4.1 LIN Communication Formats
            1. 13.4.2.4.1.1  LIN Standards
            2. 13.4.2.4.1.2  Message Frame
              1. 13.4.2.4.1.2.1 Message Header
              2. 13.4.2.4.1.2.2 Response
            3. 13.4.2.4.1.3  Synchronizer
            4. 13.4.2.4.1.4  Baud Rate
              1. 13.4.2.4.1.4.1 Fractional Divider
              2. 13.4.2.4.1.4.2 Superfractional Divider
                1. 13.4.2.4.1.4.2.1 Superfractional Divider In LIN Mode
            5. 13.4.2.4.1.5  Header Generation
              1. 13.4.2.4.1.5.1 Event Triggered Frame Handling
              2. 13.4.2.4.1.5.2 Header Reception and Adaptive Baud Rate
            6. 13.4.2.4.1.6  Extended Frames Handling
            7. 13.4.2.4.1.7  Timeout Control
              1. 13.4.2.4.1.7.1 No-Response Error (NRE)
              2. 13.4.2.4.1.7.2 Bus Idle Detection
              3. 13.4.2.4.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
            8. 13.4.2.4.1.8  TXRX Error Detector (TED)
              1. 13.4.2.4.1.8.1 Bit Errors
              2. 13.4.2.4.1.8.2 Physical Bus Errors
              3. 13.4.2.4.1.8.3 ID Parity Errors
              4. 13.4.2.4.1.8.4 Checksum Errors
            9. 13.4.2.4.1.9  Message Filtering and Validation
            10. 13.4.2.4.1.10 Receive Buffers
            11. 13.4.2.4.1.11 Transmit Buffers
          2. 13.4.2.4.2 LIN Interrupts
          3. 13.4.2.4.3 Servicing LIN Interrupts
          4. 13.4.2.4.4 LIN DMA Interface
            1. 13.4.2.4.4.1 LIN Receive DMA Requests
            2. 13.4.2.4.4.2 LIN Transmit DMA Requests
          5. 13.4.2.4.5 LIN Configurations
            1. 13.4.2.4.5.1 Receiving Data
              1. 13.4.2.4.5.1.1 Receiving Data in Single-Buffer Mode
              2. 13.4.2.4.5.1.2 Receiving Data in Multibuffer Mode
            2. 13.4.2.4.5.2 Transmitting Data
              1. 13.4.2.4.5.2.1 Transmitting Data in Single-Buffer Mode
              2. 13.4.2.4.5.2.2 Transmitting Data in Multibuffer Mode
        6. 13.4.2.5 Low-Power Mode
          1. 13.4.2.5.1 Entering Sleep Mode
          2. 13.4.2.5.2 Wakeup
          3. 13.4.2.5.3 Wakeup Timeouts
        7. 13.4.2.6 Emulation Mode
        8. 13.4.2.7 LIN Programming Guide
    5. 13.5 Timer Modules
      1. 13.5.1 Real Time Interrupts/Windowed Watchdog Timer (RTI/WWDT)
        1. 13.5.1.1 RTI/WWDT Overview
          1. 13.5.1.1.1 RTI Features
          2. 13.5.1.1.2 RTI Unsupported Features
        2. 13.5.1.2 RTI Integration
        3. 13.5.1.3 WWDT Integration
        4. 13.5.1.4 RTI Functional Description
          1. 13.5.1.4.1 RTI Digital Windowed Watchdog
            1. 13.5.1.4.1.1 RTI Debug Mode Behavior
          2. 13.5.1.4.2 RTI Digital Watchdog
          3. 13.5.1.4.3 RTI Counter Operation
        5. 13.5.1.5 RTI/WWDT Programming Guide
    6. 13.6 Internal Diagnostics Modules
      1. 13.6.1 Dual Clock Comparator (DCC)
        1. 13.6.1.1 DCC Overview
          1. 13.6.1.1.1 DCC Features
          2. 13.6.1.1.2 DCC Not Supported Features
        2. 13.6.1.2 DCC Integration
          1. 13.6.1.2.1 DCC Integration
        3. 13.6.1.3 DCC Functional Description
          1. 13.6.1.3.1 DCC Counter Operation
          2. 13.6.1.3.2 DCC Clock Sources
          3. 13.6.1.3.3 DCC Mode of Operation
            1. 13.6.1.3.3.1 DCC Single-Shot Mode
            2. 13.6.1.3.3.2 DCC Continuous Mode
              1. 13.6.1.3.3.2.1 DCC Continue on Error
              2. 13.6.1.3.3.2.2 DCC Error Count
          4. 13.6.1.3.4 DCC Error Trajectory Record
            1. 13.6.1.3.4.1 DCC FIFO Capturing for Errors
            2. 13.6.1.3.4.2 DCC FIFO in Continuous Capture Mode
            3. 13.6.1.3.4.3 DCC FIFO Details
          5. 13.6.1.3.5 DCC Count Read Registers
          6. 13.6.1.3.6 Limp Mode Generation
      2. 13.6.2 ECC Aggregator
        1. 13.6.2.1 ECC Aggregator Overview
          1. 13.6.2.1.1 ECC Aggregator Features
        2. 13.6.2.2 ECC Aggregator Integration
          1. 13.6.2.2.1 ECC Aggregator Integration
        3. 13.6.2.3 ECC Aggregator Functional Description
          1. 13.6.2.3.1 ECC Aggregator Block Diagram
          2. 13.6.2.3.2 ECC Aggregator Register Groups
          3. 13.6.2.3.3 Read Access to the ECC Control and Status Registers
          4. 13.6.2.3.4 Serial Write Operation
          5. 13.6.2.3.5 Interrupts
          6. 13.6.2.3.6 Inject Only Mode
      3. 13.6.3 Error Signaling Module (ESM)
        1. 13.6.3.1 ESM Overview
        2. 13.6.3.2 ESM Features
        3. 13.6.3.3 ESM Integration
        4. 13.6.3.4 ESM Functional Description
          1. 13.6.3.4.1 ESM Functional Operation
          2. 13.6.3.4.2 Error Interrupt Outputs
          3. 13.6.3.4.3 ESM Error Pin Output
          4. 13.6.3.4.4 Error Pin Behavior During Reset
          5. 13.6.3.4.5 PWM Mode
          6. 13.6.3.4.6 Minimum Time Interval
          7. 13.6.3.4.7 Safety Protection for MMRs
          8. 13.6.3.4.8 ESM Interrupts
          9. 13.6.3.4.9 Programming Guide
            1. 13.6.3.4.9.1 Configuration Error Interrupt
            2. 13.6.3.4.9.2 Low Priority Error Interrupt
            3. 13.6.3.4.9.3 High Priority Error Interrupt
      4. 13.6.4 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 13.6.4.1 MCRC Overview
          1. 13.6.4.1.1 MCRC Features
        2. 13.6.4.2 MCRC Integration
        3. 13.6.4.3 MCRC Functional Description
          1. 13.6.4.3.1  MCRC Block Diagram
          2. 13.6.4.3.2  MCRC General Operation
          3. 13.6.4.3.3  MCRC Modes of Operation
            1. 13.6.4.3.3.1 AUTO Mode
            2. 13.6.4.3.3.2 Semi-CPU Mode
            3. 13.6.4.3.3.3 Full-CPU Mode
          4. 13.6.4.3.4  PSA Signature Register
          5. 13.6.4.3.5  PSA Sector Signature Register
          6. 13.6.4.3.6  CRC Value Register
          7. 13.6.4.3.7  Raw Data Register
          8. 13.6.4.3.8  Example DMA Controller Setup
            1. 13.6.4.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 13.6.4.3.8.2 AUTO Mode Using Software Trigger
            3. 13.6.4.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 13.6.4.3.9  Pattern Count Register
          10. 13.6.4.3.10 Sector Count Register/Current Sector Register
          11. 13.6.4.3.11 Interrupts
            1. 13.6.4.3.11.1 Overrun Interrupt
            2. 13.6.4.3.11.2 Timeout Interrupt
            3. 13.6.4.3.11.3 Underrun Interrupt
            4. 13.6.4.3.11.4 Compression Complete Interrupt
            5. 13.6.4.3.11.5 Interrupt Offset Register
            6. 13.6.4.3.11.6 Error Handling
          12. 13.6.4.3.12 Power Down Mode
          13. 13.6.4.3.13 Emulation
        4. 13.6.4.4 MCRC Programming Examples
          1. 13.6.4.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 13.6.4.4.1.1 DMA Setup
            2. 13.6.4.4.1.2 Timer Setup
            3. 13.6.4.4.1.3 CRC Setup
          2. 13.6.4.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 13.6.4.4.2.1 DMA Setup
            2. 13.6.4.4.2.2 CRC Setup
          3. 13.6.4.4.3 Example: Semi-CPU Mode
            1. 13.6.4.4.3.1 DMA Setup
            2. 13.6.4.4.3.2 Timer Setup
            3. 13.6.4.4.3.3 CRC Setup
          4. 13.6.4.4.4 Example: Full-CPU Mode
            1. 13.6.4.4.4.1 CRC Setup
      5. 13.6.5 Self-Test Controller (STC)
        1. 13.6.5.1 STC Overview
          1. 13.6.5.1.1 Unsupported Features
          2. 13.6.5.1.2 STC Memory Map
          3. 13.6.5.1.3 OPMISR Concept
        2. 13.6.5.2 Block Diagram
        3. 13.6.5.3 Module Description
          1. 13.6.5.3.1 ROM Interface
          2. 13.6.5.3.2 FSM and Sequence Control
            1. 13.6.5.3.2.1 Clock Control
            2. 13.6.5.3.2.2 MISR Compare Block
          3. 13.6.5.3.3 Register Block
          4. 13.6.5.3.4 VBUSP Interface
          5. 13.6.5.3.5 STC Flow
          6. 13.6.5.3.6 Programming Sequence
          7. 13.6.5.3.7 ROM Organization
            1. 13.6.5.3.7.1 TR_T: Transition Delay Methodology Type
            2. 13.6.5.3.7.2 FT: Fault Model for the BIST Run
            3. 13.6.5.3.7.3 SEG_ID[1:0]
            4. 13.6.5.3.7.4 Pattern Count ( patt_count[9:0] )
            5. 13.6.5.3.7.5 MISR_GOLDEN[895:0]: Golden Signature Data Bits
            6. 13.6.5.3.7.6 LP_MISR_GOLDEN[895:0]: Low Power Mode Golden Signature Data Bits
            7. 13.6.5.3.7.7 INV_MISR_GOLDEN[895:0]: Inverse Mode Golden Signature Data Bits
            8. 13.6.5.3.7.8 LP_INV_MISR_GOLDEN[895:0]: Low Power Inverse Mode Golden Signature Data Bits
            9. 13.6.5.3.7.9 Pn_SDm[7:0] (n - no. of patterns, m - scan chain length): OP-MISR Scan Data
      6. 13.6.6 Programmable Built-In Self-Test (PBIST) Module
        1. 13.6.6.1 Overview
          1. 13.6.6.1.1 Features of PBIST
          2. 13.6.6.1.2 PBIST vs. Application Software-Based Testing
          3. 13.6.6.1.3 PBIST Block Diagram
            1. 13.6.6.1.3.1 On-chip ROM
            2. 13.6.6.1.3.2 Host Processor Interface to the PBIST Controller Registers
            3. 13.6.6.1.3.3 Memory Data Path
        2. 13.6.6.2 PBIST Flow
        3. 13.6.6.3 PBIST RAM-ROM Memory and Algorithm Group Configuration
        4. 13.6.6.4 Memory Test Algorithms on the On-chip ROM
  16. 14On-Chip Debug
    1. 14.1 On-Chip Debug
      1. 14.1.1 On-Chip Debug Overview
      2. 14.1.2 On-Chip Debug Features
      3. 14.1.3 On-Chip Debug Functional Description
        1. 14.1.3.1 On-Chip Debug Block Diagram
        2. 14.1.3.2 Device Interfaces
          1. 14.1.3.2.1 JTAG Interface
          2. 14.1.3.2.2 Trace Port Interface
        3. 14.1.3.3 Debug and Boundary Scan Access and Control
          1. 14.1.3.3.1 DAP
            1. 14.1.3.3.1.1 Debug Subsystem Address Map
          2. 14.1.3.3.2 Boundary Scan
        4. 14.1.3.4 Reset Management
        5. 14.1.3.5 Debug Cross Triggering
          1. 14.1.3.5.1 R5F CTI Trigger Connections
          2. 14.1.3.5.2 Cortex M4 CTI Trigger Connections
          3. 14.1.3.5.3 STM CTI Trigger Connections
          4. 14.1.3.5.4 DEBUGSS CS-CTI Trigger Connections
        6. 14.1.3.6 SOC Debug and Trace
          1. 14.1.3.6.1 Software Messaging Trace
          2. 14.1.3.6.2 Debug Aware Peripherals
        7. 14.1.3.7 Trace Infrastructure
          1. 14.1.3.7.1 Trace Sources
          2. 14.1.3.7.2 Trace Distribution
          3. 14.1.3.7.3 Trace Sinks
      4. 14.1.4 Arm Debug Links
  17.   Revision History
13.2.1.5.2 Transmit Operation

After reset, the host must write zeroes to all TX DMA State head descriptor pointers. The TX port may then be enabled. To initiate packet transmission the host constructs transmit queues in memory (one or more packets for transmission) and then writes the appropriate TX DMA state head descriptor pointers. For each buffer added to a transmit queue, the host must initialize the TX buffer descriptor values as follows:

  1. Write the Next Descriptor Pointer with the 32-bit aligned address of the next descriptor in the queue (zero if last descriptor)
  2. Write the Buffer Pointer with the byte aligned address of the buffer data
  3. Write the Buffer Length with the number of bytes in the buffer
  4. Write the Buffer Offset with the number of bytes in the offset to the data (nonzero with SOP only)
  5. Set the SOP, EOP, and Ownership bits as appropriate
  6. Clear the End Of Queue bit

The port begins TX packet transmission on a given channel when the host writes the channel's TX queue head descriptor pointer with the address of the first buffer descriptor in the queue (nonzero value). Each channel may have one or more queues, so each channel may have one or more head descriptor pointers. The first buffer descriptor for each TX packet must have the Start of Packet (SOP) bit and the Ownership bit set to one by the host. The last buffer descriptor for each TX packet must have the End of Packet (EOP) bit set to one by the host. The port will transmit packets until all queued packets have been transmitted and the queue(s) are empty. When each packet transmission is complete, the port will clear the Ownership bit in the packet's SOP buffer descriptor and issue an interrupt to the host by writing the packet's last buffer descriptor address to the queue's TX DMA State Completion Pointer. The interrupt is generated by the write, regardless of the value written. When the last packet in a queue has been transmitted, the port sets the End Of Queue bit in the EOP buffer descriptor, clears the Ownership bit in the SOP Descriptor, zeroes the appropriate DMA state head descriptor pointer, and then issues a TX interrupt to the host by writing to the queue's associated TX completion pointer (address of the last buffer descriptor processed by the port). The port issues a maskable level interrupt (which may then be routed through external interrupt control logic to the host).

On interrupt from the port, the host processes the buffer queue, detecting transmitted packets by the status of the Ownership bit in the SOP buffer descriptor. If the Ownership bit is cleared to zero, then the packet has been transmitted and the host may reclaim the buffers associated with the packet. The host continues queue processing until the end of the queue or until a SOP buffer descriptor is read that contains a set Ownership bit indicating that the packet transmission is not complete. The host determines that all packets in the queue have been transmitted when the last packet in the queue has a cleared Ownership bit in the SOP buffer descriptor, the End of Queue bit is set in the last packet EOP buffer descriptor, and the Next Descriptor Pointer of the last packet EOP buffer descriptor is zero. The host acknowledges an interrupt by writing the address of the last buffer descriptor to the queue's associated TX Completion Pointer in the TX DMA State. If the host written buffer address value is different from the buffer address written by the port, then the level interrupt remains asserted. If the host written buffer address value is equal to the port written value, then the level interrupt is de-asserted. The port write to the completion pointer actually stores the value in the state register (RAM). The host written value is actually not written to the register location. The host written value is compared to the register contents (which was written by the port) and if the two values are equal, the interrupt is removed, otherwise the interrupt remains asserted. The host may process multiple packets previous to acknowledging an interrupt, or the host may acknowledge interrupts for every packet.

A mis-queued packet condition may occur when the host adds a packet to a queue for transmission as the port finishes transmitting the previous last packet in the queue. The mis-queued packet is detected by the host when queue processing detects a cleared Ownership bit in the SOP buffer descriptor, a set End of Queue bit in the EOP buffer descriptor, and a nonzero Next Descriptor Pointer in the EOP buffer descriptor. A mis-queued packet means that the port read the last EOP buffer descriptor before the host added the new last packet to the queue, so the port determined queue empty just before the last packet was added. The host corrects the mis-queued packet condition by initiating a new packet transfer for the mis-queued packet by writing the mis-queued packet's SOP buffer descriptor address to the appropriate DMA State TX Queue head Descriptor Pointer.

The host may add packets to the tail end of an active TX queue at any time by writing the Next Descriptor Pointer to the current last descriptor in the queue. If a TX queue is empty (inactive), the host may initiate packet transmission at any time by writing the appropriate TX DMA State head descriptor pointer. The host software should always check for and reinitiate transmission for mis-queued packets during queue processing on interrupt from the port. In order to preclude software underrun, the host should avoid adding buffers to an active queue for any TX packet that is not complete and ready for transmission.

The port determines that a packet is the last packet in the queue by detecting the End of Packet bit set with a zero Next Descriptor Pointer in the packet buffer descriptor. If the End of Packet bit is set and the Next Descriptor Pointer is nonzero, then the queue still contains one or more packets to be transmitted. If the EOP bit is set with a zero Next Descriptor Pointer, then the port will set the EOQ bit in the packet's EOP buffer descriptor and then zero the appropriate head descriptor pointer previous to interrupting the port (by writing the completion pointer) when the packet transmission is complete.

AM263x TX Queue Head DescriptorFigure 13-113 TX Queue Head Descriptor