SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
The Tx Buffers section can be configured to hold dedicated Tx Buffers as well as a Tx FIFO/Tx Queue. In case that the Tx Buffers section is shared by dedicated Tx buffers and a Tx FIFO/Tx Queue, the dedicated Tx Buffers start at the beginning of the Tx Buffers section followed by the buffers assigned to the Tx FIFO or Tx Queue. The Tx Handler makes difference between dedicated Tx Buffers and Tx FIFO/Tx Queue via the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields. The element size can be configured for storage of CAN FD messages with up to 64 bytes data field via the MCAN_TXESC register.
Figure 13-222 shows Tx Buffer element structure.
Table 13-274 shows Tx Buffer element field descriptions.
Word | Bits | Field Name | Description | ||
---|---|---|---|---|---|
T0 | 31 | ESI | Error State Indicator
Note: The ESI bit of the transmit buffer is or'ed with the error passive flag to decide the value of the ESI bit in the transmitted CAN FD frame. As required by the CAN FD protocol specification, an error active node may optionally transmit the ESI bit recessive, but an error passive node will always transmit the ESI bit recessive. | ||
30 | XTD | Extended Identifier
| |||
29 | RTR | Remote Transmission Request
Note: When RTR = 1, the MCAN module transmits a remote frame according to ISO11898-1:2015, even if the MCAN_CCCR[8] FDOE bit enables the transmission in CAN FD format. | |||
28-0 | ID[28-0] | Identifier Standard or extended identifier depending on XTD bit. A standard identifier has to be written to ID[28-18]. | |||
T1 | 31-24 | MM[7-0] | Message Marker Written by Host CPU during Tx Buffer configuration. Copied into Tx Event FIFO element for identification of Tx message status (see also MM[7-0] field in Table 13-275). | ||
23 | EFC | Event FIFO Control
| |||
22 | RES | Reserved | |||
21 | FDF | FD Format
| |||
20 | BRS | Bit Rate Switch
Note: ESI, FDF, and BRS bits are only evaluated when CAN FD operation is enabled vie the MCAN_CCCR[8] FDOE bit. BRS bit is only evaluated when in addition the MCAN_CCCR[9] BRSE = 1. | |||
19-16 | DLC[3-0] | Data Length Code
| |||
15-0 | RES | Reserved | |||
T2 | 31-24 | DB3[7-0] | Data Byte 3 | ||
23-16 | DB2[7-0] | Data Byte 2 | |||
15-8 | DB1[7-0] | Data Byte 1 | |||
7-0 | DB0[7-0] | Data Byte 0 | |||
T3 | 31-24 | DB7[7-0] | Data Byte 7 | ||
23-16 | DB6[7-0] | Data Byte 6 | |||
15-8 | DB5[7-0] | Data Byte 5 | |||
7-0 | DB4[7-0] | Data Byte 4 | |||
... | ... | ... | ... | ||
Tn | 31-24 | DBm[7-0] | Data Byte m | ||
23-16 | DBm-1[7-0] | Data Byte m-1 | |||
15-8 | DBm-2[7-0] | Data Byte m-2 | |||
7-0 | DBm-3[7-0] | Data Byte m-3 |
Note: Depending on the configuration of the element size (MCAN_TXESC), between two and sixteen 32-bit words (Tn = 3-17) are used for storage of a CAN message's data field.