Enhanced GPIO. The other functional mode setting for PRUs EGPIOs at PRU-ICSS top registers level are:
- PRU_ICSSM_GPCFG0 / PRU_ICSSM_GPCFG1[14]
PRU0_GPO_MODE (PRU0 or PRU1) — to select between direct or serial EGPO
output mode of operation.
- PRU_ICSSM_GPCFG0 / PRU_ICSSM_GPCFG1[25]
PRU0_GPO_SH_SEL (PRU0 or PRU1) — to select between the EGPO shadow registers
0 and 1 used for output shifting. For more details, refer to the Section 7.2.5.2.2.3.4, Enhanced General-Purpose Module Outputs (R30).
- PRU_ICSSM_GPCFG0 / PRU_ICSSM_GPCFG1[1-0]
PRU0_GPI_MODE (PRU0 or PRU1) — selects the EGPI input mode of operation (
selects between "direct input", "parallel capture", "28-bit shift" or
"MII_RT" modes).
- PRU_ICSSM_GPCFG0 / PRU_ICSSM_GPCFG1[13]
PRU0_GPI_SB (PRU0 or PRU1) — start bit event status for 28-bit EGPI input
shift mode. For more details, refer to the Section 7.2.5.2.2.3, Enhanced General-Purpose Module Inputs (R31).
PRUs scratchpad (SPAD)
memory priority and configuration related bits are located in the
PRU_ICSSM_SPP register.