SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
Several internal module events can generate an interrupt. Each interrupt has a status bit, an interrupt enable bit, and a signal status enable:
If an interrupt status is disabled in the MMC_IE register, then the corresponding interrupt request is not transmitted, and the value of the corresponding interrupt signal enable in the MMC_ISE register is ignored.
When an interrupt event occurs, the corresponding status bit is automatically set to 1 (the MMC/SD/SDIO host controller updates the status bit) in the MMC_STAT register. If later a mask is applied on the interrupt in the MMC_ISE register, the interrupt request is deactivated.
When the interrupt source has not been serviced, if the interrupt status is cleared in the MMC_STAT register and the corresponding mask is removed from the MMC_ISE register, the interrupt status is not asserted again in the MMC_STAT register and the MMC/SD/SDIOi host controller does not transmit an interrupt request.
If the buffer write ready interrupt (BWR) or the buffer read ready only interrupt (BRR) are not serviced and are cleared in the MMC_STAT register, and the corresponding mask is removed, then the MMC/SD/SDIOi host controller will wait for the service of the interrupt without updating the status MMC_STAT or transmitting an interrupt request.
Table 13-244 lists the event flags, and their mask, that can cause module interrupts.
| Event Flag | Event Mask | Map To | Description |
|---|---|---|---|
| MMC_STAT[29] BADA | MMC_IE[29] BADA_ENABLE | MMC_IRQ | Bad Access to Data space. This bit is set automatically to indicate a bad access to buffer when not allowed. This bit is set during a read access to the data register (MMC_DATA) while buffer reads are not allowed (MMC_PSTATE[11] BRE=0). This bit is set during a write access to the data register (MMC_DATA) while buffer writes are not allowed (MMC_STATE[10] BWE=0) |
| MMC_STAT[28] CERR | MMC_IE[28] CERR_ENABLE | MMC_IRQ | Card Error. This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response errors MMC_CSRE is set. There is not card detection for auto CMD12 command. |
| MMC_STAT[25] ADMAE | MMC_IE[25] ADMAE_ENABLE | MMC_IRQ | ADMA error. This bit is set when the host controller detects errors during ADMA based data transfer. The stat of the ADMA at an error occurrence is saved in the ADMA Error Status Register. In addition, the host controller generates this interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. |
| MMC_STAT[24] ACE | MMC_IE[24] ACE_ENABLE | MMC_IRQ | Auto CMD12 error. This bit is set automatically when one of the bits in Auto CMD12 Error status register has changed from 0 to 1 |
| MMC_STAT[22] DEB | MMC_IE[22] DEB_ENABLE | MMC_IRQ | Data End Bit error. This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode. |
| MMC_STAT[21] DCRC | MMC_IE[21] DCRC_ENABLE | MMC_IRQ | Data CRC error. This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position "010" token during a block write command. |
| MMC_STAT[20] DTO | MMC_IE[20] DTO_ENABLE | MMC_IRQ | Data Timeout error. This bit is set automatically according to the following conditions: A) busy timeout for R1b, R5b response. B) busy timeout after write CRC status. C) write CRC status timeout, or D) read data timeout. |
| MMC_STAT[19] CIE | MMC_IE[19] CIE_ENABLE | MMC_IRQ | Command Index Error. This bit is set automatically when response index differs from corresponding command index previously emitted. The check is enabled through MMC_CMD[20] CICE bit. |
| MMC_STAT[18] CEB | MMC_IE[18] CEB_ENABLE | MMC_IRQ | Command End Bit error. This bit is set automatically when detecting a 0 at the end bit position of a command response. |
| MMC_STAT[17] CCRC | MMC_IE[17] CCRC_ENABLE | MMC_IRQ | Command CRC error. This bit is set automatically when there is a CRC7 error in the command response. CRC check is enabled through the MMC_CMD[19] CCCE bit. |
| MMC_STAT[16] CTO | MMC_IE[16] CTO_ENABLE | MMC_IRQ | Command Timeout error. This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands the reply within 5 clock cycles, the timeout is still detected at 64 clock cycles. |
| MMC_STAT[15] ERRI | MMC_IE[15] ERRI_ENABLE | MMC_IRQ | Error Interrupt. If any of the bits in the Error Interrupt Status register (MMC_STAT[24:15]) are set, the this bit is set to 1. |
| MMC_STAT[10] BSR | MMC_IE[10] BSR_ENABLE | MMC_IRQ | Boot Status Received interrupt. This bit is set automatically when MMC_CON[18] BOOT_CF0 is set to 1 or 2h and boot status is received on the dat0 line. This interrupt is only used for MMC cards. |
| MMC_STAT[8] CIRQ | MMC_IE[8] CIRQ_ENABLE | MMC_IRQ | Card Interrupt. This bit is only used for SD, SDIO, and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wake-up). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drive CMD line to zero during one cycle after data transmission end. |
| MMC_STAT[5] BRR | MMC_IE[5] BRR_ENABLE | MMC_IRQ | Buffer Read ready. This bit is set automatically during a read operation to the card when one block specified by MMC_BLK[10:0] BLEN is completely written in the buffer. It indicates that the memory card has filled out the buffer and the local host needs to empty the buffer by reading it. |
| MMC_STAT[4] BWR | MMC_IE[4] BWR_ENABLE | MMC_IRQ | Buffer Write ready. This bit is automatically set during a write operation to the card when the host can write a complete block as specified by MMC_BLK[10:0] BLEN. It indicates that the memory card has emptied one block from the bugger and the local host is able to write one block of data into the buffer. |
| MMC_STAT[3] DMA | MMC_IE[3] DMA_ENABLE | MMC_IRQ | DMA interrupt. This status is set when an interrupt is required in the ADMA instruction and after the data transfer is complete. |
| MMC_STAT[2] BGE | MMC_IE[2] BGE_ENABLE | MMC_IRQ | Block Gap event. When a stop at block gap is requested (MMC_HCTL[16] SBGR), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. |
| MMC_STAT[1] TC | MMC_IE[1] TC_ENABLE | MMC_IRQ | Transfer completed. This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap requested (MMC_HCTL[16 SBGR). In read mode this bit is automatically set on completion of a read transfer (MMC_PSTATE[9] RTA). In write mode, this bit is automatically set on completion of the DAT line use (MMC_PSTATE[2] DLA). |
| MMC_STAT[0] CC | MMC_IE[0] CC_ENABLE | MMC_IRQ | Command complete. This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMC_PSTATE[0] CMDI). If the command is a type for which no response is expected, then the command complete interrupt is generated at the end of the command. A command timeout error (MMC_STAT[16] CTO) has higher priority than command complete (MMC_STAT[0] CC). If a response is expected but none is received, the a Command Timeout error is detected and signaled instead of the Command Complete interrupt. |