SPRUJ21D October   2022  – February 2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 EMC, EMI, and ESD Compliance
  5. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J14] With LED for Status [LD3]
      2. 2.1.2 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW1]
      2. 2.2.2 Reset Pushbutton [SW2]
      3. 2.2.3 User Pushbutton [SW3] With User LED Indication [LD2]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J4] With LED for Status [LD1]
      2. 2.3.2 Gigabit Ethernet [J8] With Integrated LEDs for Status
      3. 2.3.3 JTAG/Emulation Interface [J9]
      4. 2.3.4 USB3.1 Gen1 Interfaces [J10] [J12]
      5. 2.3.5 M.2 Key E Connector [J11] for Wi-Fi Networking Modules
      6. 2.3.6 Stacked DisplayPort and HDMI Type A [J13]
      7. 2.3.7 M.2 Key M Connector [J22] for SSD Modules
      8. 2.3.8 MicroSD Card Cage [J23]
    4. 2.4 Expansion Interfaces
      1. 2.4.1 Heatsink [ACC1] With [J16] Fan Header
      2. 2.4.2 CAN-FD Connector(s) [J1] [J2] [J5] [J6]
      3. 2.4.3 Expansion Header [J3]
      4. 2.4.4 Camera Interface, 15-Pin Flex Connectors [J18] [J19]
      5. 2.4.5 Camera Interface, 40-Pin High Speed [J24]
      6. 2.4.6 Automation and Control Connector [J25]
  6. 3Mechanicals
  7. 4Circuit Details
    1. 4.1 Top Level Diagram
    2. 4.2 Interface Mapping
    3. 4.3 I2C Address Mapping
    4. 4.4 GPIO Mapping
    5. 4.5 Identification EEPROM
  8. 5Usage Notes and Advisories
    1. 5.1 Usage Notes
    2. 5.2 Advisories
  9. 6References
  10. 7Revision History

4.5 Identification EEPROM

The SK-TDA4VM board identified and revision information are stored in an on-board EEPROM. The first 259 bytes of memory are pre-programmed with EVM identification information. The format of that data is provided in Table 4-4. The remaining 32509 bytes are available for data or code storage.

The EEPROM is accessible from WKUP I2C0 port of TDA4VM processor at address 0x51.

Table 4-4 Board ID Information
Field Name Offset / Size Value Comments
MAGIC 0000 / 4B 0xEE3355AA Header Identifier
M_TYPE 0004 /1B 0x1 Fixed length and variable position board ID header
M_LENGTH 0005 /2B 0x37 Size of payload
B_TYPE 0007 /1B 0x10 Payload type
B_LENGTH 0008 /2B 0x2E Offset to next header
B_NAME 000A /16B J721EX-EAIK Name of the board
DESIGN_REV 001A /2B E2 Revision number of the design
PROC_NBR 001C /4B 112 PROC number
VARIANT 0020 /2B 1 Design variant number
PCB_REV 0022 /2B E2 Revision number of the PCB
SCHBOM_REV 0024 /2B 0 Revision number of the schematic
SWR_REV 0026 /2B 1 First software release number
VENDORID 0028 /2B 1
BUILD_WK 002A /2B Week of the year of production
BUILD_YR 002C /2B Year of production
BOARDID 002E /6B 0
SERIAL_NBR 0034 /4B Incrementing board number
DDR_INFO TYPE 1
Length 2 Offset to next header
DDR control 2 DDR Control Word
MAC_ADDR TYPE 1 Payload type
Length 2 Size of payload
MAC control 2 MAC header control word
MAC_adrs 192
END_LIST TYPE 1 End Marker