SPRUJ21D October   2022  – February 2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 EMC, EMI, and ESD Compliance
  5. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J14] With LED for Status [LD3]
      2. 2.1.2 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW1]
      2. 2.2.2 Reset Pushbutton [SW2]
      3. 2.2.3 User Pushbutton [SW3] With User LED Indication [LD2]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J4] With LED for Status [LD1]
      2. 2.3.2 Gigabit Ethernet [J8] With Integrated LEDs for Status
      3. 2.3.3 JTAG/Emulation Interface [J9]
      4. 2.3.4 USB3.1 Gen1 Interfaces [J10] [J12]
      5. 2.3.5 M.2 Key E Connector [J11] for Wi-Fi Networking Modules
      6. 2.3.6 Stacked DisplayPort and HDMI Type A [J13]
      7. 2.3.7 M.2 Key M Connector [J22] for SSD Modules
      8. 2.3.8 MicroSD Card Cage [J23]
    4. 2.4 Expansion Interfaces
      1. 2.4.1 Heatsink [ACC1] With [J16] Fan Header
      2. 2.4.2 CAN-FD Connector(s) [J1] [J2] [J5] [J6]
      3. 2.4.3 Expansion Header [J3]
      4. 2.4.4 Camera Interface, 15-Pin Flex Connectors [J18] [J19]
      5. 2.4.5 Camera Interface, 40-Pin High Speed [J24]
      6. 2.4.6 Automation and Control Connector [J25]
  6. 3Mechanicals
  7. 4Circuit Details
    1. 4.1 Top Level Diagram
    2. 4.2 Interface Mapping
    3. 4.3 I2C Address Mapping
    4. 4.4 GPIO Mapping
    5. 4.5 Identification EEPROM
  8. 5Usage Notes and Advisories
    1. 5.1 Usage Notes
    2. 5.2 Advisories
  9. 6References
  10. 7Revision History

2.4.5 Camera Interface, 40-Pin High Speed [J24]

The EVM includes a 40-pin (2x20, 2.54 mm pitch) high speed camera interface [J24]. The expansion connector supports two CSI-2 (4 Lanes each), power, and control signals (I2C, GPIO, and so forth): All control signals are configurable for 3.3V or 1.8V voltage levels.

Table 2-13 Camera IO Voltage Control
GPIO0 #118 (Pin Y1) Camera IO Level
Low or ‘0’ 1.8V (Default)
High or ‘1’ 3.3V
Table 2-14 40-Pin High-Speed Camera Expansion Pin Definition [J24]
Pin # Pin Name Description (TDA4VM Pin #) Dir
1 Power Output
2 I2C_SCL I2C Bus #3, Clock (T26) Bi-Dir
3 Power Output
4 I2C_SDA I2C Bus #3, Data (T25) Bi-Dir
5 CSI0_CLK_P CSI Port 0 Clock Input
6 GPIO/PWMA GPIO0 #74 (AG26) Bi-Dir
7 CSI0_CLK_N CSI Port 0 Clock Input
8 GPIO/PWMB GPIO0 #75 (AF27) Bi-Dir
9 CSI0_D0_P CSI Port 0 Data Lane 0 Input
10 REFCLK REFCLK2 (W26) Bi-Dir
11 CSI0_D0_N CSI Port 0 Data Lane 0 Input
12 GND Ground
13 CSI0_D1_P CSI Port 0 Data Lane 1 Input
14 RESETz GPIO0 #79 (AG29) Output
15 CSI0_D1_N CSI Port 0 Data Lane 1 Input
16 GND Ground
17 CSI0_D2_P CSI Port 0 Data Lane 2 Input
18 GPIO GPIO0 #76 (AF26) Bi-Dir
19 CSI0_D2_N CSI Port 0 Data Lane 2 Input
20 GPIO GPIO0 #77 (AE25) Bi-Dir
21 CSI0_D3_P CSI Port 0 Data Lane 3 Input
22 GPIO GPIO0 #78 (AF29) Bi-Dir
23 CSI0_D3_N CSI Port 0 Data Lane 3 Input
24 GND Ground
25 CSI1_CLK_P CSI Port 1 Clock Input
26 CSI1_D3_P CSI Port 1 Data Lane 3 Input
27 CSI1_CLK_N CSI Port 1 Clock Input
28 CSI1_D3_N CSI Port 1 Data Lane 3 Input
29 CSI1_D0_P CSI Port 1 Data Lane 0 Input
30 Power Power, 3.3V Output
31 CSI1_D0_N CSI Port 1 Data Lane 0 Input
32 Power Power, 3.3V Output
33 CSI1_D1_P CSI Port 1 Data Lane 1 Input
34 Power Power, 3.3V Output
35 CSI1_D1_N CSI Port 1 Data Lane 1 Input
36 Power Power, 3.3V Output
37 CSI1_D2_P CSI Port 1 Data Lane 2 Input
38 Power Power, IO Level (1.8 or 3.3V) Output
39 CSI1_D2_N CSI Port 1 Data Lane 2 Input
40 Power Power, IO Level (1.8 or 3.3V) Output
Note: In the DIR column, output is to the expansion module, input is from the expansion module. Bi-Dir signals can be configured as either input or output.