SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Interrupt Enable Clear Shadow Register. Write 1 to clear interrupt enable bits.
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Instance Name | Physical Address |
---|---|
MCAN0 | 5260 8014h |
MCAN1 | 5261 8014h |
MCAN2 | 5262 8014h |
MCAN3 | 5263 8014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NU4 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NU4 | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NU4 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NU4 | IECS | ||||||
R | W | ||||||
0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:1 | NU4 | R | 0h | Reserved |
0 | IECS | W | 0h | External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. [IECS - Interrupt Enable Clear Shadow Register] |