SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.12.2.17 CFG_DBTP Register

12.2.17.1 CFG_DBTP Register (Offset = 20Ch) [reset = A33h]

Data Bit Timing & Prescaler Register.
Configuration of data phase bit timing, transmitter delay compensation enable. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 MCAN functional clock periods. tq = (MCAN_DBTP[20-16] DBRP + 1) mtq (minimum time quantum = CAN clock period (MCAN functional clock)). The MCAN_DBTP[12-8] DTSEG1 field is the sum of Prop_Seg and Phase_Seg1. The MCAN_DBTP[7-4] DTSEG2 field is Phase_Seg2. Therefore the length of the bit time is (programmed values) [MCAN_DBTP[12-8] DTSEG1 + MCAN_DBTP[7-4] DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
Note: With a CAN clock (MCAN functional clock) of 8 MHz, the reset value of 0000 0A33h configures the MCAN module for a data phase bit rate of 500 kbit/s.
Note: The bit rate configured for the CAN FD data phase via the MCAN_DBTP register must be higher or equal to the bit rate configured for the arbitration phase via the MCAN_DBTP register.

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Table 5-1406 Instance Table

Instance Name	Physical Address
MCAN0	5260 820Ch
MCAN1	5261 820Ch
MCAN2	5262 820Ch
MCAN3	5263 820Ch

Figure 5-693 CFG_DBTP Name Register

31	30	29	28	27	26	25	24
NU13
R
0h
23	22	21	20	19	18	17	16
TDC	NU12		DBRP
R/W	R		R/W
0h	0h		0h
15	14	13	12	11	10	9	8
NU11			DTSEG1
R			R/W
0h			Ah
7	6	5	4	3	2	1	0
DTSEG2				DSJW
R/W				R/W
3h				3h

Table 5-1407 CFG_DBTP Register Field Descriptions

Bit	Field	Type	Reset	Description
31:24	NU13	R	0h	Reserved
23	TDC	R/W	0h	Transmitter Delay Compensation 1'b0 = Transmitter Delay Compensation disabled 1'b1 = Transmitter Delay Compensation enabled
22:21	NU12	R	0h	Reserved
20:16	DBRP	R/W	0h	Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
15:13	NU11	R	0h	Reserved
12:8	DTSEG1	R/W	Ah	Data time segment before smaple point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
7:4	DTSEG2	R/W	3h	Data time segment after sample point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
3:0	DSJW	R/W	3h	Data resynchronization Jump Width. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.