SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.12.2.20 CFG_CCCR Register

12.2.20.1 CFG_CCCR Register (Offset = 218h) [reset = 1h]

CC Control Register. Operation mode configuration.

Table 5-1412 Instance Table

Instance Name	Physical Address
MCAN0	5260 8218h
MCAN1	5261 8218h
MCAN2	5262 8218h
MCAN3	5263 8218h

Figure 5-696 CFG_CCCR Name Register

31	30	29	28	27	26	25	24
NU18
R/W
0h
23	22	21	20	19	18	17	16
NU18
R/W
0h
15	14	13	12	11	10	9	8
NU18	TXP	EFBI	PXHD	NU17		BRSE	FDOE
R/W	R/W	R/W	R/W	R		R/W	R/W
0h	0h	0h	0h	0h		0h	0h
7	6	5	4	3	2	1	0
TEST	DAR	MON	CSR	CSA	ASM	CCE	INIT
R/W	R/W	R/W	R/W	R	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	1h

Table 5-1413 CFG_CCCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:15	NU18	R/W	0h	Reserved
14	TXP	R/W	0h	Transmit Pause If this bit is set, the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame(see Tx Handling) . 1'b0 = Transmit pause disabled 1'b1 = Transmit pause enabled
13	EFBI	R/W	0h	Edge Filtering durign Bus Integration 1'b0 = Edge filtering disabled 1'b1 = Two consecutive dominant tq required to detect an edge for hard synchronization
12	PXHD	R/W	0h	Protocol Exception Handling Disable 1'b0 = Protocol exception handling enabled 1'b1 = Protocol exception handling disabled Note: When protocol exception handling is disabled, the MCAN module will transmit an error frame when it detects a protocol exception condition.
11:10	NU17	R	0h	Reserved
9	BRSE	R/W	0h	Bit Rate Switch Enable 1'b0 = Bit rate switching for transmissions disabled 1'b1 = Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 1'b0, the MCAN_CCCR[9] BRSE bit is not evaluated.
8	FDOE	R/W	0h	FD Operation Enable 1'b0 = FD operation disabled 1'b1 = FD operation enabled
7	TEST	R/W	0h	Test Mode enable 1'b0 = Normal operation. The MCAN_TEST register holds reset values. 1'b1 = Test Mode. Write access to the MCAN_TEST register enabled
6	DAR	R/W	0h	Disable Automatic Regransmission 1'b0 = Automatic retransmission of messages not transmitted successfully enabled 1'b1 = Automatic retransmission disabled
5	MON	R/W	0h	Bus Monitoring Mode The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. 1'b0 = Bus Monitoring Mode is disabled 1'b1 = Bus Monitoring Mode is enabled
4	CSR	R/W	0h	Clock Stop Request 1'b0 = No clock stop is requested 1'b1 = Clock stop requested. When clock stop is requested, first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and the CAN bus reached idle.
3	CSA	R	0h	Clock Stop Acknowledge 1'b0 = No clock stop acknowledged 1'b1 = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock
2	ASM	R/W	0h	Restriced Operation Mode The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation Mode, see Restricted Operation Mode. 1'b0 = Normal CAN operation 1'b1 = Restricted Operation Mode active
1	CCE	R/W	0h	Configuration Change Enable 1'b0 = The Host CPU has no write access to the protected configuration registers 1'b1 = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1)
0	INIT	R/W	1h	Initialization 1'b0 = Normal Operation 1'b1 = Initialization is started Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the software has to assure that the previous value written to the MCAN_CCCR[0] INIT bit has been accepted by Reading the MCAN_CCCR[0] INIT bit before setting the MCAN_CCCR[0] INIT bit to a new value.