SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

12.2.54.1 CFG_RXF0C Register (Offset = 2A0h) [reset = 0h]

Rx FIFO 0 Configuration register. FIFO 0 operation mode, watermark, size and start address.

Table 5-1480 Instance Table

Figure 5-730 CFG_RXF0C Name Register

Table 5-1481 CFG_RXF0C Register Field Descriptions

Bit	Field	Type	Reset	Description
31	F0OM	R/W	0h	Rx FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 0 blocking mode 1'b1 = FIFO 0 overwrite mode
30:24	F0WM	R/W	0h	Rx FIFO 0 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W) > 7'h40 (64) = Watermark interrupt disabled
23	NU42_1	R	0h	Reserved
22:16	F0S	R/W	0h	Rx FIFO 0 Size 7'h00 = No Rx FIFO 0 7'h01-7'h40 (1-64) = Number of Rx FIFO 0 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1.
15	NU42	R	0h	Reserved
14:2	F0SA	R/W	0h	Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Message RAM Configuration).
1:0	NU41	R	0h	Reserved