SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Tx Buffer Configuration register. Configure Tx FIFO/Queue mode, Tx FIFO/Queue size, number of dedicated Tx buffers, Tx buffer start address.
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Instance Name | Physical Address |
---|---|
MCAN0 | 5260 82C0h |
MCAN1 | 5261 82C0h |
MCAN2 | 5262 82C0h |
MCAN3 | 5263 82C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NU61 | TFQM | TFQS | |||||
R | R | R | |||||
0h | 0h | 0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NU60 | NDTB | ||||||
R | R | ||||||
0h | 0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TBSA | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBSA | NU59 | ||||||
R | R | ||||||
0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NU61 | R | 0h | Reserved |
30 | TFQM | R | 0h | Tx FIFO/Queue Mode 1'b0 = Tx FIFO operation 1'b1 = Tx Queue operation |
29:24 | TFQS | R | 0h | Transmit FIFO/Queue Size 6'h00 = No Tx FIFO/Queue 6'b01-6'h20 (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 6'h20 (32) = Values greater than 32 are interpreted as 32 |
23:22 | NU60 | R | 0h | Reserved |
21:16 | NDTB | R | 0h | Number of Dedicated Transmit Buffers 6'h00 = No Dedicated Tx Buffers 6'h01-6'h20 (1-32) = Number of Dedicated Tx Buffers > 6'h20 (32) = Values greater than 32 are interpreted as 32 |
15:2 | TBSA | R | 0h | Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Message RAM Configuration). Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. |
1:0 | NU59 | R | 0h | Reserved |