SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.12.2.63 CFG_TXFQS Register

12.2.63.1 CFG_TXFQS Register (Offset = 2C4h) [reset = 0h]

Tx FIFO/Queue Status register. Tx FIFO/Queue full indication and put index, Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (the MCAN_TXBRP register not yet updated).

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Table 5-1498 Instance Table

Instance Name	Physical Address
MCAN0	5260 82C4h
MCAN1	5261 82C4h
MCAN2	5262 82C4h
MCAN3	5263 82C4h

Figure 5-739 CFG_TXFQS Name Register

31	30	29	28	27	26	25	24
NU64
R
0h
23	22	21	20	19	18	17	16
NU64		TFQF	TFQPI
R		R	R
0h		0h	0h
15	14	13	12	11	10	9	8
NU63			TFGI
R			R
0h			0h
7	6	5	4	3	2	1	0
NU62		TFFL
R		R
0h		0h

Table 5-1499 CFG_TXFQS Register Field Descriptions

Bit	Field	Type	Reset	Description
31:22	NU64	R	0h	Reserved
21	TFQF	R	0h	Tx FIFO/Queue Full
20:16	TFQPI	R	0h	Tx FIFO/Queue Put Index
15:13	NU63	R	0h	Reserved
12:8	TFGI	R	0h	Tx Queue Get Index
7:6	NU62	R	0h	Reserved
5:0	TFFL	R	0h	Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field, range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1'b1). Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.