SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

12.2.74.1 CFG_TXEFC Register (Offset = 2F0h) [reset = 0h]

Tx Event FIFO Configuration register. Tx event FIFO watermark, size and start address.

Table 5-1520 Instance Table

Figure 5-750 CFG_TXEFC Name Register

Table 5-1521 CFG_TXEFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	NU68	R/W	0h	Reserved
29:24	EFWM	R/W	0h	Event FIFO Watermark 6'h00 = Watermark interrupt disabled 6'h01-6'h20 (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW) > 6'h20 (32) = Watermark interrupt disabled
23:22	NU67	R/W	0h	Reserved
21:16	EFS	R/W	0h	Event FIFO Size 6'h00 = Tx Event FIFO disabled 6'h01-6'h20 (1-32) = Number of Tx Event FIFO elements > 6'h20 (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1.
15:2	EFSA	R/W	0h	Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Message RAM Configuration).
1:0	NU66	R/W	0h	Reserved