SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

12.2.75.1 CFG_TXEFS Register (Offset = 2F4h) [reset = 0h]

Tx Event FIFO Status register. Tx event FIFO element lost/full indication, put index, get index, and fill level.

Table 5-1522 Instance Table

Figure 5-751 CFG_TXEFS Name Register

Table 5-1523 CFG_TXEFS Register Field Descriptions

Bit	Field	Type	Reset	Description
31:26	NU72	R	0h	Reserved
25	TEFL	R	0h	Tx Event FIFO Element Lost This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset, this bit is also reset. 1'b0 = No Tx Event FIFO element lost 1'b1 = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
24	EFF	R	0h	Event FIFO Full
23:21	NU71	R	0h	Reserved
20:16	EFPI	R	0h	Event FIFO Put Index
15:13	NU70	R	0h	Reserved
12:8	EFGI	R	0h	Event FIFO Get Index
7:6	NU69	R	0h	Reserved
5:0	EFFL	R	0h	Event FIFO FIll Level