SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

12.2.76.1 CFG_TXEFA Register (Offset = 2F8h) [reset = 0h]

Tx Event FIFO Acknowledge register. Tx event FIFO acknowledge last index of read elements, updates get index and fill level.

Table 5-1524 Instance Table

Figure 5-752 CFG_TXEFA Name Register

Table 5-1525 CFG_TXEFA Register Field Descriptions

Bit	Field	Type	Reset	Description
31:5	NU73	R	0h	Reserved
4:0	EFAI	R	0h	Event FIFO Acknowledge Index After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event FIFO Get Index MCAN_TXEFS[12-8] EFGI field to the MCAN_TXEFA[4-0] EFAI field + 1 and update the Event FIFO Fill Level MCAN_TXEFS[5-0] EFFL field.