SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Offset | Length | Register Name | MCAN0 Physical Address | MCAN1 Physical Address | MCAN2 Physical Address |
---|---|---|---|---|---|
0h | 32 | ECC_REV | 5270 0000h | 5270 1000h | 5270 2000h |
8h | 32 | ECC_VECTOR | 5270 0008h | 5270 1008h | 5270 2008h |
Ch | 32 | ECC_STAT | 5270 000Ch | 5270 100Ch | 5270 200Ch |
14h | 32 | ECC_CTRL | 5270 0014h | 5270 1014h | 5270 2014h |
18h | 32 | ECC_ERR_CTRL1 | 5270 0018h | 5270 1018h | 5270 2018h |
1Ch | 32 | ECC_ERR_CTRL2 | 5270 001Ch | 5270 101Ch | 5270 201Ch |
20h | 32 | ECC_ERR_STAT1 | 5270 0020h | 5270 1020h | 5270 2020h |
24h | 32 | ECC_ERR_STAT2 | 5270 0024h | 5270 1024h | 5270 2024h |
28h | 32 | ECC_ERR_STAT3 | 5270 0028h | 5270 1028h | 5270 2028h |
3Ch | 32 | ECC_SEC_EOI_REG | 5270 003Ch | 5270 103Ch | 5270 203Ch |
40h | 32 | ECC_SEC_STATUS_REG0 | 5270 0040h | 5270 1040h | 5270 2040h |
80h | 32 | ECC_SEC_ENABLE_SET_REG0 | 5270 0080h | 5270 1080h | 5270 2080h |
C0h | 32 | ECC_SEC_ENABLE_CLR_REG0 | 5270 00C0h | 5270 10C0h | 5270 20C0h |
13Ch | 32 | ECC_DED_EOI_REG | 5270 013Ch | 5270 113Ch | 5270 213Ch |
140h | 32 | ECC_DED_STATUS_REG0 | 5270 0140h | 5270 1140h | 5270 2140h |
180h | 32 | ECC_DED_ENABLE_SET_REG0 | 5270 0180h | 5270 1180h | 5270 2180h |
1C0h | 32 | ECC_DED_ENABLE_CLR_REG0 | 5270 01C0h | 5270 11C0h | 5270 21C0h |
200h | 32 | ECC_AGGR_ENABLE_SET | 5270 0200h | 5270 1200h | 5270 2200h |
204h | 32 | ECC_AGGR_ENABLE_CLR | 5270 0204h | 5270 1204h | 5270 2204h |
208h | 32 | ECC_AGGR_STATUS_SET | 5270 0208h | 5270 1208h | 5270 2208h |
20Ch | 32 | ECC_AGGR_STATUS_CLR | 5270 020Ch | 5270 120Ch | 5270 220Ch |
Offset | Length | Register Name | MCAN3 Physical Address |
---|---|---|---|
0h | 32 | ECC_REV | 5270 3000h |
8h | 32 | ECC_VECTOR | 5270 3008h |
Ch | 32 | ECC_STAT | 5270 300Ch |
14h | 32 | ECC_CTRL | 5270 3014h |
18h | 32 | ECC_ERR_CTRL1 | 5270 3018h |
1Ch | 32 | ECC_ERR_CTRL2 | 5270 301Ch |
20h | 32 | ECC_ERR_STAT1 | 5270 3020h |
24h | 32 | ECC_ERR_STAT2 | 5270 3024h |
28h | 32 | ECC_ERR_STAT3 | 5270 3028h |
3Ch | 32 | ECC_SEC_EOI_REG | 5270 303Ch |
40h | 32 | ECC_SEC_STATUS_REG0 | 5270 3040h |
80h | 32 | ECC_SEC_ENABLE_SET_REG0 | 5270 3080h |
C0h | 32 | ECC_SEC_ENABLE_CLR_REG0 | 5270 30C0h |
13Ch | 32 | ECC_DED_EOI_REG | 5270 313Ch |
140h | 32 | ECC_DED_STATUS_REG0 | 5270 3140h |
180h | 32 | ECC_DED_ENABLE_SET_REG0 | 5270 3180h |
1C0h | 32 | ECC_DED_ENABLE_CLR_REG0 | 5270 31C0h |
200h | 32 | ECC_AGGR_ENABLE_SET | 5270 3200h |
204h | 32 | ECC_AGGR_ENABLE_CLR | 5270 3204h |
208h | 32 | ECC_AGGR_STATUS_SET | 5270 3208h |
20Ch | 32 | ECC_AGGR_STATUS_CLR | 5270 320Ch |