SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
AGGR interrupt enable set Register.
Return to Summary Table
Instance Name | Physical Address |
---|---|
MCAN0 | 5270 0200h |
MCAN1 | 5270 1200h |
MCAN2 | 5270 2200h |
MCAN3 | 5270 3200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NU15 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NU15 | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NU15 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NU15 | TIMEOUT | PARITY | |||||
R | R/W | R/W | |||||
0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:2 | NU15 | R | 0h | Reserved |
1 | TIMEOUT | R/W | 0h | Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. |
0 | PARITY | R/W | 0h | Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. |