SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.12.2.97 ECC_AGGR_STATUS_SET Register

12.2.97.1 ECC_AGGR_STATUS_SET Register (Offset = 208h) [reset = 0h]

AGGR interrupt status set Register.

Table 5-1566 Instance Table

Instance Name	Physical Address
MCAN0	5270 0208h
MCAN1	5270 1208h
MCAN2	5270 2208h
MCAN3	5270 3208h

Figure 5-773 ECC_AGGR_STATUS_SET Name Register

31	30	29	28	27	26	25	24
NU17
R
0h
23	22	21	20	19	18	17	16
NU17
R
0h
15	14	13	12	11	10	9	8
NU17
R
0h
7	6	5	4	3	2	1	0
NU17				TIMEOUT		PARITY
R				R/W		R/W
0h				0h		0h

Table 5-1567 ECC_AGGR_STATUS_SET Register Field Descriptions

Bit	Field	Type	Reset	Description
31:4	NU17	R	0h	Reserved
3:2	TIMEOUT	R/W	0h	2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register increments that many from the timeout fields. If the value written is less than the current value of the counter, then the pending level interrupt stays asserted. . If this register goes from 0 ot non zero a level interrupt will be asserted as well as a pulse interrupt. If the value was non zero to non zero then the level interrupt would remain asserted, but no new pulse interrupt would be asserted. You must write the eoi register to get a new pulse interrupt.
1:0	PARITY	R/W	0h	2-bit saturating counter of the number of parity errors that have occurred since last cleared. 2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register incrments that many from the parity fields. If the value written is less than the current value of the counter, then the pending level interrupt stays asserted. If this register goes from 0 ot non zero a level interrupt will be asserted as well as a pulse interrupt. If the value was non zero to non zero then the level interrupt would remain asserted, but no new pulse interrupt would be asserted. You must write the eoi register to get a new pulse interrupt.