SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Error Details Register.
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Instance Name | Physical Address |
---|---|
EDMA0 | 52A6 012Ch |
EDMA1 | 52A4 012Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TCCHEN | TCINTEN | |||||
NONE | R | R | |||||
0h | 0h | 0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TCC | ||||||
NONE | R | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||
NONE | R | ||||||
0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:18 | RESERVED | NONE | 0h | Reserved |
17 | TCCHEN | R | 0h | Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error. |
16 | TCINTEN | R | 0h | Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error. |
15:14 | RESERVED | NONE | 0h | Reserved |
13:8 | TCC | R | 0h | Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error. |
7:4 | RESERVED | NONE | 0h | Reserved |
3:0 | STAT | R | 0h | Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec. |