SPRUJ42 User guide | TI.com

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.4.2.140 TPTC_SAOPT Register

4.2.140.1 TPTC_SAOPT Register (Offset = 240h) [reset = 0h]

Src Actv Set Options.

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Table 4-1670 Instance Table

Instance Name	Physical Address
EDMA0	52A6 0240h
EDMA1	52A4 0240h

Figure 4-817 TPTC_SAOPT Name Register

31	30	29	28	27	26	25	24
RESERVED		DBG_ID		RESERVED
NONE		R		NONE
0h		0h		0h
23	22	21	20	19	18	17	16
RESERVED	TCCHEN	RESERVED	TCINTEN	RESERVED		TCC
NONE	R	NONE	R	NONE		R
0h	0h	0h	0h	0h		0h
15	14	13	12	11	10	9	8
TCC				RESERVED	FWID
R				NONE	R
0h				0h	0h
7	6	5	4	3	2	1	0
RESERVED	PRI			RESERVED		DAM	SAM
NONE	R			NONE		R	R
0h	0h			0h		0h	0h

Table 4-1671 TPTC_SAOPT Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED	NONE	0h	Reserved
29:28	DBG_ID	R	0h	Debug ID Value driven on the read [tptc_r_dbg_channel_id] and write [tptc_w_dbg_channel_id] command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature.
27:23	RESERVED	NONE	0h	Reserved
22	TCCHEN	R	0h	Transfer complete chaining enable: 0:Transfer complete chaining is disabled. 1:Transfer complete chaining is enabled.
21	RESERVED	NONE	0h	Reserved
20	TCINTEN	R	0h	Transfer complete interrupt enable: 0:Transfer complete interrupt is disabled. 1:Transfer complete interrupt is enabled.
19:18	RESERVED	NONE	0h	Reserved
17:12	TCC	R	0h	Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module.
11	RESERVED	NONE	0h	Reserved
10:8	FWID	R	0h	FIFO width control: Applies if either SAM or DAM is set to FIFO mode.
7	RESERVED	NONE	0h	Reserved
6:4	PRI	R	0h	Transfer Priority: 0:Priority 0 - Highest priority 1:Priority 1 ... 7:Priority 7 - Lowest priority
3:2	RESERVED	NONE	0h	Reserved
1	DAM	R	0h	Destination Address Mode within an array: 0:INCR Dst addressing within an array increments. 1:FIFO Dst addressing within an array wraps around upon reaching FIFO width.
0	SAM	R	0h	Source Address Mode within an array: 0:INCR Src addressing within an array increments. 1:FIFO Src addressing within an array wraps around upon reaching FIFO width.